| /src/sys/arch/mips/cavium/ |
| octeon_intr.c | 542 const uint32_t mbox_mask = (uintptr_t) arg; local in function:octeon_ipi_intr
543 uint32_t ipi_mask = mbox_mask;
545 KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
546 "mbox_mask %#"PRIx32" cpl %d", mbox_mask, ci->ci_cpl);
555 KASSERT(__SHIFTOUT(ipi_mask, mbox_mask) < __BIT(NIPIS));
577 ipi_process(ci, __SHIFTOUT(ipi_mask, mbox_mask));
|
| /src/sys/arch/evbmips/sbmips/ |
| sb1250_icu.c | 180 const uint64_t mbox_mask = 1LLU << tag; local in function:sb1250_lsw_send_ipi
183 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_SET_CPU, mbox_mask);
193 uint64_t mbox_mask; local in function:sb1250_ipi_intr
197 mbox_mask = READ_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CPU);
198 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CLR_CPU, mbox_mask);
200 ipi_process(ci, mbox_mask);
|
| /src/sys/arch/sbmips/sbmips/ |
| sb1250_icu.c | 180 const uint64_t mbox_mask = 1LLU << tag; local in function:sb1250_lsw_send_ipi
183 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_SET_CPU, mbox_mask);
193 uint64_t mbox_mask; local in function:sb1250_ipi_intr
197 mbox_mask = READ_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CPU);
198 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CLR_CPU, mbox_mask);
200 ipi_process(ci, mbox_mask);
|
