1 /* $NetBSD: agp_intel.c,v 1.40 2026/06/21 17:09:44 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.40 2026/06/21 17:09:44 andvar Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/agpio.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 43 #include <dev/pci/agpreg.h> 44 #include <dev/pci/agpvar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 49 struct agp_intel_softc { 50 u_int32_t initial_aperture; 51 /* aperture size at startup */ 52 struct agp_gatt *gatt; 53 struct pci_attach_args vga_pa; 54 u_int aperture_mask; 55 int chiptype; /* Chip type */ 56 #define CHIP_INTEL 0x0 57 #define CHIP_I443 0x1 58 #define CHIP_I840 0x2 59 #define CHIP_I845 0x3 60 #define CHIP_I850 0x4 61 #define CHIP_I865 0x5 62 63 }; 64 65 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 66 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 67 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 68 static int agp_intel_unbind_page(struct agp_softc *, off_t); 69 static void agp_intel_flush_tlb(struct agp_softc *); 70 static int agp_intel_init(struct agp_softc *); 71 static bool agp_intel_resume(device_t, const pmf_qual_t *); 72 73 static struct agp_methods agp_intel_methods = { 74 agp_intel_get_aperture, 75 agp_intel_set_aperture, 76 agp_intel_bind_page, 77 agp_intel_unbind_page, 78 agp_intel_flush_tlb, 79 agp_generic_enable, 80 agp_generic_alloc_memory, 81 agp_generic_free_memory, 82 agp_generic_bind_memory, 83 agp_generic_unbind_memory, 84 }; 85 86 static int 87 agp_intel_vgamatch(const struct pci_attach_args *pa) 88 { 89 switch (PCI_PRODUCT(pa->pa_id)) { 90 case PCI_PRODUCT_INTEL_82855GM_AGP: 91 case PCI_PRODUCT_INTEL_82855PM_AGP: 92 case PCI_PRODUCT_INTEL_82443LX_AGP: 93 case PCI_PRODUCT_INTEL_82443BX_AGP: 94 case PCI_PRODUCT_INTEL_82443GX_AGP: 95 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 96 case PCI_PRODUCT_INTEL_82845_AGP: 97 case PCI_PRODUCT_INTEL_82840_AGP: 98 case PCI_PRODUCT_INTEL_82865_AGP: 99 case PCI_PRODUCT_INTEL_82875P_AGP: 100 return (1); 101 } 102 103 return (0); 104 } 105 106 int 107 agp_intel_attach(device_t parent, device_t self, void *aux) 108 { 109 struct agp_softc *sc = device_private(self); 110 struct pci_attach_args *pa = aux; 111 struct agp_intel_softc *isc; 112 struct agp_gatt *gatt; 113 u_int32_t value; 114 115 isc = malloc(sizeof *isc, M_AGP, M_WAITOK|M_ZERO); 116 sc->as_methods = &agp_intel_methods; 117 sc->as_chipc = isc; 118 119 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 120 aprint_normal(": using generic initialization for Intel AGP\n"); 121 aprint_normal_dev(sc->as_dev, ""); 122 isc->chiptype = CHIP_INTEL; 123 } 124 125 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 126 NULL); 127 128 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 129 aprint_error(": can't map aperture\n"); 130 free(isc, M_AGP); 131 sc->as_chipc = NULL; 132 return ENXIO; 133 } 134 135 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 136 case PCI_PRODUCT_INTEL_82443LX_AGP: 137 case PCI_PRODUCT_INTEL_82443BX_AGP: 138 case PCI_PRODUCT_INTEL_82443GX_AGP: 139 isc->chiptype = CHIP_I443; 140 break; 141 case PCI_PRODUCT_INTEL_82840_AGP: 142 isc->chiptype = CHIP_I840; 143 break; 144 case PCI_PRODUCT_INTEL_82855GM_AGP: 145 case PCI_PRODUCT_INTEL_82855PM_AGP: 146 case PCI_PRODUCT_INTEL_82845_AGP: 147 isc->chiptype = CHIP_I845; 148 break; 149 case PCI_PRODUCT_INTEL_82850_AGP: 150 isc->chiptype = CHIP_I850; 151 break; 152 case PCI_PRODUCT_INTEL_82865_AGP: 153 case PCI_PRODUCT_INTEL_82875P_AGP: 154 isc->chiptype = CHIP_I865; 155 break; 156 } 157 158 /* Determine maximum supported aperture size. */ 159 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 160 pci_conf_write(sc->as_pc, sc->as_tag, 161 AGP_INTEL_APSIZE, APSIZE_MASK); 162 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 163 AGP_INTEL_APSIZE) & APSIZE_MASK; 164 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 165 isc->initial_aperture = AGP_GET_APERTURE(sc); 166 167 for (;;) { 168 gatt = agp_alloc_gatt(sc); 169 if (gatt) 170 break; 171 172 /* 173 * Probably contigmalloc failure. Try reducing the 174 * aperture so that the gatt size reduces. 175 */ 176 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 177 agp_generic_detach(sc); 178 aprint_error(": failed to set aperture\n"); 179 return ENOMEM; 180 } 181 } 182 isc->gatt = gatt; 183 184 if (!pmf_device_register(self, NULL, agp_intel_resume)) 185 aprint_error_dev(self, "couldn't establish power handler\n"); 186 187 return agp_intel_init(sc); 188 } 189 190 static int 191 agp_intel_init(struct agp_softc *sc) 192 { 193 struct agp_intel_softc *isc = sc->as_chipc; 194 struct agp_gatt *gatt = isc->gatt; 195 pcireg_t reg; 196 197 /* Install the gatt. */ 198 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 199 gatt->ag_physical); 200 201 /* Enable the GLTB and setup the control register. */ 202 switch (isc->chiptype) { 203 case CHIP_I443: 204 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 205 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 206 break; 207 208 default: 209 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 210 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 211 | AGPCTRL_GTLB); 212 } 213 214 /* Enable things, clear errors etc. */ 215 switch (isc->chiptype) { 216 case CHIP_I845: 217 case CHIP_I865: 218 { 219 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 220 reg |= MCHCFG_AAGN; 221 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 222 break; 223 } 224 case CHIP_I840: 225 case CHIP_I850: 226 { 227 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 228 reg |= AGPCMD_AGPEN; 229 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 230 reg); 231 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 232 reg |= MCHCFG_AAGN; 233 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 234 reg); 235 break; 236 } 237 default: 238 { 239 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 240 reg &= ~NBXCFG_APAE; 241 reg |= NBXCFG_AAGN; 242 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 243 } 244 } 245 246 /* Clear Error status */ 247 switch (isc->chiptype) { 248 case CHIP_I840: 249 pci_conf_write(sc->as_pc, sc->as_tag, 250 AGP_INTEL_I8XX_ERRSTS, 0xc000); 251 break; 252 253 case CHIP_I845: 254 case CHIP_I850: 255 case CHIP_I865: 256 pci_conf_write(sc->as_pc, sc->as_tag, 257 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 258 break; 259 260 default: 261 { 262 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS); 263 /* clear error bits (write-one-to-clear) - just write back */ 264 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS, reg); 265 } 266 } 267 268 return (0); 269 } 270 271 #if 0 272 static int 273 agp_intel_detach(struct agp_softc *sc) 274 { 275 int error; 276 pcireg_t reg; 277 struct agp_intel_softc *isc = sc->as_chipc; 278 279 error = agp_generic_detach(sc); 280 if (error) 281 return error; 282 283 /* XXX i845/i855PM/i840/i850E */ 284 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 285 reg &= ~(1 << 9); 286 printf("%s: set NBXCFG to %x\n", __func__, reg); 287 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 288 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 289 AGP_SET_APERTURE(sc, isc->initial_aperture); 290 agp_free_gatt(sc, isc->gatt); 291 292 return 0; 293 } 294 #endif 295 296 static u_int32_t 297 agp_intel_get_aperture(struct agp_softc *sc) 298 { 299 struct agp_intel_softc *isc = sc->as_chipc; 300 u_int32_t apsize; 301 302 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 303 AGP_INTEL_APSIZE) & isc->aperture_mask; 304 305 /* 306 * The size is determined by the number of low bits of 307 * register APBASE which are forced to zero. The low 22 bits 308 * are always forced to zero and each zero bit in the apsize 309 * field just read forces the corresponding bit in the 27:22 310 * to be zero. We calculate the aperture size accordingly. 311 */ 312 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 313 } 314 315 static int 316 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 317 { 318 struct agp_intel_softc *isc = sc->as_chipc; 319 u_int32_t apsize; 320 321 /* 322 * Reverse the magic from get_aperture. 323 */ 324 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 325 326 /* 327 * Double check for sanity. 328 */ 329 if ((((apsize ^ isc->aperture_mask) << 22) | 330 ((1 << 22) - 1)) + 1 != aperture) 331 return EINVAL; 332 333 pci_conf_write(sc->as_pc, sc->as_tag, 334 AGP_INTEL_APSIZE, apsize); 335 336 return 0; 337 } 338 339 static int 340 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 341 { 342 struct agp_intel_softc *isc = sc->as_chipc; 343 344 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 345 return EINVAL; 346 347 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 348 return 0; 349 } 350 351 static int 352 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 353 { 354 struct agp_intel_softc *isc = sc->as_chipc; 355 356 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 357 return EINVAL; 358 359 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 360 return 0; 361 } 362 363 static void 364 agp_intel_flush_tlb(struct agp_softc *sc) 365 { 366 struct agp_intel_softc *isc = sc->as_chipc; 367 pcireg_t reg; 368 369 switch (isc->chiptype) { 370 case CHIP_I865: 371 case CHIP_I850: 372 case CHIP_I845: 373 case CHIP_I840: 374 case CHIP_I443: 375 { 376 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 377 reg &= ~AGPCTRL_GTLB; 378 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 379 reg); 380 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 381 reg | AGPCTRL_GTLB); 382 break; 383 } 384 default: /* XXX */ 385 { 386 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 387 0x2200); 388 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 389 0x2280); 390 } 391 } 392 } 393 394 static bool 395 agp_intel_resume(device_t dv, const pmf_qual_t *qual) 396 { 397 struct agp_softc *sc = device_private(dv); 398 399 agp_intel_init(sc); 400 agp_flush_cache(); 401 402 return true; 403 } 404
Indexes created Sun Oct 25 00:26:45 UTC 2026