1 /* $NetBSD: savage_drv.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* savage_drv.h -- Private header for the savage driver */ 4 /* 5 * Copyright 2004 Felix Kuehling 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sub license, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 24 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #ifndef __SAVAGE_DRV_H__ 29 #define __SAVAGE_DRV_H__ 30 31 #include <linux/io.h> 32 33 #include <drm/drm_ioctl.h> 34 #include <drm/drm_legacy.h> 35 #include <drm/savage_drm.h> 36 37 #define DRIVER_AUTHOR "Felix Kuehling" 38 39 #define DRIVER_NAME "savage" 40 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" 41 #define DRIVER_DATE "20050313" 42 43 #define DRIVER_MAJOR 2 44 #define DRIVER_MINOR 4 45 #define DRIVER_PATCHLEVEL 1 46 /* Interface history: 47 * 48 * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy 49 * 2.0 The first real DRM 50 * 2.1 Scissors registers managed by the DRM, 3D operations clipped by 51 * cliprects of the cmdbuf ioctl 52 * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX 53 * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits 54 * wide and thus very long lived (unlikely to ever wrap). The size 55 * in the struct was 32 bits before, but only 16 bits were used 56 * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is 57 * actually used 58 */ 59 60 typedef struct drm_savage_age { 61 uint16_t event; 62 unsigned int wrap; 63 } drm_savage_age_t; 64 65 typedef struct drm_savage_buf_priv { 66 struct drm_savage_buf_priv *next; 67 struct drm_savage_buf_priv *prev; 68 drm_savage_age_t age; 69 struct drm_buf *buf; 70 } drm_savage_buf_priv_t; 71 72 typedef struct drm_savage_dma_page { 73 drm_savage_age_t age; 74 unsigned int used, flushed; 75 } drm_savage_dma_page_t; 76 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 77 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 78 * size of 16kbytes or 4k entries. Minimum requirement would be 79 * 10kbytes for 255 40-byte vertices in one drawing command. */ 80 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) 81 82 /* interesting bits of hardware state that are saved in dev_priv */ 83 typedef union { 84 struct drm_savage_common_state { 85 uint32_t vbaddr; 86 } common; 87 struct { 88 unsigned char pad[sizeof(struct drm_savage_common_state)]; 89 uint32_t texctrl, texaddr; 90 uint32_t scstart, new_scstart; 91 uint32_t scend, new_scend; 92 } s3d; 93 struct { 94 unsigned char pad[sizeof(struct drm_savage_common_state)]; 95 uint32_t texdescr, texaddr0, texaddr1; 96 uint32_t drawctrl0, new_drawctrl0; 97 uint32_t drawctrl1, new_drawctrl1; 98 } s4; 99 } drm_savage_state_t; 100 101 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ 102 enum savage_family { 103 S3_UNKNOWN = 0, 104 S3_SAVAGE3D, 105 S3_SAVAGE_MX, 106 S3_SAVAGE4, 107 S3_PROSAVAGE, 108 S3_TWISTER, 109 S3_PROSAVAGEDDR, 110 S3_SUPERSAVAGE, 111 S3_SAVAGE2000, 112 S3_LAST 113 }; 114 115 extern const struct drm_ioctl_desc savage_ioctls[]; 116 extern int savage_max_ioctl; 117 118 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 119 120 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 121 || (chip==S3_PROSAVAGE) \ 122 || (chip==S3_TWISTER) \ 123 || (chip==S3_PROSAVAGEDDR)) 124 125 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 126 127 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 128 129 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 130 ||(chip==S3_PROSAVAGEDDR)) 131 132 /* flags */ 133 #define SAVAGE_IS_AGP 1 134 135 typedef struct drm_savage_private { 136 drm_savage_sarea_t *sarea_priv; 137 138 drm_savage_buf_priv_t head, tail; 139 140 /* who am I? */ 141 enum savage_family chipset; 142 143 unsigned int cob_size; 144 unsigned int bci_threshold_lo, bci_threshold_hi; 145 unsigned int dma_type; 146 147 /* frame buffer layout */ 148 unsigned int fb_bpp; 149 unsigned int front_offset, front_pitch; 150 unsigned int back_offset, back_pitch; 151 unsigned int depth_bpp; 152 unsigned int depth_offset, depth_pitch; 153 154 /* bitmap descriptors for swap and clear */ 155 unsigned int front_bd, back_bd, depth_bd; 156 157 /* local textures */ 158 unsigned int texture_offset; 159 unsigned int texture_size; 160 161 /* memory regions in physical memory */ 162 drm_local_map_t *sarea; 163 drm_local_map_t *mmio; 164 drm_local_map_t *fb; 165 drm_local_map_t *aperture; 166 drm_local_map_t *status; 167 drm_local_map_t *agp_textures; 168 drm_local_map_t *cmd_dma; 169 drm_local_map_t fake_dma; 170 171 int mtrr_handles[3]; 172 173 /* BCI and status-related stuff */ 174 volatile uint32_t *status_ptr, *bci_ptr; 175 uint32_t status_used_mask; 176 uint16_t event_counter; 177 unsigned int event_wrap; 178 179 /* Savage4 command DMA */ 180 drm_savage_dma_page_t *dma_pages; 181 unsigned int nr_dma_pages, first_dma_page, current_dma_page; 182 drm_savage_age_t last_dma_age; 183 184 /* saved hw state for global/local check on S3D */ 185 uint32_t hw_draw_ctrl, hw_zbuf_ctrl; 186 /* and for scissors (global, so don't emit if not changed) */ 187 uint32_t hw_scissors_start, hw_scissors_end; 188 189 drm_savage_state_t state; 190 191 /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ 192 unsigned int waiting; 193 194 /* config/hardware-dependent function pointers */ 195 int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); 196 int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); 197 /* Err, there is a macro wait_event in include/linux/wait.h. 198 * Avoid unwanted macro expansion. */ 199 void (*emit_clip_rect) (struct drm_savage_private * dev_priv, 200 const struct drm_clip_rect * pbox); 201 void (*dma_flush) (struct drm_savage_private * dev_priv); 202 } drm_savage_private_t; 203 204 /* ioctls */ 205 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); 206 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 207 208 /* BCI functions */ 209 extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 210 unsigned int flags); 211 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf); 212 extern void savage_dma_reset(drm_savage_private_t * dev_priv); 213 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); 214 extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, 215 unsigned int n); 216 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); 217 extern int savage_driver_firstopen(struct drm_device *dev); 218 extern void savage_driver_lastclose(struct drm_device *dev); 219 extern void savage_driver_unload(struct drm_device *dev); 220 extern void savage_reclaim_buffers(struct drm_device *dev, 221 struct drm_file *file_priv); 222 223 /* state functions */ 224 extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, 225 const struct drm_clip_rect * pbox); 226 extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, 227 const struct drm_clip_rect * pbox); 228 229 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 230 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 231 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ 232 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 233 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 234 235 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 236 * inside the MMIO region */ 237 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 238 * BCI FIFO */ 239 240 /* 241 * MMIO registers 242 */ 243 #define SAVAGE_STATUS_WORD0 0x48C00 244 #define SAVAGE_STATUS_WORD1 0x48C04 245 #define SAVAGE_ALT_STATUS_WORD0 0x48C60 246 247 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff 248 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff 249 250 /* Copied from savage_bci.h in the 2D driver with some renaming. */ 251 252 /* Bitmap descriptors */ 253 #define SAVAGE_BD_STRIDE_SHIFT 0 254 #define SAVAGE_BD_BPP_SHIFT 16 255 #define SAVAGE_BD_TILE_SHIFT 24 256 #define SAVAGE_BD_BW_DISABLE (1<<28) 257 /* common: */ 258 #define SAVAGE_BD_TILE_LINEAR 0 259 /* savage4, MX, IX, 3D */ 260 #define SAVAGE_BD_TILE_16BPP 2 261 #define SAVAGE_BD_TILE_32BPP 3 262 /* twister, prosavage, DDR, supersavage, 2000 */ 263 #define SAVAGE_BD_TILE_DEST 1 264 #define SAVAGE_BD_TILE_TEXTURE 2 265 /* GBD - BCI enable */ 266 /* savage4, MX, IX, 3D */ 267 #define SAVAGE_GBD_BCI_ENABLE 8 268 /* twister, prosavage, DDR, supersavage, 2000 */ 269 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 270 271 #define SAVAGE_GBD_BIG_ENDIAN 4 272 #define SAVAGE_GBD_LITTLE_ENDIAN 0 273 #define SAVAGE_GBD_64 1 274 275 /* Global Bitmap Descriptor */ 276 #define SAVAGE_BCI_GLB_BD_LOW 0x8168 277 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C 278 279 /* 280 * BCI registers 281 */ 282 /* Savage4/Twister/ProSavage 3D registers */ 283 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e 284 #define SAVAGE_TEXPALADDR_S4 0x1f 285 #define SAVAGE_TEXCTRL0_S4 0x20 286 #define SAVAGE_TEXCTRL1_S4 0x21 287 #define SAVAGE_TEXADDR0_S4 0x22 288 #define SAVAGE_TEXADDR1_S4 0x23 289 #define SAVAGE_TEXBLEND0_S4 0x24 290 #define SAVAGE_TEXBLEND1_S4 0x25 291 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 292 #define SAVAGE_TEXDESCR_S4 0x27 293 #define SAVAGE_FOGTABLE_S4 0x28 294 #define SAVAGE_FOGCTRL_S4 0x30 295 #define SAVAGE_STENCILCTRL_S4 0x31 296 #define SAVAGE_ZBUFCTRL_S4 0x32 297 #define SAVAGE_ZBUFOFF_S4 0x33 298 #define SAVAGE_DESTCTRL_S4 0x34 299 #define SAVAGE_DRAWCTRL0_S4 0x35 300 #define SAVAGE_DRAWCTRL1_S4 0x36 301 #define SAVAGE_ZWATERMARK_S4 0x37 302 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 303 #define SAVAGE_TEXBLENDCOLOR_S4 0x39 304 /* Savage3D/MX/IX 3D registers */ 305 #define SAVAGE_TEXPALADDR_S3D 0x18 306 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 307 #define SAVAGE_TEXADDR_S3D 0x1A 308 #define SAVAGE_TEXDESCR_S3D 0x1B 309 #define SAVAGE_TEXCTRL_S3D 0x1C 310 #define SAVAGE_FOGTABLE_S3D 0x20 311 #define SAVAGE_FOGCTRL_S3D 0x30 312 #define SAVAGE_DRAWCTRL_S3D 0x31 313 #define SAVAGE_ZBUFCTRL_S3D 0x32 314 #define SAVAGE_ZBUFOFF_S3D 0x33 315 #define SAVAGE_DESTCTRL_S3D 0x34 316 #define SAVAGE_SCSTART_S3D 0x35 317 #define SAVAGE_SCEND_S3D 0x36 318 #define SAVAGE_ZWATERMARK_S3D 0x37 319 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 320 /* common stuff */ 321 #define SAVAGE_VERTBUFADDR 0x3e 322 #define SAVAGE_BITPLANEWTMASK 0xd7 323 #define SAVAGE_DMABUFADDR 0x51 324 325 /* texture enable bits (needed for tex addr checking) */ 326 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 327 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 328 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 329 330 /* Global fields in Savage4/Twister/ProSavage 3D registers: 331 * 332 * All texture registers and DrawLocalCtrl are local. All other 333 * registers are global. */ 334 335 /* Global fields in Savage3D/MX/IX 3D registers: 336 * 337 * All texture registers are local. DrawCtrl and ZBufCtrl are 338 * partially local. All other registers are global. 339 * 340 * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal 341 * ZBufCtrl global fields: zCmpFunc, zBufEn 342 */ 343 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c 344 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 345 346 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) 347 */ 348 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff 349 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff 350 351 /* 352 * BCI commands 353 */ 354 #define BCI_CMD_NOP 0x40000000 355 #define BCI_CMD_RECT 0x48000000 356 #define BCI_CMD_RECT_XP 0x01000000 357 #define BCI_CMD_RECT_YP 0x02000000 358 #define BCI_CMD_SCANLINE 0x50000000 359 #define BCI_CMD_LINE 0x5C000000 360 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000 361 #define BCI_CMD_BYTE_TEXT 0x63000000 362 #define BCI_CMD_NT_BYTE_TEXT 0x67000000 363 #define BCI_CMD_BIT_TEXT 0x6C000000 364 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 365 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 366 #define BCI_CMD_SEND_COLOR 0x00008000 367 368 #define BCI_CMD_CLIP_NONE 0x00000000 369 #define BCI_CMD_CLIP_CURRENT 0x00002000 370 #define BCI_CMD_CLIP_LR 0x00004000 371 #define BCI_CMD_CLIP_NEW 0x00006000 372 373 #define BCI_CMD_DEST_GBD 0x00000000 374 #define BCI_CMD_DEST_PBD 0x00000800 375 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 376 #define BCI_CMD_DEST_SBD 0x00001000 377 #define BCI_CMD_DEST_SBD_NEW 0x00001400 378 379 #define BCI_CMD_SRC_TRANSPARENT 0x00000200 380 #define BCI_CMD_SRC_SOLID 0x00000000 381 #define BCI_CMD_SRC_GBD 0x00000020 382 #define BCI_CMD_SRC_COLOR 0x00000040 383 #define BCI_CMD_SRC_MONO 0x00000060 384 #define BCI_CMD_SRC_PBD_COLOR 0x00000080 385 #define BCI_CMD_SRC_PBD_MONO 0x000000A0 386 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 387 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 388 #define BCI_CMD_SRC_SBD_COLOR 0x00000100 389 #define BCI_CMD_SRC_SBD_MONO 0x00000120 390 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 391 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 392 393 #define BCI_CMD_PAT_TRANSPARENT 0x00000010 394 #define BCI_CMD_PAT_NONE 0x00000000 395 #define BCI_CMD_PAT_COLOR 0x00000002 396 #define BCI_CMD_PAT_MONO 0x00000003 397 #define BCI_CMD_PAT_PBD_COLOR 0x00000004 398 #define BCI_CMD_PAT_PBD_MONO 0x00000005 399 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 400 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 401 #define BCI_CMD_PAT_SBD_COLOR 0x00000008 402 #define BCI_CMD_PAT_SBD_MONO 0x00000009 403 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A 404 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B 405 406 #define BCI_BD_BW_DISABLE 0x10000000 407 #define BCI_BD_TILE_MASK 0x03000000 408 #define BCI_BD_TILE_NONE 0x00000000 409 #define BCI_BD_TILE_16 0x02000000 410 #define BCI_BD_TILE_32 0x03000000 411 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) 412 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) 413 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) 414 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) 415 416 #define BCI_CMD_SET_REGISTER 0x96000000 417 418 #define BCI_CMD_WAIT 0xC0000000 419 #define BCI_CMD_WAIT_3D 0x00010000 420 #define BCI_CMD_WAIT_2D 0x00020000 421 422 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 423 424 #define BCI_CMD_DRAW_PRIM 0x80000000 425 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 426 #define BCI_CMD_DRAW_CONT 0x01000000 427 #define BCI_CMD_DRAW_TRILIST 0x00000000 428 #define BCI_CMD_DRAW_TRISTRIP 0x02000000 429 #define BCI_CMD_DRAW_TRIFAN 0x04000000 430 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff 431 #define BCI_CMD_DRAW_NO_Z 0x00000001 432 #define BCI_CMD_DRAW_NO_W 0x00000002 433 #define BCI_CMD_DRAW_NO_CD 0x00000004 434 #define BCI_CMD_DRAW_NO_CS 0x00000008 435 #define BCI_CMD_DRAW_NO_U0 0x00000010 436 #define BCI_CMD_DRAW_NO_V0 0x00000020 437 #define BCI_CMD_DRAW_NO_UV0 0x00000030 438 #define BCI_CMD_DRAW_NO_U1 0x00000040 439 #define BCI_CMD_DRAW_NO_V1 0x00000080 440 #define BCI_CMD_DRAW_NO_UV1 0x000000c0 441 442 #define BCI_CMD_DMA 0xa8000000 443 444 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 445 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 446 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) 447 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) 448 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) 449 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) 450 451 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) 452 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) 453 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \ 454 (((maj) & 0x1FFF) | \ 455 ((ym) ? 1<<13 : 0) | \ 456 ((xp) ? 1<<14 : 0) | \ 457 ((yp) ? 1<<15 : 0) | \ 458 ((err) << 16)) 459 460 /* 461 * common commands 462 */ 463 #define BCI_SET_REGISTERS( first, n ) \ 464 BCI_WRITE(BCI_CMD_SET_REGISTER | \ 465 ((uint32_t)(n) & 0xff) << 16 | \ 466 ((uint32_t)(first) & 0xffff)) 467 #define DMA_SET_REGISTERS( first, n ) \ 468 DMA_WRITE(BCI_CMD_SET_REGISTER | \ 469 ((uint32_t)(n) & 0xff) << 16 | \ 470 ((uint32_t)(first) & 0xffff)) 471 472 #define BCI_DRAW_PRIMITIVE(n, type, skip) \ 473 BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 474 ((n) << 16)) 475 #define DMA_DRAW_PRIMITIVE(n, type, skip) \ 476 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 477 ((n) << 16)) 478 479 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ 480 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 481 ((n) << 16) | (i0)) 482 483 #define BCI_DRAW_INDICES_S4(n, type, skip) \ 484 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 485 (skip) | ((n) << 16)) 486 487 #define BCI_DMA(n) \ 488 BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) 489 490 /* 491 * access to MMIO 492 */ 493 #define SAVAGE_READ(reg) \ 494 readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) 495 #define SAVAGE_WRITE(reg) \ 496 writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) 497 498 /* 499 * access to the burst command interface (BCI) 500 */ 501 #define SAVAGE_BCI_DEBUG 1 502 503 #define BCI_LOCALS volatile uint32_t *bci_ptr; 504 505 #define BEGIN_BCI( n ) do { \ 506 dev_priv->wait_fifo(dev_priv, (n)); \ 507 bci_ptr = dev_priv->bci_ptr; \ 508 } while(0) 509 510 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) 511 512 /* 513 * command DMA support 514 */ 515 #define SAVAGE_DMA_DEBUG 1 516 517 #define DMA_LOCALS uint32_t *dma_ptr; 518 519 #define BEGIN_DMA( n ) do { \ 520 unsigned int cur = dev_priv->current_dma_page; \ 521 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ 522 dev_priv->dma_pages[cur].used; \ 523 if ((n) > rest) { \ 524 dma_ptr = savage_dma_alloc(dev_priv, (n)); \ 525 } else { /* fast path for small allocations */ \ 526 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ 527 cur * SAVAGE_DMA_PAGE_SIZE + \ 528 dev_priv->dma_pages[cur].used; \ 529 if (dev_priv->dma_pages[cur].used == 0) \ 530 savage_dma_wait(dev_priv, cur); \ 531 dev_priv->dma_pages[cur].used += (n); \ 532 } \ 533 } while(0) 534 535 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) 536 537 #define DMA_COPY(src, n) do { \ 538 memcpy(dma_ptr, (src), (n)*4); \ 539 dma_ptr += n; \ 540 } while(0) 541 542 #if SAVAGE_DMA_DEBUG 543 #define DMA_COMMIT() do { \ 544 unsigned int cur = dev_priv->current_dma_page; \ 545 uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ 546 cur * SAVAGE_DMA_PAGE_SIZE + \ 547 dev_priv->dma_pages[cur].used; \ 548 if (dma_ptr != expected) { \ 549 DRM_ERROR("DMA allocation and use don't match: " \ 550 "%p != %p\n", expected, dma_ptr); \ 551 savage_dma_reset(dev_priv); \ 552 } \ 553 } while(0) 554 #else 555 #define DMA_COMMIT() do {/* nothing */} while(0) 556 #endif 557 558 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) 559 560 /* Buffer aging via event tag 561 */ 562 563 #define UPDATE_EVENT_COUNTER( ) do { \ 564 if (dev_priv->status_ptr) { \ 565 uint16_t count; \ 566 /* coordinate with Xserver */ \ 567 count = dev_priv->status_ptr[1023]; \ 568 if (count < dev_priv->event_counter) \ 569 dev_priv->event_wrap++; \ 570 dev_priv->event_counter = count; \ 571 } \ 572 } while(0) 573 574 #define SET_AGE( age, e, w ) do { \ 575 (age)->event = e; \ 576 (age)->wrap = w; \ 577 } while(0) 578 579 #define TEST_AGE( age, e, w ) \ 580 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 581 582 #endif /* __SAVAGE_DRV_H__ */ 583
Indexes created Thu Oct 02 14:10:14 GMT 2025