1 /* $NetBSD: mvsoc.c,v 1.33 2023/06/19 08:40:29 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014, 2016 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.33 2023/06/19 08:40:29 msaitoh Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #ifdef ARMADAXP 34 #include "mvxpe.h" 35 #include "mvxpsec.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/boot_flag.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/marvell/marvellreg.h> 48 #include <dev/marvell/marvellvar.h> 49 50 #include <arm/marvell/mvsocreg.h> 51 #include <arm/marvell/mvsocvar.h> 52 #include <arm/marvell/orionreg.h> 53 #include <arm/marvell/kirkwoodreg.h> 54 #include <arm/marvell/mv78xx0reg.h> 55 #include <arm/marvell/dovereg.h> 56 #include <arm/marvell/armadaxpvar.h> 57 #include <arm/marvell/armadaxpreg.h> 58 59 #include <uvm/uvm.h> 60 61 #include "locators.h" 62 63 #ifdef MVSOC_CONSOLE_EARLY 64 #include <dev/ic/ns16550reg.h> 65 #include <dev/ic/comreg.h> 66 #include <dev/cons.h> 67 #endif 68 69 static int mvsoc_match(device_t, struct cfdata *, void *); 70 static void mvsoc_attach(device_t, device_t, void *); 71 72 static int mvsoc_print(void *, const char *); 73 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 74 75 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 76 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 77 static int mvsoc_target_axi(int, uint32_t *, uint32_t *); 78 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 79 80 uint32_t mvPclk, mvSysclk, mvTclk = 0; 81 int nwindow = 0, nremap = 0; 82 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 83 vaddr_t mlmb_base; 84 85 void (*mvsoc_intr_init)(void); 86 int (*mvsoc_clkgating)(struct marvell_attach_args *); 87 88 89 #ifdef MVSOC_CONSOLE_EARLY 90 static vaddr_t com_base; 91 92 static inline uint32_t 93 uart_read(bus_size_t o) 94 { 95 return le32toh(*(volatile uint32_t *)(com_base + (o << 2))); 96 } 97 98 static inline void 99 uart_write(bus_size_t o, uint32_t v) 100 { 101 *(volatile uint32_t *)(com_base + (o << 2)) = htole32(v); 102 } 103 104 static int 105 mvsoc_cngetc(dev_t dv) 106 { 107 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 108 return -1; 109 110 return uart_read(com_data) & 0xff; 111 } 112 113 static void 114 mvsoc_cnputc(dev_t dv, int c) 115 { 116 int timo = 150000; 117 118 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 119 ; 120 121 uart_write(com_data, c); 122 123 timo = 150000; 124 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 125 ; 126 } 127 128 static struct consdev mvsoc_earlycons = { 129 .cn_putc = mvsoc_cnputc, 130 .cn_getc = mvsoc_cngetc, 131 .cn_pollc = nullcnpollc, 132 }; 133 #endif 134 135 136 /* attributes */ 137 static struct { 138 int tag; 139 uint32_t attr; 140 uint32_t target; 141 } mvsoc_tags[] = { 142 { MARVELL_TAG_SDRAM_CS0, 143 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 144 { MARVELL_TAG_SDRAM_CS1, 145 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 146 { MARVELL_TAG_SDRAM_CS2, 147 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 148 { MARVELL_TAG_SDRAM_CS3, 149 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 150 151 { MARVELL_TAG_AXI_CS0, 152 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR }, 153 { MARVELL_TAG_AXI_CS1, 154 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR }, 155 156 { MARVELL_TAG_DDR3_CS0, 157 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 158 { MARVELL_TAG_DDR3_CS1, 159 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 160 { MARVELL_TAG_DDR3_CS2, 161 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 162 { MARVELL_TAG_DDR3_CS3, 163 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 164 165 #if defined(ORION) 166 { ORION_TAG_DEVICE_CS0, 167 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 168 { ORION_TAG_DEVICE_CS1, 169 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 170 { ORION_TAG_DEVICE_CS2, 171 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 172 { ORION_TAG_DEVICE_BOOTCS, 173 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 174 { ORION_TAG_FLASH_CS, 175 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 176 { ORION_TAG_PEX0_MEM, 177 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 178 { ORION_TAG_PEX0_IO, 179 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 180 { ORION_TAG_PEX1_MEM, 181 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 182 { ORION_TAG_PEX1_IO, 183 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 184 { ORION_TAG_PCI_MEM, 185 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 186 { ORION_TAG_PCI_IO, 187 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 188 { ORION_TAG_CRYPT, 189 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 190 #endif 191 192 #if defined(KIRKWOOD) 193 { KIRKWOOD_TAG_NAND, 194 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 195 { KIRKWOOD_TAG_SPI, 196 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 197 { KIRKWOOD_TAG_BOOTROM, 198 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 199 { KIRKWOOD_TAG_PEX_MEM, 200 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 201 { KIRKWOOD_TAG_PEX_IO, 202 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 203 { KIRKWOOD_TAG_PEX1_MEM, 204 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 205 { KIRKWOOD_TAG_PEX1_IO, 206 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 207 { KIRKWOOD_TAG_CRYPT, 208 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 209 #endif 210 211 #if defined(MV78XX0) 212 { MV78XX0_TAG_DEVICE_CS0, 213 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 214 { MV78XX0_TAG_DEVICE_CS1, 215 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 216 { MV78XX0_TAG_DEVICE_CS2, 217 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 218 { MV78XX0_TAG_DEVICE_CS3, 219 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 220 { MV78XX0_TAG_DEVICE_BOOTCS, 221 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 222 { MV78XX0_TAG_SPI, 223 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 224 { MV78XX0_TAG_PEX0_MEM, 225 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 226 { MV78XX0_TAG_PEX01_MEM, 227 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 228 { MV78XX0_TAG_PEX02_MEM, 229 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 230 { MV78XX0_TAG_PEX03_MEM, 231 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 232 { MV78XX0_TAG_PEX0_IO, 233 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 234 { MV78XX0_TAG_PEX01_IO, 235 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 236 { MV78XX0_TAG_PEX02_IO, 237 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 238 { MV78XX0_TAG_PEX03_IO, 239 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 240 { MV78XX0_TAG_PEX1_MEM, 241 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 242 { MV78XX0_TAG_PEX11_MEM, 243 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 244 { MV78XX0_TAG_PEX12_MEM, 245 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 246 { MV78XX0_TAG_PEX13_MEM, 247 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 248 { MV78XX0_TAG_PEX1_IO, 249 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 250 { MV78XX0_TAG_PEX11_IO, 251 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 252 { MV78XX0_TAG_PEX12_IO, 253 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 254 { MV78XX0_TAG_PEX13_IO, 255 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 256 { MV78XX0_TAG_CRYPT, 257 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 258 #endif 259 260 #if defined(DOVE) 261 { DOVE_TAG_PEX0_MEM, 262 DOVE_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 263 { DOVE_TAG_PEX0_IO, 264 DOVE_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 265 { DOVE_TAG_PEX1_MEM, 266 DOVE_ATTR_PEX_MEM, DOVE_UNITID_PEX1 }, 267 { DOVE_TAG_PEX1_IO, 268 DOVE_ATTR_PEX_IO, DOVE_UNITID_PEX1 }, 269 { DOVE_TAG_CRYPT, 270 DOVE_ATTR_SA, DOVE_UNITID_SA }, 271 { DOVE_TAG_SPI0, 272 DOVE_ATTR_SPI0, MVSOC_UNITID_DEVBUS }, 273 { DOVE_TAG_SPI1, 274 DOVE_ATTR_SPI1, MVSOC_UNITID_DEVBUS }, 275 { DOVE_TAG_BOOTROM, 276 DOVE_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 277 { DOVE_TAG_PMU, 278 DOVE_ATTR_NAND, DOVE_UNITID_NAND }, 279 { DOVE_TAG_PMU, 280 DOVE_ATTR_PMU, DOVE_UNITID_PMU }, 281 #endif 282 283 #if defined(ARMADAXP) 284 { ARMADAXP_TAG_PEX00_MEM, 285 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 286 { ARMADAXP_TAG_PEX00_IO, 287 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 288 289 { ARMADAXP_TAG_PEX01_MEM, 290 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 291 { ARMADAXP_TAG_PEX01_IO, 292 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 293 294 { ARMADAXP_TAG_PEX02_MEM, 295 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 296 { ARMADAXP_TAG_PEX02_IO, 297 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 298 299 { ARMADAXP_TAG_PEX03_MEM, 300 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 301 { ARMADAXP_TAG_PEX03_IO, 302 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 303 304 { ARMADAXP_TAG_PEX10_MEM, 305 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX1 }, 306 { ARMADAXP_TAG_PEX10_IO, 307 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX1 }, 308 309 { ARMADAXP_TAG_PEX11_MEM, 310 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX1 }, 311 { ARMADAXP_TAG_PEX11_IO, 312 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX1 }, 313 314 { ARMADAXP_TAG_PEX12_MEM, 315 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX1 }, 316 { ARMADAXP_TAG_PEX12_IO, 317 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX1 }, 318 319 { ARMADAXP_TAG_PEX13_MEM, 320 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX1 }, 321 { ARMADAXP_TAG_PEX13_IO, 322 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX1 }, 323 324 { ARMADAXP_TAG_PEX2_MEM, 325 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 326 { ARMADAXP_TAG_PEX2_IO, 327 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 328 329 { ARMADAXP_TAG_PEX3_MEM, 330 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 331 { ARMADAXP_TAG_PEX3_IO, 332 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 333 334 { ARMADAXP_TAG_CRYPT0, 335 ARMADAXP_ATTR_CRYPT0_NOSWAP, ARMADAXP_UNITID_CRYPT }, 336 { ARMADAXP_TAG_CRYPT1, 337 ARMADAXP_ATTR_CRYPT1_NOSWAP, ARMADAXP_UNITID_CRYPT }, 338 #endif 339 }; 340 341 #if defined(ORION) 342 #define ORION_1(m) MARVELL_ORION_1_ ## m 343 #define ORION_2(m) MARVELL_ORION_2_ ## m 344 #endif 345 #if defined(KIRKWOOD) 346 #undef KIRKWOOD 347 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 348 #endif 349 #if defined(MV78XX0) 350 #undef MV78XX0 351 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 352 #endif 353 #if defined(DOVE) 354 #undef DOVE 355 #define DOVE(m) MARVELL_DOVE_ ## m 356 #endif 357 #if defined(ARMADAXP) 358 #undef ARMADAXP 359 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 360 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 361 #endif 362 static struct { 363 uint16_t model; 364 uint8_t rev; 365 const char *modelstr; 366 const char *revstr; 367 const char *typestr; 368 } nametbl[] = { 369 #if defined(ORION) 370 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 371 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 372 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 373 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 374 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 375 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 376 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 377 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 378 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 379 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 380 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 381 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 382 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 383 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 384 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 385 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 386 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 387 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 388 389 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 390 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 391 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 392 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 393 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 394 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 395 #endif 396 397 #if defined(KIRKWOOD) 398 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 399 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 400 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 401 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 402 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 403 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 404 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 405 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 406 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 407 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 408 #endif 409 410 #if defined(MV78XX0) 411 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 412 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 413 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 414 #endif 415 416 #if defined(DOVE) 417 { DOVE(88AP510), 0, "88AP510", "Z0", "Dove" }, 418 { DOVE(88AP510), 1, "88AP510", "Z1", "Dove" }, 419 { DOVE(88AP510), 2, "88AP510", "Y0", "Dove" }, 420 { DOVE(88AP510), 3, "88AP510", "Y1", "Dove" }, 421 { DOVE(88AP510), 4, "88AP510", "X0", "Dove" }, 422 { DOVE(88AP510), 6, "88AP510", "A0", "Dove" }, 423 { DOVE(88AP510), 7, "88AP510", "A1", "Dove" }, 424 #endif 425 426 #if defined(ARMADAXP) 427 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 428 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 429 { ARMADAXP(MV78230), 1, "MV78230", "A0", "Armada XP" }, 430 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 431 { ARMADAXP(MV78260), 2, "MV78260", "B0", "Armada XP" }, 432 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 433 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 434 435 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 436 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 437 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 438 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 439 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 440 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 441 #endif 442 }; 443 444 enum marvell_tags ddr_tags[] = { 445 MARVELL_TAG_SDRAM_CS0, 446 MARVELL_TAG_SDRAM_CS1, 447 MARVELL_TAG_SDRAM_CS2, 448 MARVELL_TAG_SDRAM_CS3, 449 450 MARVELL_TAG_UNDEFINED 451 }; 452 enum marvell_tags ddr3_tags[] = { 453 MARVELL_TAG_DDR3_CS0, 454 MARVELL_TAG_DDR3_CS1, 455 MARVELL_TAG_DDR3_CS2, 456 MARVELL_TAG_DDR3_CS3, 457 458 MARVELL_TAG_UNDEFINED 459 }; 460 enum marvell_tags axi_tags[] = { 461 MARVELL_TAG_AXI_CS0, 462 MARVELL_TAG_AXI_CS1, 463 464 MARVELL_TAG_UNDEFINED 465 }; 466 static struct { 467 uint16_t model; 468 uint8_t rev; 469 enum marvell_tags *tags; 470 } tagstbl[] = { 471 #if defined(ORION) 472 { ORION_1(88F1181), 0, ddr_tags }, 473 { ORION_1(88F5082), 2, ddr_tags }, 474 { ORION_1(88F5180N), 3, ddr_tags }, 475 { ORION_1(88F5181), 0, ddr_tags }, 476 { ORION_1(88F5181), 1, ddr_tags }, 477 { ORION_1(88F5181), 2, ddr_tags }, 478 { ORION_1(88F5181), 3, ddr_tags }, 479 { ORION_1(88F5181), 8, ddr_tags }, 480 { ORION_1(88F5181), 9, ddr_tags }, 481 { ORION_1(88F5182), 0, ddr_tags }, 482 { ORION_1(88F5182), 1, ddr_tags }, 483 { ORION_1(88F5182), 2, ddr_tags }, 484 { ORION_1(88F6082), 0, ddr_tags }, 485 { ORION_1(88F6082), 1, ddr_tags }, 486 { ORION_1(88F6183), 0, ddr_tags }, 487 { ORION_1(88F6183), 1, ddr_tags }, 488 { ORION_1(88W8660), 0, ddr_tags }, 489 { ORION_1(88W8660), 1, ddr_tags }, 490 491 { ORION_2(88F1281), 0, ddr_tags }, 492 { ORION_2(88F5281), 0, ddr_tags }, 493 { ORION_2(88F5281), 1, ddr_tags }, 494 { ORION_2(88F5281), 2, ddr_tags }, 495 { ORION_2(88F5281), 3, ddr_tags }, 496 { ORION_2(88F5281), 4, ddr_tags }, 497 #endif 498 499 #if defined(KIRKWOOD) 500 { KIRKWOOD(88F6180), 2, ddr_tags }, 501 { KIRKWOOD(88F6180), 3, ddr_tags }, 502 { KIRKWOOD(88F6192), 0, ddr_tags }, 503 { KIRKWOOD(88F6192), 2, ddr_tags }, 504 { KIRKWOOD(88F6192), 3, ddr_tags }, 505 { KIRKWOOD(88F6281), 0, ddr_tags }, 506 { KIRKWOOD(88F6281), 2, ddr_tags }, 507 { KIRKWOOD(88F6281), 3, ddr_tags }, 508 { KIRKWOOD(88F6282), 0, ddr_tags }, 509 { KIRKWOOD(88F6282), 1, ddr_tags }, 510 #endif 511 512 #if defined(MV78XX0) 513 { MV78XX0(MV78100), 1, ddr_tags }, 514 { MV78XX0(MV78100), 2, ddr_tags }, 515 { MV78XX0(MV78200), 1, ddr_tags }, 516 #endif 517 518 #if defined(DOVE) 519 { DOVE(88AP510), 0, axi_tags }, 520 { DOVE(88AP510), 1, axi_tags }, 521 { DOVE(88AP510), 2, axi_tags }, 522 { DOVE(88AP510), 3, axi_tags }, 523 { DOVE(88AP510), 4, axi_tags }, 524 { DOVE(88AP510), 5, axi_tags }, 525 { DOVE(88AP510), 6, axi_tags }, 526 { DOVE(88AP510), 7, axi_tags }, 527 #endif 528 529 #if defined(ARMADAXP) 530 { ARMADAXP(MV78130), 1, ddr3_tags }, 531 { ARMADAXP(MV78160), 1, ddr3_tags }, 532 { ARMADAXP(MV78230), 1, ddr3_tags }, 533 { ARMADAXP(MV78260), 1, ddr3_tags }, 534 { ARMADAXP(MV78260), 2, ddr3_tags }, 535 { ARMADAXP(MV78460), 1, ddr3_tags }, 536 { ARMADAXP(MV78460), 2, ddr3_tags }, 537 538 { ARMADA370(MV6707), 0, ddr3_tags }, 539 { ARMADA370(MV6707), 1, ddr3_tags }, 540 { ARMADA370(MV6710), 0, ddr3_tags }, 541 { ARMADA370(MV6710), 1, ddr3_tags }, 542 { ARMADA370(MV6W11), 0, ddr3_tags }, 543 { ARMADA370(MV6W11), 1, ddr3_tags }, 544 #endif 545 }; 546 547 548 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 549 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 550 static const struct mvsoc_periph { 551 int model; 552 const char *name; 553 int unit; 554 bus_size_t offset; 555 int irq; 556 } mvsoc_periphs[] = { 557 #if defined(ORION) 558 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 559 560 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 561 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 562 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 563 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 564 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 565 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 566 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 567 568 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 569 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 570 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 571 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 572 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 573 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 574 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 575 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 576 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 577 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 578 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 579 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 580 581 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 582 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 583 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 584 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 585 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 586 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 587 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 588 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 589 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 590 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 591 592 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 593 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 594 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 595 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 596 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 597 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 598 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 599 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 600 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 601 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 602 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 603 604 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 605 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 606 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 607 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 608 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 609 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 610 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 611 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 612 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 613 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 614 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 615 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 616 617 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 618 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 619 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 620 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 621 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 622 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 623 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 624 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 625 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 626 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 627 628 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 629 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 630 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 631 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 632 633 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 634 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 635 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 636 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 637 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 638 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 639 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 640 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 641 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 642 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 643 644 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 645 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 646 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 647 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 648 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 649 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 650 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 651 652 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 653 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 654 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 655 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 656 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 657 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 658 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 659 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 660 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 661 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 662 #endif 663 664 #if defined(KIRKWOOD) 665 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 666 667 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 668 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 669 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 670 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 671 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 672 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 673 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 674 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 675 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 676 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 677 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 678 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 679 680 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 681 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 682 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 683 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 684 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 685 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 686 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 687 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 688 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 689 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 690 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 691 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 692 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 693 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 694 695 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 696 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 697 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 698 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 699 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 700 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 701 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 702 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 703 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 704 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 705 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 706 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 707 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 708 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 709 710 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 711 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 712 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 713 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 714 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 715 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 716 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 717 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 718 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 719 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 720 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 721 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 722 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 723 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 724 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 725 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 726 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 727 #endif 728 729 #if defined(MV78XX0) 730 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 731 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 732 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 733 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 734 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 735 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 736 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 737 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 738 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 739 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 740 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 741 742 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 743 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 744 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 745 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 746 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 747 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 748 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 749 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 750 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 751 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 752 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 753 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 754 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 755 #endif 756 757 #if defined(DOVE) 758 #define DOVE_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 759 760 { DOVE(88AP510), "mvsoctmr",0, MVSOC_TMR_BASE, DOVE_IRQ_TMR }, 761 { DOVE(88AP510), "mvsocpmu",0, DOVE_PMU_BASE, DOVE_IRQ_PMU }, 762 { DOVE(88AP510), "com", 0, MVSOC_COM0_BASE, DOVE_IRQ_UART0 }, 763 { DOVE(88AP510), "com", 1, MVSOC_COM1_BASE, DOVE_IRQ_UART1 }, 764 { DOVE(88AP510), "com", 2, DOVE_COM2_BASE, DOVE_IRQ_UART2 }, 765 { DOVE(88AP510), "com", 3, DOVE_COM3_BASE, DOVE_IRQ_UART3 }, 766 { DOVE(88AP510), "gttwsi", 0, MVSOC_TWSI_BASE, DOVE_IRQ_TWSI }, 767 { DOVE(88AP510), "mvspi", 0, DOVE_SPI0_BASE, DOVE_IRQ_SPI0 }, 768 { DOVE(88AP510), "mvspi", 1, DOVE_SPI1_BASE, DOVE_IRQ_SPI1 }, 769 { DOVE(88AP510), "mvcesa", 0, DOVE_CESA_BASE, DOVE_IRQ_SECURITYINT }, 770 { DOVE(88AP510), "ehci", 0, DOVE_USB0_BASE, DOVE_IRQ_USB0CNT }, 771 { DOVE(88AP510), "ehci", 1, DOVE_USB1_BASE, DOVE_IRQ_USB1CNT }, 772 { DOVE(88AP510), "gtidmac", 0, DOVE_XORE_BASE, IRQ_DEFAULT }, 773 { DOVE(88AP510), "mvgbec", 0, DOVE_GBE_BASE, IRQ_DEFAULT }, 774 { DOVE(88AP510), "mvpex", 0, MVSOC_PEX_BASE, DOVE_IRQ_PEX0_INT }, 775 { DOVE(88AP510), "mvpex", 1, DOVE_PEX1_BASE, DOVE_IRQ_PEX1_INT }, 776 { DOVE(88AP510), "sdhc", 0, DOVE_SDHC0_BASE, DOVE_IRQ_SD0 }, 777 { DOVE(88AP510), "sdhc", 1, DOVE_SDHC1_BASE, DOVE_IRQ_SD1 }, 778 { DOVE(88AP510), "mvsata", 0, DOVE_SATAHC_BASE, DOVE_IRQ_SATAINT }, 779 // { DOVE(88AP510), "mvsocgpp",0, MVSOC_GPP_BASE, IRQ_DEFAULT }, 780 { DOVE(88AP510), "mvsocrtc",0, DOVE_RTC_BASE, IRQ_DEFAULT }, 781 #endif 782 783 #if defined(ARMADAXP) 784 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 785 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 786 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 787 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 788 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 789 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 790 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 791 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 792 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 793 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 794 { ARMADAXP(MV78130), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 795 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 796 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 797 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 798 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 799 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 800 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 801 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 802 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 803 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 804 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 805 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 806 #if NMVXPE > 0 807 { ARMADAXP(MV78130), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 808 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 809 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 810 #else 811 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 812 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 813 #endif 814 #if NMVXPSEC > 0 815 { ARMADAXP(MV78130), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 816 { ARMADAXP(MV78130), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 817 #else 818 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 819 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 820 #endif 821 822 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 823 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 824 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 825 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 826 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 827 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 828 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 829 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 830 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 831 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 832 { ARMADAXP(MV78160), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 833 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 834 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 835 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 836 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 837 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 838 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 839 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 840 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 841 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 842 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 843 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 844 #if NMVXPE > 0 845 { ARMADAXP(MV78160), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 846 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 847 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 848 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 849 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 850 #else 851 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 852 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 853 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 854 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 855 #endif 856 #if NMVXPSEC > 0 857 { ARMADAXP(MV78160), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 858 { ARMADAXP(MV78160), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 859 #else 860 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 861 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 862 #endif 863 864 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 865 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 866 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 867 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 868 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 869 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 870 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 871 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 872 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 873 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 874 { ARMADAXP(MV78230), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 875 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 876 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 877 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 878 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 879 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 880 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 881 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 882 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX10_BASE,ARMADAXP_IRQ_PEX10 }, 883 { ARMADAXP(MV78230), "mvpex", 5, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 884 { ARMADAXP(MV78230), "mvpex", 6, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 885 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 886 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 887 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 888 #if NMVXPE > 0 889 { ARMADAXP(MV78230), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 890 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 891 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 892 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 893 #else 894 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 895 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 896 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 897 #endif 898 #if NMVXPSEC > 0 899 { ARMADAXP(MV78230), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 900 { ARMADAXP(MV78230), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 901 #else 902 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 903 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 904 #endif 905 906 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 907 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 908 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 909 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 910 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 911 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 912 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 913 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 914 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 915 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 916 { ARMADAXP(MV78260), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 917 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 918 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 919 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 920 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 921 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 922 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 923 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 924 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 925 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 926 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 927 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 928 #if NMVXPE > 0 929 { ARMADAXP(MV78260), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 930 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 931 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 932 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 933 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 934 #else 935 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 936 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 937 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 938 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 939 #endif 940 #if NMVXPSEC > 0 941 { ARMADAXP(MV78260), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 942 { ARMADAXP(MV78260), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 943 #else 944 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 945 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 946 #endif 947 948 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 949 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 950 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 951 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 952 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 953 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 954 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 955 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 956 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 957 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 958 { ARMADAXP(MV78460), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 959 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 960 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 961 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 962 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 963 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 964 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 965 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 966 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 967 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 968 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 969 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 970 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 971 #if NMVXPE > 0 972 { ARMADAXP(MV78460), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 973 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 974 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 975 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 976 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 977 #else 978 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 979 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 980 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 981 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 982 #endif 983 #if NMVXPSEC > 0 984 { ARMADAXP(MV78460), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 985 { ARMADAXP(MV78460), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 986 #else 987 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 988 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 989 #endif 990 991 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 992 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 993 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 994 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 995 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 996 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 997 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 998 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 999 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 1000 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 1001 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 1002 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 1003 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 1004 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 1005 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 1006 #if NMVXPE > 0 1007 { ARMADA370(MV6710), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 1008 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 1009 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 1010 #else 1011 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 1012 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 1013 #endif 1014 #if NMVXPSEC > 0 1015 { ARMADA370(MV6710), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 1016 #else 1017 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 1018 #endif 1019 #endif 1020 }; 1021 1022 1023 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 1024 mvsoc_match, mvsoc_attach, NULL, NULL); 1025 1026 /* ARGSUSED */ 1027 static int 1028 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 1029 { 1030 1031 return 1; 1032 } 1033 1034 /* ARGSUSED */ 1035 static void 1036 mvsoc_attach(device_t parent, device_t self, void *aux) 1037 { 1038 struct mvsoc_softc *sc = device_private(self); 1039 struct marvell_attach_args mva; 1040 enum marvell_tags *tags; 1041 uint16_t model; 1042 uint8_t rev; 1043 int i; 1044 1045 sc->sc_dev = self; 1046 sc->sc_iot = &mvsoc_bs_tag; 1047 sc->sc_addr = vtophys(regbase); 1048 sc->sc_dmat = &mvsoc_bus_dma_tag; 1049 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 1050 0) { 1051 aprint_error_dev(self, "can't map registers\n"); 1052 return; 1053 } 1054 1055 model = mvsoc_model(); 1056 rev = mvsoc_rev(); 1057 for (i = 0; i < __arraycount(nametbl); i++) 1058 if (nametbl[i].model == model && nametbl[i].rev == rev) 1059 break; 1060 if (i >= __arraycount(nametbl)) 1061 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 1062 1063 aprint_normal(": Marvell %s %s%s %s\n", 1064 nametbl[i].modelstr, 1065 nametbl[i].revstr != NULL ? "Rev. " : "", 1066 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 1067 nametbl[i].typestr); 1068 aprint_normal("%s: CPU Clock %d.%03d MHz" 1069 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 1070 device_xname(self), 1071 mvPclk / 1000000, (mvPclk / 1000) % 1000, 1072 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 1073 mvTclk / 1000000, (mvTclk / 1000) % 1000); 1074 aprint_naive("\n"); 1075 1076 mvsoc_intr_init(); 1077 1078 for (i = 0; i < __arraycount(tagstbl); i++) 1079 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 1080 break; 1081 if (i >= __arraycount(tagstbl)) 1082 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 1083 tags = tagstbl[i].tags; 1084 1085 if (boothowto & (AB_VERBOSE | AB_DEBUG)) 1086 mvsoc_target_dump(sc); 1087 1088 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 1089 if (mvsoc_periphs[i].model != model) 1090 continue; 1091 1092 mva.mva_name = mvsoc_periphs[i].name; 1093 mva.mva_model = model; 1094 mva.mva_revision = rev; 1095 mva.mva_iot = sc->sc_iot; 1096 mva.mva_ioh = sc->sc_ioh; 1097 mva.mva_unit = mvsoc_periphs[i].unit; 1098 mva.mva_addr = sc->sc_addr; 1099 mva.mva_offset = mvsoc_periphs[i].offset; 1100 mva.mva_size = 0; 1101 mva.mva_dmat = sc->sc_dmat; 1102 mva.mva_irq = mvsoc_periphs[i].irq; 1103 mva.mva_tags = tags; 1104 1105 /* Skip clock disabled devices */ 1106 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 1107 aprint_normal_dev(self, "%s%d clock disabled\n", 1108 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 1109 continue; 1110 } 1111 1112 config_found(sc->sc_dev, &mva, mvsoc_print, 1113 CFARGS(.submatch = mvsoc_search)); 1114 } 1115 } 1116 1117 static int 1118 mvsoc_print(void *aux, const char *pnp) 1119 { 1120 struct marvell_attach_args *mva = aux; 1121 1122 if (pnp) 1123 aprint_normal("%s at %s unit %d", 1124 mva->mva_name, pnp, mva->mva_unit); 1125 else { 1126 if (mva->mva_unit != MVA_UNIT_DEFAULT) 1127 aprint_normal(" unit %d", mva->mva_unit); 1128 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 1129 aprint_normal(" offset 0x%04lx", mva->mva_offset); 1130 if (mva->mva_size > 0) 1131 aprint_normal("-0x%04lx", 1132 mva->mva_offset + mva->mva_size - 1); 1133 } 1134 if (mva->mva_irq != MVA_IRQ_DEFAULT) 1135 aprint_normal(" irq %d", mva->mva_irq); 1136 } 1137 1138 return UNCONF; 1139 } 1140 1141 /* ARGSUSED */ 1142 static int 1143 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 1144 { 1145 1146 return config_match(parent, cf, aux); 1147 } 1148 1149 /* ARGSUSED */ 1150 int 1151 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 1152 uint64_t *base, uint32_t *size) 1153 { 1154 uint32_t base32; 1155 int rv; 1156 1157 rv = mvsoc_target(tag, target, attribute, &base32, size); 1158 *base = base32; 1159 if (rv == -1) 1160 return -1; 1161 return 0; 1162 } 1163 1164 1165 /* 1166 * These functions is called before bus_space is initialized. 1167 */ 1168 1169 void 1170 mvsoc_bootstrap(bus_addr_t iobase) 1171 { 1172 1173 regbase = iobase; 1174 dsc_base = iobase + MVSOC_DSC_BASE; 1175 mlmb_base = iobase + MVSOC_MLMB_BASE; 1176 pex_base = iobase + MVSOC_PEX_BASE; 1177 #ifdef MVSOC_CONSOLE_EARLY 1178 com_base = iobase + MVSOC_COM0_BASE; 1179 cn_tab = &mvsoc_earlycons; 1180 printf("Hello\n"); 1181 #endif 1182 } 1183 1184 /* 1185 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1186 */ 1187 uint16_t 1188 mvsoc_model(void) 1189 { 1190 /* 1191 * We read product-id from vendor/device register of PCI-Express. 1192 */ 1193 uint32_t reg; 1194 uint16_t model; 1195 1196 KASSERT(regbase != 0xffffffff); 1197 1198 reg = le32toh(*(volatile uint32_t *)(pex_base + PCI_ID_REG)); 1199 model = PCI_PRODUCT(reg); 1200 1201 #if defined(ORION) 1202 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1203 reg = le32toh(*(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1204 ORION_PMI_SAMPLE_AT_RESET)); 1205 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1206 model = PCI_PRODUCT_MARVELL_88F5082; 1207 } 1208 #endif 1209 #if defined(KIRKWOOD) 1210 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1211 reg = le32toh(*(volatile uint32_t *)(regbase + 1212 KIRKWOOD_MISC_BASE + KIRKWOOD_MISC_DEVICEID)); 1213 if (reg == 1) /* 88F6192 is 1 */ 1214 model = MARVELL_KIRKWOOD_88F6192; 1215 } 1216 #endif 1217 1218 return model; 1219 } 1220 1221 uint8_t 1222 mvsoc_rev(void) 1223 { 1224 uint32_t reg; 1225 uint8_t rev; 1226 1227 KASSERT(regbase != 0xffffffff); 1228 1229 reg = le32toh(*(volatile uint32_t *)(pex_base + PCI_CLASS_REG)); 1230 rev = PCI_REVISION(reg); 1231 1232 return rev; 1233 } 1234 1235 1236 int 1237 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1238 uint32_t *size) 1239 { 1240 int i; 1241 1242 KASSERT(regbase != 0xffffffff); 1243 1244 if (tag == MVSOC_TAG_INTERNALREG) { 1245 if (target != NULL) 1246 *target = 0; 1247 if (attr != NULL) 1248 *attr = 0; 1249 if (base != NULL) 1250 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1251 MVSOC_MLMB_IRBAR_BASE_MASK; 1252 if (size != NULL) 1253 *size = 0; 1254 1255 return 0; 1256 } 1257 1258 /* sanity check */ 1259 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1260 if (mvsoc_tags[i].tag == tag) 1261 break; 1262 if (i >= __arraycount(mvsoc_tags)) 1263 return -1; 1264 1265 if (target != NULL) 1266 *target = mvsoc_tags[i].target; 1267 if (attr != NULL) 1268 *attr = mvsoc_tags[i].attr; 1269 1270 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1271 if (tag == MARVELL_TAG_SDRAM_CS0 || 1272 tag == MARVELL_TAG_SDRAM_CS1 || 1273 tag == MARVELL_TAG_SDRAM_CS2 || 1274 tag == MARVELL_TAG_SDRAM_CS3) 1275 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1276 else if (tag == MARVELL_TAG_AXI_CS0 || 1277 tag == MARVELL_TAG_AXI_CS1) 1278 return mvsoc_target_axi(tag, base, size); 1279 else 1280 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1281 size); 1282 } else 1283 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1284 mvsoc_tags[i].attr, base, size); 1285 } 1286 1287 static int 1288 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1289 { 1290 uint32_t baseaddrreg, sizereg; 1291 int cs; 1292 1293 /* 1294 * Read DDR SDRAM Controller Address Decode Registers 1295 */ 1296 1297 switch (attr) { 1298 case MARVELL_ATTR_SDRAM_CS0: 1299 cs = 0; 1300 break; 1301 case MARVELL_ATTR_SDRAM_CS1: 1302 cs = 1; 1303 break; 1304 case MARVELL_ATTR_SDRAM_CS2: 1305 cs = 2; 1306 break; 1307 case MARVELL_ATTR_SDRAM_CS3: 1308 cs = 3; 1309 break; 1310 default: 1311 aprint_error("unknown ATTR: 0x%x", attr); 1312 return -1; 1313 } 1314 sizereg = le32toh(*(volatile uint32_t *)(dsc_base + 1315 MVSOC_DSC_CSSR(cs))); 1316 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1317 baseaddrreg = le32toh(*(volatile uint32_t *)(dsc_base + 1318 MVSOC_DSC_CSBAR(cs))); 1319 1320 if (base != NULL) 1321 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1322 if (size != NULL) 1323 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1324 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1325 } else { 1326 if (base != NULL) 1327 *base = 0; 1328 if (size != NULL) 1329 *size = 0; 1330 } 1331 return 0; 1332 } 1333 1334 static int 1335 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1336 { 1337 uint32_t baseaddrreg, sizereg; 1338 int cs, i; 1339 1340 /* 1341 * Read DDR3 SDRAM Address Decoding Registers 1342 */ 1343 1344 switch (attr) { 1345 case MARVELL_ATTR_SDRAM_CS0: 1346 cs = 0; 1347 break; 1348 case MARVELL_ATTR_SDRAM_CS1: 1349 cs = 1; 1350 break; 1351 case MARVELL_ATTR_SDRAM_CS2: 1352 cs = 2; 1353 break; 1354 case MARVELL_ATTR_SDRAM_CS3: 1355 cs = 3; 1356 break; 1357 default: 1358 aprint_error("unknown ATTR: 0x%x", attr); 1359 return -1; 1360 } 1361 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1362 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1363 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1364 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1365 break; 1366 } 1367 if (i == MVSOC_MLMB_NWIN) { 1368 if (base != NULL) 1369 *base = 0; 1370 if (size != NULL) 1371 *size = 0; 1372 return 0; 1373 } 1374 1375 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1376 if (base != NULL) 1377 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1378 if (size != NULL) 1379 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1380 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1381 return 0; 1382 } 1383 1384 static int 1385 mvsoc_target_axi(int tag, uint32_t *base, uint32_t *size) 1386 { 1387 uint32_t val; 1388 int cs; 1389 1390 /* 1391 * Read MMAP1 Chip Select N the other side of AXI DDR Registers 1392 */ 1393 1394 switch (tag) { 1395 case MARVELL_TAG_AXI_CS0: 1396 cs = 0; 1397 break; 1398 case MARVELL_TAG_AXI_CS1: 1399 cs = 1; 1400 break; 1401 default: 1402 aprint_error("unknown TAG: 0x%x", tag); 1403 return -1; 1404 } 1405 val = le32toh(*(volatile uint32_t *)(regbase + MVSOC_AXI_MMAP1(cs))); 1406 if (val & MVSOC_AXI_MMAP1_VALID) { 1407 if (base != NULL) 1408 *base = MVSOC_AXI_MMAP1_STARTADDRESS(val); 1409 if (size != NULL) 1410 *size = MVSOC_AXI_MMAP1_AREALENGTH(val); 1411 } else { 1412 if (base != NULL) 1413 *base = 0; 1414 if (size != NULL) 1415 *size = 0; 1416 } 1417 return 0; 1418 } 1419 1420 static int 1421 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1422 uint32_t *size) 1423 { 1424 uint32_t basereg, ctrlreg, ta, tamask; 1425 int i; 1426 1427 /* 1428 * Read CPU Address Map Registers 1429 */ 1430 1431 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1432 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1433 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1434 1435 if (base != NULL) 1436 *base = 0; 1437 if (size != NULL) 1438 *size = 0; 1439 1440 for (i = 0; i < nwindow; i++) { 1441 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1442 if ((ctrlreg & tamask) != ta) 1443 continue; 1444 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1445 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1446 1447 if (base != NULL) 1448 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1449 if (size != NULL) 1450 *size = (ctrlreg & 1451 MVSOC_MLMB_WCR_SIZE_MASK) + 1452 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1453 } 1454 break; 1455 } 1456 return i; 1457 } 1458 1459 int 1460 mvsoc_target_dump(struct mvsoc_softc *sc) 1461 { 1462 uint32_t reg, base, size, target, attr, enable; 1463 int i, n; 1464 1465 for (i = 0, n = 0; i < nwindow; i++) { 1466 reg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1467 enable = reg & MVSOC_MLMB_WCR_WINEN; 1468 target = MVSOC_MLMB_WCR_GET_TARGET(reg); 1469 attr = MVSOC_MLMB_WCR_GET_ATTR(reg); 1470 size = MVSOC_MLMB_WCR_GET_SIZE(reg); 1471 1472 reg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1473 base = MVSOC_MLMB_WBR_GET_BASE(reg); 1474 1475 if (!enable) 1476 continue; 1477 1478 aprint_verbose_dev(sc->sc_dev, 1479 "Mbus window %2d: Base 0x%08x Size 0x%08x ", i, base, size); 1480 #ifdef ARMADAXP 1481 armadaxp_attr_dump(sc, target, attr); 1482 #else 1483 mvsoc_attr_dump(sc, target, attr); 1484 #endif 1485 printf("\n"); 1486 n++; 1487 } 1488 1489 return n; 1490 } 1491 1492 int 1493 mvsoc_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr) 1494 { 1495 aprint_verbose_dev(sc->sc_dev, "target 0x%x(attr 0x%x)", target, attr); 1496 return 0; 1497 } 1498
Indexes created Sun Sep 21 14:09:52 GMT 2025