1 /* $NetBSD: ibm4xx_460ex_l2.c,v 1.2 2026/09/28 20:41:00 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * AMCC PPC460EX on-chip 256KB L2 cache support 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: ibm4xx_460ex_l2.c,v 1.2 2026/09/28 20:41:00 rkujawa Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 42 #include <powerpc/ibm4xx/cpu.h> 43 #include <powerpc/ibm4xx/amcc460ex.h> 44 #include <powerpc/ibm4xx/ibm4xx_460ex_l2.h> 45 46 bool ibm4xx_460ex_l2_enabled = false; 47 uint32_t ibm4xx_460ex_l2_cfg; 48 49 static void 50 ibm4xx_460ex_l2_cmd(uint32_t cmd) 51 { 52 53 mtdcr(DCR_L2C0_CMD, cmd); 54 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0) 55 ; 56 } 57 58 /* 59 * Enable L2 cache, as write-through, with hardware snooping on the 60 * low latency PLB segment. 61 */ 62 void 63 ibm4xx_460ex_l2cache_enable(void) 64 { 65 uint32_t cfg; 66 67 /* Hand the SRAM0 data arrays back from the SRAM controller. */ 68 mtdcr(DCR_SRAM0_SB0CR, 0); 69 mtdcr(DCR_SRAM0_SB1CR, 0); 70 mtdcr(DCR_SRAM0_SB2CR, 0); 71 mtdcr(DCR_SRAM0_SB3CR, 0); 72 73 /* RDBW is required; switch the array into L2 mode. */ 74 mtdcr(DCR_L2C0_CFG, L2C_CFG_RDBW | L2C_CFG_L2M | L2C_CFG_SS_256KB); 75 76 /* Clear the array and any parity errors. */ 77 mtdcr(DCR_L2C0_ADDR, 0); 78 ibm4xx_460ex_l2_cmd(L2C_CMD_HCC); 79 ibm4xx_460ex_l2_cmd(L2C_CMD_CCP); 80 ibm4xx_460ex_l2_cmd(L2C_CMD_CTE); 81 __asm volatile ("msync" ::: "memory"); 82 83 /* All of the LL, and the HB alias. */ 84 mtdcr(DCR_L2C0_SNP0, L2C_SNP_SSR_32GB | L2C_SNP_ESR); 85 mtdcr(DCR_L2C0_SNP1, 0x80000000 | L2C_SNP_SSR_32GB | L2C_SNP_ESR); 86 __asm volatile ("sync; isync" ::: "memory"); 87 88 cfg = mfdcr(DCR_L2C0_CFG); 89 cfg &= ~(L2C_CFG_DCW | L2C_CFG_PMUX | L2C_CFG_PMIM | L2C_CFG_TPEI | 90 L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM); 91 cfg |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | 92 L2C_CFG_FRAN | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | 93 L2C_CFG_SMCM | L2C_CFG_SNP440 | L2C_CFG_RDBW; 94 mtdcr(DCR_L2C0_CFG, cfg); 95 __asm volatile ("sync; isync" ::: "memory"); 96 97 ibm4xx_460ex_l2_cfg = mfdcr(DCR_L2C0_CFG); 98 if (ibm4xx_460ex_l2_cfg & L2C_CFG_L2M) 99 ibm4xx_460ex_l2_enabled = true; 100 } 101
Indexes created Sun Oct 25 00:26:45 UTC 2026