1 /* $NetBSD: obio.c,v 1.13 2023/07/13 19:42:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec Corporation may not be used to endorse or 16 * promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * TODO: dispatch interrupt to SOFTSERIAL or SOFTNET according to requested 34 * interrupt level. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.13 2023/07/13 19:42:24 riastradh Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/kernel.h> 44 #include <sys/reboot.h> 45 #include <sys/bitops.h> 46 47 #include <machine/cpu.h> 48 #include <sys/bus.h> 49 #include <machine/intr.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/mainbus/mainbus.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_gpio.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 #include <evbarm/lubbock/lubbock_reg.h> 58 #include <evbarm/lubbock/lubbock_var.h> 59 60 #include "locators.h" 61 62 /* prototypes */ 63 static int obio_match(device_t, cfdata_t, void *); 64 static void obio_attach(device_t, device_t, void *); 65 static int obio_search(device_t, cfdata_t, const int *, void *); 66 static int obio_print(void *, const char *); 67 68 /* attach structures */ 69 CFATTACH_DECL_NEW(obio, sizeof(struct obio_softc), obio_match, obio_attach, 70 NULL, NULL); 71 72 uint32_t obio_intr_mask; 73 74 static int 75 obio_spurious(void *arg) 76 { 77 int irqno = (int)arg; 78 79 aprint_normal("Spurious interrupt %d on On-board peripheral", irqno); 80 return 1; 81 } 82 83 84 /* 85 * interrupt handler for GPIO0 (on-board peripherals) 86 * 87 * On Lubbock, 8 interrupts are ORed through on-board logic, 88 * and routed to GPIO0 of PXA250 processor. 89 */ 90 static int 91 obio_intr(void *arg) 92 { 93 int irqno, pending, mask; 94 struct obio_softc *sc = (struct obio_softc *)arg; 95 int psw; 96 97 mask = sc->sc_obio_intr_mask; /* real irq mask for obio */ 98 99 psw = disable_interrupts(I32_bit|F32_bit); 100 pending = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, 101 LUBBOCK_INTRCTL); 102 /* Here is a chance to lose some interrupts. 103 * You need to modify FPGA program to avoid it 104 */ 105 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, LUBBOCK_INTRCTL, 0); 106 restore_interrupts(psw); 107 108 109 pending &= mask; 110 while (pending) { 111 irqno = 0; 112 113 for ( ;pending; ++irqno) { 114 if (0 == (pending & (1U<<irqno))) 115 continue; 116 pending &= ~(1U<<irqno); 117 118 #ifdef notyet 119 /* if ipl of this irq is higher than current spl level, 120 call the handler directly instead of dispatching it to 121 software interrupt. */ 122 if (sc->sc_handler[irqno].level > curcpl()) { 123 (* sc->sc_handler[irqno].func)( 124 sc->sc_handler[irqno].arg ); 125 } 126 else 127 #endif 128 { 129 /* mask this interrupt until software 130 interrupt is handled. */ 131 sc->sc_obio_intr_pending |= (1U<<irqno); 132 mask &= ~(1U<<irqno); 133 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 134 LUBBOCK_INTRMASK, mask); 135 136 /* handle it later */ 137 softint_schedule(sc->sc_si); 138 } 139 } 140 141 psw = disable_interrupts(I32_bit|F32_bit); 142 pending = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, 143 LUBBOCK_INTRCTL); 144 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 145 LUBBOCK_INTRCTL,0); 146 restore_interrupts(psw); 147 pending &= mask; 148 } 149 150 /* GPIO interrupt is edge triggered. make a pulse 151 to let Cotulla notice when other interrupts are 152 still pending */ 153 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, LUBBOCK_INTRMASK, 0); 154 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, LUBBOCK_INTRMASK, mask); 155 return 1; 156 } 157 158 static void 159 obio_softintr(void *arg) 160 { 161 struct obio_softc *sc = (struct obio_softc *)arg; 162 int irqno; 163 int psw; 164 int spl_save = curcpl(); 165 166 psw = disable_interrupts(I32_bit); 167 while ((irqno = fls32(sc->sc_obio_intr_pending) - 1) >= 0) { 168 sc->sc_obio_intr_pending &= ~(1U<<irqno); 169 170 restore_interrupts(psw); 171 172 _splraise(sc->sc_handler[irqno].level); 173 (* sc->sc_handler[irqno].func)( 174 sc->sc_handler[irqno].arg); 175 splx(spl_save); 176 177 psw = disable_interrupts(I32_bit); 178 } 179 180 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 181 LUBBOCK_INTRMASK, sc->sc_obio_intr_mask); 182 183 restore_interrupts(psw); 184 } 185 186 /* 187 * int obio_print(void *aux, const char *name) 188 * print configuration info for children 189 */ 190 191 static int 192 obio_print(void *aux, const char *name) 193 { 194 struct obio_attach_args *oba = (struct obio_attach_args*)aux; 195 196 if (oba->oba_addr != OBIOCF_ADDR_DEFAULT) 197 aprint_normal(" addr 0x%lx", oba->oba_addr); 198 if (oba->oba_intr > 0) 199 aprint_normal(" intr %d", oba->oba_intr); 200 return (UNCONF); 201 } 202 203 int 204 obio_match(device_t parent, cfdata_t match, void *aux) 205 { 206 return 1; 207 } 208 209 void 210 obio_attach(device_t parent, device_t self, void *aux) 211 { 212 struct obio_softc *sc = device_private(self); 213 int system_id, baseboard_id, expansion_id, processor_card_id; 214 struct pxaip_attach_args *sa = (struct pxaip_attach_args *)aux; 215 const char *processor_card_name; 216 int i; 217 218 219 /* Map on-board FPGA registers */ 220 sc->sc_dev = self; 221 sc->sc_iot = &pxa2x0_bs_tag; 222 if (bus_space_map(sc->sc_iot, LUBBOCK_OBIO_PBASE, LUBBOCK_OBIO_SIZE, 223 0, &(sc->sc_obioreg_ioh))) { 224 aprint_normal_dev(self, "can't map FPGA registers\n"); 225 } 226 227 system_id = bus_space_read_4(sc->sc_iot, sc->sc_obioreg_ioh, 228 LUBBOCK_SYSTEMID); 229 230 baseboard_id = (system_id>>8) & 0x0f; 231 expansion_id = (system_id>>4) & 0x0f; 232 processor_card_id = system_id & 0x0f; 233 234 switch (processor_card_id) { 235 case 0: processor_card_name = "Cotulla"; break; 236 case 1: processor_card_name = "Sabinal"; break; 237 default: processor_card_name = "(unknown)"; 238 } 239 240 printf(" : baseboard=%d (%s), expansion card=%d, processor card=%d (%s)\n", 241 baseboard_id, 242 baseboard_id==8 ? "DBPXA250(lubbock)" : "(unknown)", 243 expansion_id, 244 processor_card_id, processor_card_name ); 245 246 /* 247 * Mask all interrupts. 248 * They are later unmasked at each device's attach routine. 249 */ 250 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 251 LUBBOCK_INTRMASK,0); 252 253 sc->sc_intr = sa->pxa_intr; /* irq no. on ICU. */ 254 sc->sc_obio_intr_mask = 0; /* No interrupt used */ 255 sc->sc_obio_intr_pending = 0; 256 sc->sc_ipl = IPL_BIO; 257 258 for (i=0; i < N_OBIO_IRQ; ++i) { 259 sc->sc_handler[i].func = obio_spurious; 260 sc->sc_handler[i].arg = (void *)i; 261 } 262 263 264 /* 265 * establish interrupt handler. 266 */ 267 #if 0 268 /* 269 * level is lowest at first, and changed when 270 * sub-interrupt handlers are established 271 */ 272 sc->sc_ipl = IPL_BIO; 273 #else 274 /* 275 * level is very high to allow high priority sub-interrupts. 276 */ 277 sc->sc_ipl = IPL_AUDIO; 278 #endif 279 sc->sc_ih = pxa2x0_gpio_intr_establish(0, IST_EDGE_FALLING, sc->sc_ipl, 280 obio_intr, sc); 281 sc->sc_si = softint_establish(SOFTINT_NET, obio_softintr, sc); 282 283 284 /* 285 * Attach each devices 286 */ 287 config_search(self, NULL, 288 CFARGS(.search = obio_search)); 289 } 290 291 int 292 obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 293 { 294 struct obio_softc *sc = device_private(parent); 295 struct obio_attach_args oba; 296 297 oba.oba_sc = sc; 298 oba.oba_iot = sc->sc_iot; 299 oba.oba_addr = cf->cf_loc[OBIOCF_ADDR]; 300 oba.oba_intr = cf->cf_loc[OBIOCF_INTR]; 301 302 if (config_probe(parent, cf, &oba)) 303 config_attach(parent, cf, &oba, obio_print, CFARGS_NONE); 304 305 return 0; 306 } 307 308 void * 309 obio_intr_establish(struct obio_softc *sc, 310 int irq, int ipl, int (*func)(void *), void *arg) 311 { 312 int psw; 313 314 if (irq < 0 || N_OBIO_IRQ <= irq) 315 panic("Bad irq no for obio"); 316 317 psw = disable_interrupts(I32_bit); 318 319 sc->sc_handler[irq].func = func; 320 sc->sc_handler[irq].arg = arg; 321 sc->sc_handler[irq].level = ipl; 322 323 #ifdef notyet 324 if (ipl > sc->sc_ipl) { 325 pxa2x0_update_intr_masks(sc->sc_intr, ipl); 326 sc->sc_ipl = ipl; 327 } 328 #endif 329 330 sc->sc_obio_intr_mask |= (1U << irq); 331 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 332 LUBBOCK_INTRMASK, sc->sc_obio_intr_mask); 333 334 enable_interrupts(psw); 335 return &sc->sc_handler[irq]; 336 } 337
Indexes created Wed Oct 01 19:09:53 GMT 2025