1 /* $NetBSD: omap3_cm.c,v 1.5 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: omap3_cm.c,v 1.5 2021/01/27 03:10:20 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #define TI_PRCM_PRIVATE 41 #include <arm/ti/ti_prcm.h> 42 43 #define CM_CORE1_BASE 0x0a00 44 #define CM_CORE3_BASE 0x0a08 45 #define CM_WKUP_BASE 0x0c00 46 #define CM_PER_BASE 0x1000 47 #define CM_USBHOST_BASE 0x1400 48 49 #define CM_FCLKEN 0x00 50 #define CM_ICLKEN 0x10 51 #define CM_AUTOIDLE 0x30 52 #define CM_CLKSEL 0x40 53 54 static int omap3_cm_match(device_t, cfdata_t, void *); 55 static void omap3_cm_attach(device_t, device_t, void *); 56 57 static int 58 omap3_cm_hwmod_nopenable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 59 { 60 return 0; 61 } 62 63 static int 64 omap3_cm_hwmod_enable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 65 { 66 uint32_t val; 67 68 val = PRCM_READ(sc, tc->u.hwmod.reg + CM_FCLKEN); 69 if (enable) 70 val |= tc->u.hwmod.mask; 71 else 72 val &= ~tc->u.hwmod.mask; 73 PRCM_WRITE(sc, tc->u.hwmod.reg + CM_FCLKEN, val); 74 75 val = PRCM_READ(sc, tc->u.hwmod.reg + CM_ICLKEN); 76 if (enable) 77 val |= tc->u.hwmod.mask; 78 else 79 val &= ~tc->u.hwmod.mask; 80 PRCM_WRITE(sc, tc->u.hwmod.reg + CM_ICLKEN, val); 81 82 if (tc->u.hwmod.flags & TI_HWMOD_DISABLE_AUTOIDLE) { 83 val = PRCM_READ(sc, tc->u.hwmod.reg + CM_AUTOIDLE); 84 val &= ~tc->u.hwmod.mask; 85 PRCM_WRITE(sc, tc->u.hwmod.reg + CM_AUTOIDLE, val); 86 } 87 88 return 0; 89 } 90 91 #define OMAP3_CM_HWMOD_CORE1(_name, _bit, _parent, _flags) \ 92 TI_PRCM_HWMOD_MASK((_name), CM_CORE1_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) 93 #define OMAP3_CM_HWMOD_CORE3(_name, _bit, _parent, _flags) \ 94 TI_PRCM_HWMOD_MASK((_name), CM_CORE3_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) 95 #define OMAP3_CM_HWMOD_WKUP(_name, _bit, _parent, _flags) \ 96 TI_PRCM_HWMOD_MASK((_name), CM_WKUP_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) 97 #define OMAP3_CM_HWMOD_PER(_name, _bit, _parent, _flags) \ 98 TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) 99 #define OMAP3_CM_HWMOD_USBHOST(_name, _bit, _parent, _flags) \ 100 TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) 101 #define OMAP3_CM_HWMOD_NOP(_name, _parent) \ 102 TI_PRCM_HWMOD_MASK((_name), 0, 0, (_parent), omap3_cm_hwmod_nopenable, 0) 103 104 static const struct device_compatible_entry compat_data[] = { 105 { .compat = "ti,omap3-cm" }, 106 DEVICE_COMPAT_EOL 107 }; 108 109 CFATTACH_DECL_NEW(omap3_cm, sizeof(struct ti_prcm_softc), 110 omap3_cm_match, omap3_cm_attach, NULL, NULL); 111 112 static struct ti_prcm_clk omap3_cm_clks[] = { 113 /* XXX until we get a proper clock tree */ 114 TI_PRCM_FIXED("FIXED_32K", 32768), 115 TI_PRCM_FIXED("SYS_CLK", 13000000), 116 TI_PRCM_FIXED("MMC_CLK", 96000000), 117 TI_PRCM_FIXED_FACTOR("PERIPH_CLK", 1, 1, "SYS_CLK"), 118 119 OMAP3_CM_HWMOD_CORE1("usb_otg_hs", 4, "PERIPH_CLK", 0), 120 OMAP3_CM_HWMOD_CORE1("mcbsp1", 9, "PERIPH_CLK", 0), 121 OMAP3_CM_HWMOD_CORE1("mcbsp5", 10, "PERIPH_CLK", 0), 122 OMAP3_CM_HWMOD_CORE1("timer10", 11, "PERIPH_CLK", 0), 123 OMAP3_CM_HWMOD_CORE1("timer11", 12, "PERIPH_CLK", 0), 124 OMAP3_CM_HWMOD_CORE1("uart1", 13, "PERIPH_CLK", 0), 125 OMAP3_CM_HWMOD_CORE1("uart2", 14, "PERIPH_CLK", 0), 126 OMAP3_CM_HWMOD_CORE1("i2c1", 15, "PERIPH_CLK", 0), 127 OMAP3_CM_HWMOD_CORE1("i2c2", 16, "PERIPH_CLK", 0), 128 OMAP3_CM_HWMOD_CORE1("i2c3", 17, "PERIPH_CLK", 0), 129 OMAP3_CM_HWMOD_CORE1("mcspi1", 18, "PERIPH_CLK", 0), 130 OMAP3_CM_HWMOD_CORE1("mcspi2", 19, "PERIPH_CLK", 0), 131 OMAP3_CM_HWMOD_CORE1("mcspi3", 20, "PERIPH_CLK", 0), 132 OMAP3_CM_HWMOD_CORE1("mcspi4", 21, "PERIPH_CLK", 0), 133 OMAP3_CM_HWMOD_CORE1("hdq1w", 22, "PERIPH_CLK", 0), 134 OMAP3_CM_HWMOD_CORE1("mmc1", 24, "MMC_CLK", 0), 135 OMAP3_CM_HWMOD_CORE1("mmc2", 25, "MMC_CLK", 0), 136 OMAP3_CM_HWMOD_CORE1("mmc3", 30, "MMC_CLK", 0), 137 138 OMAP3_CM_HWMOD_CORE3("usb_tll_hs", 2, "PERIPH_CLK", TI_HWMOD_DISABLE_AUTOIDLE), 139 140 OMAP3_CM_HWMOD_WKUP("timer1", 0, "PERIPH_CLK", 0), 141 OMAP3_CM_HWMOD_WKUP("counter_32k", 2, "FIXED_32K", 0), 142 OMAP3_CM_HWMOD_WKUP("gpio1", 3, "PERIPH_CLK", 0), 143 OMAP3_CM_HWMOD_WKUP("wd_timer2", 5, "FIXED_32K", 0), 144 145 OMAP3_CM_HWMOD_PER("mcbsp2", 0, "PERIPH_CLK", 0), 146 OMAP3_CM_HWMOD_PER("mcbsp3", 1, "PERIPH_CLK", 0), 147 OMAP3_CM_HWMOD_PER("mcbsp4", 2, "PERIPH_CLK", 0), 148 OMAP3_CM_HWMOD_PER("timer2", 3, "PERIPH_CLK", 0), 149 OMAP3_CM_HWMOD_PER("timer3", 4, "PERIPH_CLK", 0), 150 OMAP3_CM_HWMOD_PER("timer4", 5, "PERIPH_CLK", 0), 151 OMAP3_CM_HWMOD_PER("timer5", 6, "PERIPH_CLK", 0), 152 OMAP3_CM_HWMOD_PER("timer6", 7, "PERIPH_CLK", 0), 153 OMAP3_CM_HWMOD_PER("timer7", 8, "PERIPH_CLK", 0), 154 OMAP3_CM_HWMOD_PER("timer8", 9, "PERIPH_CLK", 0), 155 OMAP3_CM_HWMOD_PER("timer9", 10, "PERIPH_CLK", 0), 156 OMAP3_CM_HWMOD_PER("uart3", 11, "PERIPH_CLK", 0), 157 OMAP3_CM_HWMOD_PER("wd_timer3", 12, "PERIPH_CLK", 0), 158 OMAP3_CM_HWMOD_PER("gpio2", 13, "PERIPH_CLK", 0), 159 OMAP3_CM_HWMOD_PER("gpio3", 14, "PERIPH_CLK", 0), 160 OMAP3_CM_HWMOD_PER("gpio4", 15, "PERIPH_CLK", 0), 161 OMAP3_CM_HWMOD_PER("gpio5", 16, "PERIPH_CLK", 0), 162 OMAP3_CM_HWMOD_PER("gpio6", 17, "PERIPH_CLK", 0), 163 164 OMAP3_CM_HWMOD_USBHOST("usb_host_hs", 0, "PERIPH_CLK", 0), 165 166 OMAP3_CM_HWMOD_NOP("gpmc", "PERIPH_CLK"), 167 }; 168 169 static void 170 omap3_cm_initclocks(struct ti_prcm_softc *sc) 171 { 172 uint32_t val; 173 174 /* Select SYS_CLK for GPTIMER 2 and 3 */ 175 val = PRCM_READ(sc, CM_PER_BASE + CM_CLKSEL); 176 val |= __BIT(0); /* CLKSEL_GPT2 0x1: source is SYS_CLK */ 177 val |= __BIT(1); /* CLKSEL_GPT3 0x1: source is SYS_CLK */ 178 PRCM_WRITE(sc, CM_PER_BASE + CM_CLKSEL, val); 179 } 180 181 static int 182 omap3_cm_match(device_t parent, cfdata_t cf, void *aux) 183 { 184 struct fdt_attach_args * const faa = aux; 185 186 return of_compatible_match(faa->faa_phandle, compat_data); 187 } 188 189 static void 190 omap3_cm_attach(device_t parent, device_t self, void *aux) 191 { 192 struct ti_prcm_softc * const sc = device_private(self); 193 struct fdt_attach_args * const faa = aux; 194 int clocks; 195 196 sc->sc_dev = self; 197 sc->sc_phandle = faa->faa_phandle; 198 sc->sc_bst = faa->faa_bst; 199 200 sc->sc_clks = omap3_cm_clks; 201 sc->sc_nclks = __arraycount(omap3_cm_clks); 202 203 if (ti_prcm_attach(sc) != 0) 204 return; 205 206 aprint_naive("\n"); 207 aprint_normal(": OMAP3xxx CM\n"); 208 209 omap3_cm_initclocks(sc); 210 211 clocks = of_find_firstchild_byname(sc->sc_phandle, "clocks"); 212 if (clocks > 0) 213 fdt_add_bus(self, clocks, faa); 214 } 215
Indexes created Fri Sep 26 08:10:20 GMT 2025