| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 5871 unsigned opc1 = fieldFromInstruction(Val, 4, 4); local
5889 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5890 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5899 Inst.addOperand(MCOperand::createImm(opc1));
|
| /src/external/gpl3/gdb/dist/gdb/ |
| arm-tdep.c | 12890 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12896 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
12902 opc1 = opc1 & ~0x04;
12905 if (opc1 == 0x00)
12923 else if (opc1 == 0x01)
12931 else if (opc1 == 0x02 && !(opc3 & 0x01))
12949 else if (opc1 == 0x03)
12967 else if (opc1 == 0x08)
12975 else if (opc1 == 0x0b
12889 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; local
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| arm-tdep.c | 12894 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12900 opc1 = bits (arm_insn_r->arm_insn, 20, 23);
12906 opc1 = opc1 & ~0x04;
12909 if (opc1 == 0x00)
12927 else if (opc1 == 0x01)
12935 else if (opc1 == 0x02 && !(opc3 & 0x01))
12953 else if (opc1 == 0x03)
12971 else if (opc1 == 0x08)
12979 else if (opc1 == 0x0b
12893 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; local
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 9443 int opc1; member in struct:deprecated_coproc_regs_s
9511 && inst.operands[1].imm == r->opc1
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 9446 int opc1; member in struct:deprecated_coproc_regs_s
9514 && inst.operands[1].imm == r->opc1
|
