| /src/sys/arch/sparc/fpu/ |
| fpu.c | 305 int opf, rs1, rs2, rd, type, mask, fsr, cx; local
308 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; local
318 opf = instr.i_opf.i_opf;
320 * The low two bits of the opf field for floating point insns usually
334 type = opf & 3;
356 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) {
357 switch (opf >>= 2) {
446 ("fpu_execute: unknown v9 FP inst %x opf %x\n",
447 instr.i_int, opf));
452 switch (opf >>= 2)
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-sh.c | 1791 int opf;
1794 for (opf = 0; opf < 4; opf ++)
1795 switch (this_try->nibbles[opf])
1789 int opf; local
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-sh.c | 1791 int opf;
1794 for (opf = 0; opf < 4; opf ++)
1795 switch (this_try->nibbles[opf])
1789 int opf; local
|
| /src/external/gpl3/gdb/dist/sim/erc32/ |
| exec.c | 1677 uint32_t opf, tem, accex; local
1690 opf = (sregs->inst >> 5) & 0x1ff;
1708 if (((opf >> 6) == 0) || ((opf >> 6) == 3))
1713 ldadj = opf & 1;
1736 switch (opf) {
1757 switch (opf) {
1785 if ((fcc == 0) && (opf == FCMPEs)) {
1804 if ((fcc == 0) && (opf == FCMPEd)) {
1913 switch (opf) {
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/erc32/ |
| exec.c | 1677 uint32_t opf, tem, accex; local
1690 opf = (sregs->inst >> 5) & 0x1ff;
1708 if (((opf >> 6) == 0) || ((opf >> 6) == 3))
1713 ldadj = opf & 1;
1736 switch (opf) {
1757 switch (opf) {
1785 if ((fcc == 0) && (opf == FCMPEs)) {
1804 if ((fcc == 0) && (opf == FCMPEd)) {
1913 switch (opf) {
[all...] |
