1 /* $NetBSD: dwiic_pci.c,v 1.13 2025/09/15 15:31:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Synopsys DesignWare I2C controller, PCI front-end 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.13 2025/09/15 15:31:44 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_pci.h> 47 #include <dev/acpi/acpi_util.h> 48 49 #include <dev/ic/dwiic_var.h> 50 #include <arch/x86/pci/lpssreg.h> 51 52 #include "acpica.h" 53 54 //#define DWIIC_DEBUG 55 56 #ifdef DWIIC_DEBUG 57 #define DPRINTF(x) printf x 58 #else 59 #define DPRINTF(x) 60 #endif 61 62 #if NACPICA > 0 63 #define I2C_USE_ACPI 64 #endif /* NACPICA > 0 */ 65 66 struct pci_dwiic_softc { 67 struct dwiic_softc sc_dwiic; 68 pci_chipset_tag_t sc_pc; 69 pcitag_t sc_ptag; 70 }; 71 72 #define VIDDID(a, b) PCI_ID_CODE(PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b) 73 74 static const struct device_compatible_entry compat_data[] = { 75 { .id = VIDDID(INTEL, CORE4G_M_S_I2C_0) }, 76 { .id = VIDDID(INTEL, CORE4G_M_S_I2C_1) }, 77 { .id = VIDDID(INTEL, 100SERIES_I2C_0) }, 78 { .id = VIDDID(INTEL, 100SERIES_I2C_1) }, 79 { .id = VIDDID(INTEL, 100SERIES_I2C_2) }, 80 { .id = VIDDID(INTEL, 100SERIES_I2C_3) }, 81 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_0) }, 82 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_1) }, 83 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_2) }, 84 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_3) }, 85 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_4) }, 86 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_5) }, 87 { .id = VIDDID(INTEL, 2HS_I2C_0) }, 88 { .id = VIDDID(INTEL, 2HS_I2C_1) }, 89 { .id = VIDDID(INTEL, 2HS_I2C_2) }, 90 { .id = VIDDID(INTEL, 2HS_I2C_3) }, 91 { .id = VIDDID(INTEL, 3HS_I2C_0) }, 92 { .id = VIDDID(INTEL, 3HS_I2C_1) }, 93 { .id = VIDDID(INTEL, 3HS_I2C_2) }, 94 { .id = VIDDID(INTEL, 3HS_I2C_3) }, 95 { .id = VIDDID(INTEL, 3HS_U_I2C_0) }, 96 { .id = VIDDID(INTEL, 3HS_U_I2C_1) }, 97 { .id = VIDDID(INTEL, 3HS_U_I2C_2) }, 98 { .id = VIDDID(INTEL, 3HS_U_I2C_3) }, 99 { .id = VIDDID(INTEL, 3HS_U_I2C_4) }, 100 { .id = VIDDID(INTEL, 3HS_U_I2C_5) }, 101 { .id = VIDDID(INTEL, 4HS_H_I2C_0) }, 102 { .id = VIDDID(INTEL, 4HS_H_I2C_1) }, 103 { .id = VIDDID(INTEL, 4HS_H_I2C_2) }, 104 { .id = VIDDID(INTEL, 4HS_H_I2C_3) }, 105 { .id = VIDDID(INTEL, 4HS_V_I2C_0) }, 106 { .id = VIDDID(INTEL, 4HS_V_I2C_1) }, 107 { .id = VIDDID(INTEL, 4HS_V_I2C_2) }, 108 { .id = VIDDID(INTEL, 4HS_V_I2C_3) }, 109 { .id = VIDDID(INTEL, CMTLK_I2C_0) }, /* 4HS LP */ 110 { .id = VIDDID(INTEL, CMTLK_I2C_1) }, 111 { .id = VIDDID(INTEL, CMTLK_I2C_2) }, 112 { .id = VIDDID(INTEL, CMTLK_I2C_3) }, 113 { .id = VIDDID(INTEL, CMTLK_I2C_4) }, 114 { .id = VIDDID(INTEL, CMTLK_I2C_5) }, 115 { .id = VIDDID(INTEL, 495_YU_I2C_0) }, 116 { .id = VIDDID(INTEL, 495_YU_I2C_1) }, 117 { .id = VIDDID(INTEL, 495_YU_I2C_2) }, 118 { .id = VIDDID(INTEL, 495_YU_I2C_3) }, 119 { .id = VIDDID(INTEL, 495_YU_I2C_4) }, 120 { .id = VIDDID(INTEL, 495_YU_I2C_5) }, 121 { .id = VIDDID(INTEL, 5HS_H_I2C_0) }, 122 { .id = VIDDID(INTEL, 5HS_H_I2C_1) }, 123 { .id = VIDDID(INTEL, 5HS_H_I2C_2) }, 124 { .id = VIDDID(INTEL, 5HS_H_I2C_3) }, 125 { .id = VIDDID(INTEL, 5HS_H_I2C_4) }, 126 { .id = VIDDID(INTEL, 5HS_H_I2C_5) }, 127 { .id = VIDDID(INTEL, 5HS_H_I2C_6) }, 128 { .id = VIDDID(INTEL, 5HS_LP_I2C_0) }, 129 { .id = VIDDID(INTEL, 5HS_LP_I2C_1) }, 130 { .id = VIDDID(INTEL, 5HS_LP_I2C_2) }, 131 { .id = VIDDID(INTEL, 5HS_LP_I2C_3) }, 132 { .id = VIDDID(INTEL, 5HS_LP_I2C_4) }, 133 { .id = VIDDID(INTEL, 5HS_LP_I2C_5) }, 134 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C1) }, 135 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C2) }, 136 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C3) }, 137 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C4) }, 138 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C5) }, 139 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C6) }, 140 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C7) }, 141 { .id = VIDDID(INTEL, BSW_SIO_I2C_1) }, 142 { .id = VIDDID(INTEL, BSW_SIO_I2C_2) }, 143 { .id = VIDDID(INTEL, BSW_SIO_I2C_3) }, 144 { .id = VIDDID(INTEL, BSW_SIO_I2C_4) }, 145 { .id = VIDDID(INTEL, BSW_SIO_I2C_5) }, 146 { .id = VIDDID(INTEL, BSW_SIO_I2C_6) }, 147 { .id = VIDDID(INTEL, BSW_SIO_I2C_7) }, 148 { .id = VIDDID(INTEL, APL_I2C_0) }, 149 { .id = VIDDID(INTEL, APL_I2C_1) }, 150 { .id = VIDDID(INTEL, APL_I2C_2) }, 151 { .id = VIDDID(INTEL, APL_I2C_3) }, 152 { .id = VIDDID(INTEL, APL_I2C_4) }, 153 { .id = VIDDID(INTEL, APL_I2C_5) }, 154 { .id = VIDDID(INTEL, APL_I2C_6) }, 155 { .id = VIDDID(INTEL, APL_I2C_7) }, 156 { .id = VIDDID(INTEL, GLK_I2C_0) }, 157 { .id = VIDDID(INTEL, GLK_I2C_1) }, 158 { .id = VIDDID(INTEL, GLK_I2C_2) }, 159 { .id = VIDDID(INTEL, GLK_I2C_3) }, 160 { .id = VIDDID(INTEL, GLK_I2C_4) }, 161 { .id = VIDDID(INTEL, GLK_I2C_5) }, 162 { .id = VIDDID(INTEL, GLK_I2C_6) }, 163 { .id = VIDDID(INTEL, GLK_I2C_7) }, 164 { .id = VIDDID(INTEL, EHL_SIO_I2C_0) }, 165 { .id = VIDDID(INTEL, EHL_SIO_I2C_1) }, 166 { .id = VIDDID(INTEL, EHL_SIO_I2C_2) }, 167 { .id = VIDDID(INTEL, EHL_SIO_I2C_3) }, 168 { .id = VIDDID(INTEL, EHL_SIO_I2C_4) }, 169 { .id = VIDDID(INTEL, EHL_SIO_I2C_5) }, 170 { .id = VIDDID(INTEL, EHL_SIO_I2C_6) }, 171 { .id = VIDDID(INTEL, EHL_SIO_I2C_7) }, 172 { .id = VIDDID(INTEL, JSL_LPSS_I2C_0) }, 173 { .id = VIDDID(INTEL, JSL_LPSS_I2C_1) }, 174 { .id = VIDDID(INTEL, JSL_LPSS_I2C_2) }, 175 { .id = VIDDID(INTEL, JSL_LPSS_I2C_3) }, 176 { .id = VIDDID(INTEL, JSL_LPSS_I2C_4) }, 177 { .id = VIDDID(INTEL, JSL_LPSS_I2C_5) }, 178 179 PCI_COMPAT_EOL 180 }; 181 182 static uint32_t 183 lpss_read(struct pci_dwiic_softc *sc, int offset) 184 { 185 return bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 186 offset); 187 } 188 189 static void 190 lpss_write(struct pci_dwiic_softc *sc, int offset, uint32_t val) 191 { 192 bus_space_write_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 193 offset, val); 194 } 195 196 static int pci_dwiic_match(device_t, cfdata_t, void *); 197 static void pci_dwiic_attach(device_t, device_t, void *); 198 static bool dwiic_pci_power(struct dwiic_softc *, bool); 199 200 CFATTACH_DECL_NEW(pcidwiic, sizeof(struct pci_dwiic_softc), 201 pci_dwiic_match, pci_dwiic_attach, dwiic_detach, NULL); 202 203 204 int 205 pci_dwiic_match(device_t parent, cfdata_t match, void *aux) 206 { 207 struct pci_attach_args *pa = aux; 208 209 return pci_compatible_match(pa, compat_data); 210 } 211 212 void 213 pci_dwiic_attach(device_t parent, device_t self, void *aux) 214 { 215 struct pci_dwiic_softc *sc = device_private(self); 216 struct pci_attach_args *pa = aux; 217 const char *intrstr; 218 pci_intr_handle_t intrhandle; 219 char intrbuf[PCI_INTRSTR_LEN]; 220 pcireg_t memtype; 221 pcireg_t csr; 222 uint32_t caps; 223 224 sc->sc_dwiic.sc_dev = self; 225 sc->sc_dwiic.sc_power = dwiic_pci_power; 226 sc->sc_dwiic.sc_type = dwiic_type_sunrisepoint; 227 228 sc->sc_pc = pa->pa_pc; 229 sc->sc_ptag = pa->pa_tag; 230 231 /* register access not enabled by BIOS */ 232 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 234 csr | PCI_COMMAND_MEM_ENABLE); 235 236 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0); 237 if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &sc->sc_dwiic.sc_iot, 238 &sc->sc_dwiic.sc_ioh, NULL, NULL) != 0) { 239 aprint_error(": can't map register space\n"); 240 goto out; 241 } 242 dwiic_pci_power(&sc->sc_dwiic, 1); 243 244 caps = lpss_read(sc, LPSS_CAP); 245 246 aprint_naive(": I2C controller\n"); 247 aprint_normal(": I2C controller instance %d\n", 248 (int)(caps & LPSS_CAP_INSTANCE)); 249 250 if (pci_intr_map(pa, &intrhandle)) { 251 aprint_error_dev(self, "can't map interrupt\n"); 252 goto out; 253 } 254 intrstr = pci_intr_string(pa->pa_pc, intrhandle, 255 intrbuf, sizeof(intrbuf)); 256 257 sc->sc_dwiic.sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 258 IPL_VM, dwiic_intr, sc); 259 if (sc->sc_dwiic.sc_ih == NULL) { 260 aprint_error_dev(self, "couldn't establish interrupt"); 261 if (intrstr != NULL) 262 aprint_error(" at %s", intrstr); 263 aprint_error("\n"); 264 goto out; 265 } 266 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 267 268 lpss_write(sc, LPSS_RESET, LPSS_RESET_CTRL_REL); 269 lpss_write(sc, LPSS_REMAP_LO, 270 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0)); 271 lpss_write(sc, LPSS_REMAP_HI, 272 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0 + 0x4)); 273 274 if (!dwiic_attach(&sc->sc_dwiic)) 275 goto out; 276 277 iicbus_attach(self, &sc->sc_dwiic.sc_i2c_tag); 278 279 pmf_device_register(self, dwiic_suspend, dwiic_resume); 280 281 out: 282 return; 283 } 284 285 static bool 286 dwiic_pci_power(struct dwiic_softc *dwsc, bool power) 287 { 288 struct pci_dwiic_softc *sc = container_of(dwsc, struct pci_dwiic_softc, 289 sc_dwiic); 290 pcireg_t pmreg, csr; 291 uint32_t reset, rlo, rhi; 292 293 csr = pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG); 294 reset = lpss_read(sc, LPSS_RESET); 295 rlo = lpss_read(sc, LPSS_REMAP_LO); 296 rhi = lpss_read(sc, LPSS_REMAP_HI); 297 aprint_debug_dev(dwsc->sc_dev, 298 "status 0x%x reset 0x%x rlo 0x%x rhi 0x%x\n", 299 csr, reset, rlo, rhi); 300 301 if (!power) 302 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_OFF); 303 if (pci_get_capability(sc->sc_pc, sc->sc_ptag, PCI_CAP_PWRMGMT, 304 &pmreg, NULL)) { 305 DPRINTF(("%s: power status 0x%x", device_xname(dwsc->sc_dev), 306 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 307 pci_conf_write(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR, 308 power ? PCI_PMCSR_STATE_D0 : PCI_PMCSR_STATE_D3); 309 DELAY(10000); /* 10 milliseconds */ 310 DPRINTF((" -> 0x%x\n", 311 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 312 } 313 if (power) { 314 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_ON); 315 } 316 return true; 317 } 318
Indexes created Wed Oct 01 07:09:59 GMT 2025