1 /* $NetBSD: if_pcn.c,v 1.80 2024/11/10 11:45:25 mlelstv Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.80 2024/11/10 11:45:25 mlelstv Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/ioctl.h> 77 #include <sys/errno.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 81 #include <sys/rndsource.h> 82 83 #include <net/if.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #include <net/bpf.h> 89 90 #include <sys/bus.h> 91 #include <sys/intr.h> 92 #include <machine/endian.h> 93 94 #include <dev/mii/mii.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/ic/am79900reg.h> 98 #include <dev/ic/lancereg.h> 99 100 #include <dev/pci/pcireg.h> 101 #include <dev/pci/pcivar.h> 102 #include <dev/pci/pcidevs.h> 103 104 #include <dev/pci/if_pcnreg.h> 105 106 /* 107 * Transmit descriptor list size. This is arbitrary, but allocate 108 * enough descriptors for 128 pending transmissions, and 4 segments 109 * per packet. This MUST work out to a power of 2. 110 * 111 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 112 * 113 * So we play a little trick here. We give each packet up to 16 114 * DMA segments, but only allocate the max of 512 descriptors. The 115 * transmit logic can deal with this, we just are hoping to sneak by. 116 */ 117 #define PCN_NTXSEGS 16 118 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 119 120 #define PCN_TXQUEUELEN 128 121 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 122 #define PCN_NTXDESC 512 123 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 124 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 125 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 126 127 /* Tx interrupt every N + 1 packets. */ 128 #define PCN_TXINTR_MASK 7 129 130 /* 131 * Receive descriptor list size. We have one Rx buffer per incoming 132 * packet, so this logic is a little simpler. 133 */ 134 #define PCN_NRXDESC 128 135 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 136 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 137 138 /* 139 * Control structures are DMA'd to the PCnet chip. We allocate them in 140 * a single clump that maps to a single DMA segment to make several things 141 * easier. 142 */ 143 struct pcn_control_data { 144 /* The transmit descriptors. */ 145 struct letmd pcd_txdescs[PCN_NTXDESC]; 146 147 /* The receive descriptors. */ 148 struct lermd pcd_rxdescs[PCN_NRXDESC]; 149 150 /* The init block. */ 151 struct leinit pcd_initblock; 152 }; 153 154 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 155 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 156 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 157 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 158 159 /* 160 * Software state for transmit jobs. 161 */ 162 struct pcn_txsoft { 163 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 164 bus_dmamap_t txs_dmamap; /* our DMA map */ 165 int txs_firstdesc; /* first descriptor in packet */ 166 int txs_lastdesc; /* last descriptor in packet */ 167 }; 168 169 /* 170 * Software state for receive jobs. 171 */ 172 struct pcn_rxsoft { 173 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t rxs_dmamap; /* our DMA map */ 175 }; 176 177 /* 178 * Description of Rx FIFO watermarks for various revisions. 179 */ 180 static const char * const pcn_79c970_rcvfw[] = { 181 "16 bytes", 182 "64 bytes", 183 "128 bytes", 184 NULL, 185 }; 186 187 static const char * const pcn_79c971_rcvfw[] = { 188 "16 bytes", 189 "64 bytes", 190 "112 bytes", 191 NULL, 192 }; 193 194 /* 195 * Description of Tx start points for various revisions. 196 */ 197 static const char * const pcn_79c970_xmtsp[] = { 198 "8 bytes", 199 "64 bytes", 200 "128 bytes", 201 "248 bytes", 202 }; 203 204 static const char * const pcn_79c971_xmtsp[] = { 205 "20 bytes", 206 "64 bytes", 207 "128 bytes", 208 "248 bytes", 209 }; 210 211 static const char * const pcn_79c971_xmtsp_sram[] = { 212 "44 bytes", 213 "64 bytes", 214 "128 bytes", 215 "store-and-forward", 216 }; 217 218 /* 219 * Description of Tx FIFO watermarks for various revisions. 220 */ 221 static const char * const pcn_79c970_xmtfw[] = { 222 "16 bytes", 223 "64 bytes", 224 "128 bytes", 225 NULL, 226 }; 227 228 static const char * const pcn_79c971_xmtfw[] = { 229 "16 bytes", 230 "64 bytes", 231 "108 bytes", 232 NULL, 233 }; 234 235 /* 236 * Software state per device. 237 */ 238 struct pcn_softc { 239 device_t sc_dev; /* generic device information */ 240 bus_space_tag_t sc_st; /* bus space tag */ 241 bus_space_handle_t sc_sh; /* bus space handle */ 242 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 243 struct ethercom sc_ethercom; /* Ethernet common data */ 244 245 /* Points to our media routines, etc. */ 246 const struct pcn_variant *sc_variant; 247 248 void *sc_ih; /* interrupt cookie */ 249 250 struct mii_data sc_mii; /* MII/media information */ 251 252 callout_t sc_tick_ch; /* tick callout */ 253 254 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 255 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 256 257 /* Software state for transmit and receive descriptors. */ 258 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 259 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 260 261 /* Control data structures */ 262 struct pcn_control_data *sc_control_data; 263 #define sc_txdescs sc_control_data->pcd_txdescs 264 #define sc_rxdescs sc_control_data->pcd_rxdescs 265 #define sc_initblock sc_control_data->pcd_initblock 266 267 #ifdef PCN_EVENT_COUNTERS 268 /* Event counters. */ 269 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 270 struct evcnt sc_ev_txintr; /* Tx interrupts */ 271 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 272 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 273 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 274 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 275 276 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 277 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 278 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 279 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 280 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 281 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 282 struct evcnt sc_ev_txcopy; /* Tx copies required */ 283 #endif /* PCN_EVENT_COUNTERS */ 284 285 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 286 int sc_rcvfw; 287 288 const char * const *sc_xmtsp_desc; /* Tx start point info */ 289 int sc_xmtsp; 290 291 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 292 int sc_xmtfw; 293 294 int sc_flags; /* misc. flags; see below */ 295 int sc_swstyle; /* the software style in use */ 296 297 int sc_txfree; /* number of free Tx descriptors */ 298 int sc_txnext; /* next ready Tx descriptor */ 299 300 int sc_txsfree; /* number of free Tx jobs */ 301 int sc_txsnext; /* next free Tx job */ 302 int sc_txsdirty; /* dirty Tx jobs */ 303 304 int sc_rxptr; /* next ready Rx descriptor/job */ 305 306 uint32_t sc_csr5; /* prototype CSR5 register */ 307 uint32_t sc_mode; /* prototype MODE register */ 308 309 krndsource_t rnd_source; /* random source */ 310 }; 311 312 /* sc_flags */ 313 #define PCN_F_HAS_MII 0x0001 /* has MII */ 314 315 #ifdef PCN_EVENT_COUNTERS 316 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 317 #else 318 #define PCN_EVCNT_INCR(ev) /* nothing */ 319 #endif 320 321 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 322 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 323 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 324 325 #define PCN_CDTXSYNC(sc, x, n, ops) \ 326 do { \ 327 int __x, __n; \ 328 \ 329 __x = (x); \ 330 __n = (n); \ 331 \ 332 /* If it will wrap around, sync to the end of the ring. */ \ 333 if ((__x + __n) > PCN_NTXDESC) { \ 334 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 335 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 336 (PCN_NTXDESC - __x), (ops)); \ 337 __n -= (PCN_NTXDESC - __x); \ 338 __x = 0; \ 339 } \ 340 \ 341 /* Now sync whatever is left. */ \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 344 } while (/*CONSTCOND*/0) 345 346 #define PCN_CDRXSYNC(sc, x, ops) \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 349 350 #define PCN_CDINITSYNC(sc, ops) \ 351 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 352 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 353 354 #define PCN_INIT_RXDESC(sc, x) \ 355 do { \ 356 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 357 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 358 struct mbuf *__m = __rxs->rxs_mbuf; \ 359 \ 360 /* \ 361 * Note: We scoot the packet forward 2 bytes in the buffer \ 362 * so that the payload after the Ethernet header is aligned \ 363 * to a 4-byte boundary. \ 364 */ \ 365 __m->m_data = __m->m_ext.ext_buf + 2; \ 366 \ 367 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 368 __rmd->rmd2 = \ 369 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 370 __rmd->rmd0 = 0; \ 371 } else { \ 372 __rmd->rmd2 = 0; \ 373 __rmd->rmd0 = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 375 } \ 376 __rmd->rmd1 = htole32(LE_R1_OWN | LE_R1_ONES | \ 377 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 378 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);\ 379 } while(/*CONSTCOND*/0) 380 381 static void pcn_start(struct ifnet *); 382 static void pcn_watchdog(struct ifnet *); 383 static int pcn_ioctl(struct ifnet *, u_long, void *); 384 static int pcn_init(struct ifnet *); 385 static void pcn_stop(struct ifnet *, int); 386 387 static bool pcn_shutdown(device_t, int); 388 389 static void pcn_reset(struct pcn_softc *); 390 static void pcn_rxdrain(struct pcn_softc *); 391 static int pcn_add_rxbuf(struct pcn_softc *, int); 392 static void pcn_tick(void *); 393 394 static void pcn_spnd(struct pcn_softc *); 395 396 static void pcn_set_filter(struct pcn_softc *); 397 398 static int pcn_intr(void *); 399 static void pcn_txintr(struct pcn_softc *); 400 static int pcn_rxintr(struct pcn_softc *); 401 402 static int pcn_mii_readreg(device_t, int, int, uint16_t *); 403 static int pcn_mii_writereg(device_t, int, int, uint16_t); 404 static void pcn_mii_statchg(struct ifnet *); 405 406 static void pcn_79c970_mediainit(struct pcn_softc *); 407 static int pcn_79c970_mediachange(struct ifnet *); 408 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 409 410 static void pcn_79c971_mediainit(struct pcn_softc *); 411 412 /* 413 * Description of a PCnet-PCI variant. Used to select media access 414 * method, mostly, and to print a nice description of the chip. 415 */ 416 static const struct pcn_variant { 417 const char *pcv_desc; 418 void (*pcv_mediainit)(struct pcn_softc *); 419 uint16_t pcv_chipid; 420 } pcn_variants[] = { 421 { "Am79c970 PCnet-PCI", 422 pcn_79c970_mediainit, 423 PARTID_Am79c970 }, 424 425 { "Am79c970A PCnet-PCI II", 426 pcn_79c970_mediainit, 427 PARTID_Am79c970A }, 428 429 { "Am79c971 PCnet-FAST", 430 pcn_79c971_mediainit, 431 PARTID_Am79c971 }, 432 433 { "Am79c972 PCnet-FAST+", 434 pcn_79c971_mediainit, 435 PARTID_Am79c972 }, 436 437 { "Am79c973 PCnet-FAST III", 438 pcn_79c971_mediainit, 439 PARTID_Am79c973 }, 440 441 { "Am79c975 PCnet-FAST III", 442 pcn_79c971_mediainit, 443 PARTID_Am79c975 }, 444 445 { "Unknown PCnet-PCI variant", 446 pcn_79c971_mediainit, 447 0 }, 448 }; 449 450 int pcn_copy_small = 0; 451 452 static int pcn_match(device_t, cfdata_t, void *); 453 static void pcn_attach(device_t, device_t, void *); 454 455 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 456 pcn_match, pcn_attach, NULL, NULL); 457 458 /* 459 * Routines to read and write the PCnet-PCI CSR/BCR space. 460 */ 461 462 static inline uint32_t 463 pcn_csr_read(struct pcn_softc *sc, int reg) 464 { 465 466 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 467 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP); 468 } 469 470 static inline void 471 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 472 { 473 474 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 475 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 476 } 477 478 static inline uint32_t 479 pcn_bcr_read(struct pcn_softc *sc, int reg) 480 { 481 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 483 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP); 484 } 485 486 static inline void 487 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 488 { 489 490 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 491 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 492 } 493 494 static bool 495 pcn_is_vmware(const char *enaddr) 496 { 497 498 /* 499 * VMware uses the OUI 00:0c:29 for auto-generated MAC 500 * addresses. 501 */ 502 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 503 return TRUE; 504 505 /* 506 * VMware uses the OUI 00:50:56 for manually-set MAC 507 * addresses (and some auto-generated ones). 508 */ 509 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 510 return TRUE; 511 512 return FALSE; 513 } 514 515 static const struct pcn_variant * 516 pcn_lookup_variant(uint16_t chipid) 517 { 518 const struct pcn_variant *pcv; 519 520 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 521 if (chipid == pcv->pcv_chipid) 522 return pcv; 523 } 524 525 /* 526 * This covers unknown chips, which we simply treat like 527 * a generic PCnet-FAST. 528 */ 529 return pcv; 530 } 531 532 static int 533 pcn_match(device_t parent, cfdata_t cf, void *aux) 534 { 535 struct pci_attach_args *pa = aux; 536 537 /* 538 * IBM Makes a PCI variant of this card which shows up as a 539 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 540 * this card is truly a pcn card, so we have a special case match for 541 * it 542 */ 543 544 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 545 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 546 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 547 return 1; 548 549 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 550 return 0; 551 552 switch (PCI_PRODUCT(pa->pa_id)) { 553 case PCI_PRODUCT_AMD_PCNET_PCI: 554 /* Beat if_le_pci.c */ 555 return 10; 556 } 557 558 return 0; 559 } 560 561 static void 562 pcn_attach(device_t parent, device_t self, void *aux) 563 { 564 struct pcn_softc *sc = device_private(self); 565 struct pci_attach_args *pa = aux; 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 pci_chipset_tag_t pc = pa->pa_pc; 568 pci_intr_handle_t ih; 569 const char *intrstr = NULL; 570 bus_space_tag_t iot, memt; 571 bus_space_handle_t ioh, memh; 572 bus_dma_segment_t seg; 573 int ioh_valid, memh_valid; 574 int ntxsegs, i, rseg, error; 575 uint32_t chipid, reg; 576 uint8_t enaddr[ETHER_ADDR_LEN]; 577 prop_object_t obj; 578 bool is_vmware; 579 char intrbuf[PCI_INTRSTR_LEN]; 580 581 sc->sc_dev = self; 582 callout_init(&sc->sc_tick_ch, 0); 583 callout_setfunc(&sc->sc_tick_ch, pcn_tick, sc); 584 585 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 586 587 /* 588 * Map the device. 589 */ 590 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 591 &iot, &ioh, NULL, NULL) == 0); 592 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 593 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 594 &memt, &memh, NULL, NULL) == 0); 595 596 if (memh_valid) { 597 sc->sc_st = memt; 598 sc->sc_sh = memh; 599 } else if (ioh_valid) { 600 sc->sc_st = iot; 601 sc->sc_sh = ioh; 602 } else { 603 aprint_error_dev(self, "unable to map device registers\n"); 604 return; 605 } 606 607 sc->sc_dmat = pa->pa_dmat; 608 609 /* Make sure bus mastering is enabled. */ 610 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 611 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 612 PCI_COMMAND_MASTER_ENABLE); 613 614 /* power up chip */ 615 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 616 NULL)) && error != EOPNOTSUPP) { 617 aprint_error_dev(self, "cannot activate %d\n", error); 618 return; 619 } 620 621 /* 622 * Reset the chip to a known state. This also puts the 623 * chip into 32-bit mode. 624 */ 625 pcn_reset(sc); 626 627 /* 628 * On some systems with the chip is an on-board device, the 629 * EEPROM is not used. Handle this by reading the MAC address 630 * from the CSRs (assuming that boot firmware has written 631 * it there). 632 */ 633 obj = prop_dictionary_get(device_properties(sc->sc_dev), 634 "am79c970-no-eeprom"); 635 if (prop_bool_true(obj)) { 636 for (i = 0; i < 3; i++) { 637 uint32_t val; 638 val = pcn_csr_read(sc, LE_CSR12 + i); 639 enaddr[2 * i] = val & 0xff; 640 enaddr[2 * i + 1] = (val >> 8) & 0xff; 641 } 642 } else { 643 for (i = 0; i < ETHER_ADDR_LEN; i++) { 644 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 645 PCN32_APROM + i); 646 } 647 } 648 649 /* Check to see if this is a VMware emulated network interface. */ 650 is_vmware = pcn_is_vmware(enaddr); 651 652 /* 653 * Now that the device is mapped, attempt to figure out what 654 * kind of chip we have. Note that IDL has all 32 bits of 655 * the chip ID when we're in 32-bit mode. 656 */ 657 chipid = pcn_csr_read(sc, LE_CSR88); 658 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 659 660 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 661 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 662 ether_sprintf(enaddr)); 663 664 /* 665 * VMware has a bug in its network interface emulation; we must 666 * limit the number of Tx segments. 667 */ 668 if (is_vmware) { 669 ntxsegs = PCN_NTXSEGS_VMWARE; 670 prop_dictionary_set_bool(device_properties(sc->sc_dev), 671 "am79c970-vmware-tx-bug", TRUE); 672 aprint_verbose_dev(self, 673 "VMware Tx segment count bug detected\n"); 674 } else { 675 ntxsegs = PCN_NTXSEGS; 676 } 677 678 /* 679 * Map and establish our interrupt. 680 */ 681 if (pci_intr_map(pa, &ih)) { 682 aprint_error_dev(self, "unable to map interrupt\n"); 683 return; 684 } 685 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 686 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, pcn_intr, sc, 687 device_xname(self)); 688 if (sc->sc_ih == NULL) { 689 aprint_error_dev(self, "unable to establish interrupt"); 690 if (intrstr != NULL) 691 aprint_error(" at %s", intrstr); 692 aprint_error("\n"); 693 return; 694 } 695 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 696 697 /* 698 * Allocate the control data structures, and create and load the 699 * DMA map for it. 700 */ 701 if ((error = bus_dmamem_alloc(sc->sc_dmat, 702 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 703 0)) != 0) { 704 aprint_error_dev(self, "unable to allocate control data, " 705 "error = %d\n", error); 706 goto fail_0; 707 } 708 709 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 710 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 711 BUS_DMA_COHERENT)) != 0) { 712 aprint_error_dev(self, "unable to map control data, " 713 "error = %d\n", error); 714 goto fail_1; 715 } 716 717 if ((error = bus_dmamap_create(sc->sc_dmat, 718 sizeof(struct pcn_control_data), 1, 719 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 720 aprint_error_dev(self, "unable to create control data DMA map, " 721 "error = %d\n", error); 722 goto fail_2; 723 } 724 725 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 726 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 727 0)) != 0) { 728 aprint_error_dev(self, 729 "unable to load control data DMA map, error = %d\n", error); 730 goto fail_3; 731 } 732 733 /* Create the transmit buffer DMA maps. */ 734 for (i = 0; i < PCN_TXQUEUELEN; i++) { 735 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 736 ntxsegs, MCLBYTES, 0, 0, 737 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 738 aprint_error_dev(self, 739 "unable to create tx DMA map %d, error = %d\n", 740 i, error); 741 goto fail_4; 742 } 743 } 744 745 /* Create the receive buffer DMA maps. */ 746 for (i = 0; i < PCN_NRXDESC; i++) { 747 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 748 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 749 aprint_error_dev(self, 750 "unable to create rx DMA map %d, error = %d\n", 751 i, error); 752 goto fail_5; 753 } 754 sc->sc_rxsoft[i].rxs_mbuf = NULL; 755 } 756 757 /* Initialize our media structures. */ 758 (*sc->sc_variant->pcv_mediainit)(sc); 759 760 /* 761 * Initialize FIFO watermark info. 762 */ 763 switch (sc->sc_variant->pcv_chipid) { 764 case PARTID_Am79c970: 765 case PARTID_Am79c970A: 766 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 767 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 768 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 769 break; 770 771 default: 772 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 773 /* 774 * Read BCR25 to determine how much SRAM is 775 * on the board. If > 0, then we the chip 776 * uses different Start Point thresholds. 777 * 778 * Note BCR25 and BCR26 are loaded from the 779 * EEPROM on RST, and unaffected by S_RESET, 780 * so we don't really have to worry about 781 * them except for this. 782 */ 783 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 784 if (reg != 0) 785 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 786 else 787 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 788 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 789 break; 790 } 791 792 /* 793 * Set up defaults -- see the tables above for what these 794 * values mean. 795 * 796 * XXX How should we tune RCVFW and XMTFW? 797 */ 798 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 799 sc->sc_xmtsp = 1; 800 sc->sc_xmtfw = 0; 801 802 ifp = &sc->sc_ethercom.ec_if; 803 strcpy(ifp->if_xname, device_xname(self)); 804 ifp->if_softc = sc; 805 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 806 ifp->if_ioctl = pcn_ioctl; 807 ifp->if_start = pcn_start; 808 ifp->if_watchdog = pcn_watchdog; 809 ifp->if_init = pcn_init; 810 ifp->if_stop = pcn_stop; 811 IFQ_SET_READY(&ifp->if_snd); 812 813 /* Attach the interface. */ 814 if_attach(ifp); 815 if_deferred_start_init(ifp, NULL); 816 ether_ifattach(ifp, enaddr); 817 rnd_attach_source(&sc->rnd_source, device_xname(self), 818 RND_TYPE_NET, RND_FLAG_DEFAULT); 819 820 #ifdef PCN_EVENT_COUNTERS 821 /* Attach event counters. */ 822 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 823 NULL, device_xname(self), "txdstall"); 824 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 825 NULL, device_xname(self), "txintr"); 826 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 827 NULL, device_xname(self), "rxintr"); 828 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 829 NULL, device_xname(self), "babl"); 830 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 831 NULL, device_xname(self), "miss"); 832 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 833 NULL, device_xname(self), "merr"); 834 835 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 836 NULL, device_xname(self), "txseg1"); 837 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 838 NULL, device_xname(self), "txseg2"); 839 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 840 NULL, device_xname(self), "txseg3"); 841 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 842 NULL, device_xname(self), "txseg4"); 843 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 844 NULL, device_xname(self), "txseg5"); 845 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 846 NULL, device_xname(self), "txsegmore"); 847 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 848 NULL, device_xname(self), "txcopy"); 849 #endif /* PCN_EVENT_COUNTERS */ 850 851 /* 852 * Establish power handler with shutdown hook, to make sure 853 * the interface is shutdown during reboot. 854 */ 855 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 856 pmf_class_network_register(self, ifp); 857 else 858 aprint_error_dev(self, "couldn't establish power handler\n"); 859 860 return; 861 862 /* 863 * Free any resources we've allocated during the failed attach 864 * attempt. Do this in reverse order and fall through. 865 */ 866 fail_5: 867 for (i = 0; i < PCN_NRXDESC; i++) { 868 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 869 bus_dmamap_destroy(sc->sc_dmat, 870 sc->sc_rxsoft[i].rxs_dmamap); 871 } 872 fail_4: 873 for (i = 0; i < PCN_TXQUEUELEN; i++) { 874 if (sc->sc_txsoft[i].txs_dmamap != NULL) 875 bus_dmamap_destroy(sc->sc_dmat, 876 sc->sc_txsoft[i].txs_dmamap); 877 } 878 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 879 fail_3: 880 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 881 fail_2: 882 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 883 sizeof(struct pcn_control_data)); 884 fail_1: 885 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 886 fail_0: 887 return; 888 } 889 890 /* 891 * pcn_shutdown: 892 * 893 * Make sure the interface is stopped at reboot time. 894 */ 895 static bool 896 pcn_shutdown(device_t self, int howto) 897 { 898 struct pcn_softc *sc = device_private(self); 899 900 pcn_stop(&sc->sc_ethercom.ec_if, 1); 901 /* explicitly reset the chip for some onboard one with lazy firmware */ 902 pcn_reset(sc); 903 904 return true; 905 } 906 907 /* 908 * pcn_start: [ifnet interface function] 909 * 910 * Start packet transmission on the interface. 911 */ 912 static void 913 pcn_start(struct ifnet *ifp) 914 { 915 struct pcn_softc *sc = ifp->if_softc; 916 struct mbuf *m0, *m; 917 struct pcn_txsoft *txs; 918 bus_dmamap_t dmamap; 919 int error, nexttx, lasttx = -1, ofree, seg; 920 921 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 922 return; 923 924 /* 925 * Remember the previous number of free descriptors and 926 * the first descriptor we'll use. 927 */ 928 ofree = sc->sc_txfree; 929 930 /* 931 * Loop through the send queue, setting up transmit descriptors 932 * until we drain the queue, or use up all available transmit 933 * descriptors. 934 */ 935 while (sc->sc_txsfree != 0) { 936 /* Grab a packet off the queue. */ 937 IFQ_POLL(&ifp->if_snd, m0); 938 if (m0 == NULL) 939 break; 940 m = NULL; 941 942 txs = &sc->sc_txsoft[sc->sc_txsnext]; 943 dmamap = txs->txs_dmamap; 944 945 /* 946 * Load the DMA map. If this fails, the packet either 947 * didn't fit in the allotted number of segments, or we 948 * were short on resources. In this case, we'll copy 949 * and try again. 950 */ 951 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 952 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 953 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 954 MGETHDR(m, M_DONTWAIT, MT_DATA); 955 if (m == NULL) { 956 printf("%s: unable to allocate Tx mbuf\n", 957 device_xname(sc->sc_dev)); 958 break; 959 } 960 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 961 if (m0->m_pkthdr.len > MHLEN) { 962 MCLGET(m, M_DONTWAIT); 963 if ((m->m_flags & M_EXT) == 0) { 964 printf("%s: unable to allocate Tx " 965 "cluster\n", 966 device_xname(sc->sc_dev)); 967 m_freem(m); 968 break; 969 } 970 } 971 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 972 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 973 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 974 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 975 if (error) { 976 printf("%s: unable to load Tx buffer, " 977 "error = %d\n", device_xname(sc->sc_dev), 978 error); 979 m_freem(m); 980 break; 981 } 982 } 983 984 /* 985 * Ensure we have enough descriptors free to describe 986 * the packet. Note, we always reserve one descriptor 987 * at the end of the ring as a termination point, to 988 * prevent wrap-around. 989 */ 990 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 991 /* 992 * Not enough free descriptors to transmit this 993 * packet. 994 */ 995 bus_dmamap_unload(sc->sc_dmat, dmamap); 996 m_freem(m); 997 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 998 break; 999 } 1000 1001 IFQ_DEQUEUE(&ifp->if_snd, m0); 1002 if (m != NULL) { 1003 m_freem(m0); 1004 m0 = m; 1005 } 1006 1007 /* 1008 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1009 */ 1010 1011 /* Sync the DMA map. */ 1012 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1013 BUS_DMASYNC_PREWRITE); 1014 1015 #ifdef PCN_EVENT_COUNTERS 1016 switch (dmamap->dm_nsegs) { 1017 case 1: 1018 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1019 break; 1020 case 2: 1021 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1022 break; 1023 case 3: 1024 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1025 break; 1026 case 4: 1027 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1028 break; 1029 case 5: 1030 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1031 break; 1032 default: 1033 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1034 break; 1035 } 1036 #endif /* PCN_EVENT_COUNTERS */ 1037 1038 /* 1039 * Initialize the transmit descriptors. 1040 */ 1041 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1042 for (nexttx = sc->sc_txnext, seg = 0; 1043 seg < dmamap->dm_nsegs; 1044 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1045 /* 1046 * If this is the first descriptor we're 1047 * enqueueing, don't set the OWN bit just 1048 * yet. That could cause a race condition. 1049 * We'll do it below. 1050 */ 1051 sc->sc_txdescs[nexttx].tmd0 = 0; 1052 sc->sc_txdescs[nexttx].tmd2 = 1053 htole32(dmamap->dm_segs[seg].ds_addr); 1054 sc->sc_txdescs[nexttx].tmd1 = 1055 htole32(LE_T1_ONES | 1056 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1057 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1058 LE_T1_BCNT_MASK)); 1059 lasttx = nexttx; 1060 } 1061 } else { 1062 for (nexttx = sc->sc_txnext, seg = 0; 1063 seg < dmamap->dm_nsegs; 1064 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1065 /* 1066 * If this is the first descriptor we're 1067 * enqueueing, don't set the OWN bit just 1068 * yet. That could cause a race condition. 1069 * We'll do it below. 1070 */ 1071 sc->sc_txdescs[nexttx].tmd0 = 1072 htole32(dmamap->dm_segs[seg].ds_addr); 1073 sc->sc_txdescs[nexttx].tmd2 = 0; 1074 sc->sc_txdescs[nexttx].tmd1 = 1075 htole32(LE_T1_ONES | 1076 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1077 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1078 LE_T1_BCNT_MASK)); 1079 lasttx = nexttx; 1080 } 1081 } 1082 1083 KASSERT(lasttx != -1); 1084 /* Interrupt on the packet, if appropriate. */ 1085 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1086 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1087 1088 /* Set `start of packet' and `end of packet' appropriately. */ 1089 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1090 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1091 htole32(LE_T1_OWN | LE_T1_STP); 1092 1093 /* Sync the descriptors we're using. */ 1094 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1096 1097 /* Kick the transmitter. */ 1098 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD); 1099 1100 /* 1101 * Store a pointer to the packet so we can free it later, 1102 * and remember what txdirty will be once the packet is 1103 * done. 1104 */ 1105 txs->txs_mbuf = m0; 1106 txs->txs_firstdesc = sc->sc_txnext; 1107 txs->txs_lastdesc = lasttx; 1108 1109 /* Advance the tx pointer. */ 1110 sc->sc_txfree -= dmamap->dm_nsegs; 1111 sc->sc_txnext = nexttx; 1112 1113 sc->sc_txsfree--; 1114 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1115 1116 /* Pass the packet to any BPF listeners. */ 1117 bpf_mtap(ifp, m0, BPF_D_OUT); 1118 } 1119 1120 if (sc->sc_txfree != ofree) { 1121 /* Set a watchdog timer in case the chip flakes out. */ 1122 ifp->if_timer = 5; 1123 } 1124 } 1125 1126 /* 1127 * pcn_watchdog: [ifnet interface function] 1128 * 1129 * Watchdog timer handler. 1130 */ 1131 static void 1132 pcn_watchdog(struct ifnet *ifp) 1133 { 1134 struct pcn_softc *sc = ifp->if_softc; 1135 1136 /* 1137 * Since we're not interrupting every packet, sweep 1138 * up before we report an error. 1139 */ 1140 pcn_txintr(sc); 1141 1142 if (sc->sc_txfree != PCN_NTXDESC) { 1143 printf("%s: device timeout (txfree %d txsfree %d)\n", 1144 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1145 if_statinc(ifp, if_oerrors); 1146 1147 /* Reset the interface. */ 1148 (void) pcn_init(ifp); 1149 } 1150 1151 /* Try to get more packets going. */ 1152 pcn_start(ifp); 1153 } 1154 1155 /* 1156 * pcn_ioctl: [ifnet interface function] 1157 * 1158 * Handle control requests from the operator. 1159 */ 1160 static int 1161 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1162 { 1163 int s, error; 1164 1165 s = splnet(); 1166 1167 switch (cmd) { 1168 default: 1169 error = ether_ioctl(ifp, cmd, data); 1170 if (error == ENETRESET) { 1171 /* 1172 * Multicast list has changed; set the hardware filter 1173 * accordingly. 1174 */ 1175 if (ifp->if_flags & IFF_RUNNING) 1176 error = pcn_init(ifp); 1177 else 1178 error = 0; 1179 } 1180 break; 1181 } 1182 1183 /* Try to get more packets going. */ 1184 pcn_start(ifp); 1185 1186 splx(s); 1187 return error; 1188 } 1189 1190 /* 1191 * pcn_intr: 1192 * 1193 * Interrupt service routine. 1194 */ 1195 static int 1196 pcn_intr(void *arg) 1197 { 1198 struct pcn_softc *sc = arg; 1199 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1200 uint32_t csr0; 1201 int wantinit, handled = 0; 1202 1203 for (wantinit = 0; wantinit == 0;) { 1204 csr0 = pcn_csr_read(sc, LE_CSR0); 1205 if ((csr0 & LE_C0_INTR) == 0) 1206 break; 1207 1208 rnd_add_uint32(&sc->rnd_source, csr0); 1209 1210 /* ACK the bits and re-enable interrupts. */ 1211 pcn_csr_write(sc, LE_CSR0, csr0 & 1212 (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR | 1213 LE_C0_RINT | LE_C0_TINT | LE_C0_IDON)); 1214 1215 handled = 1; 1216 1217 if (csr0 & LE_C0_RINT) { 1218 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1219 wantinit = pcn_rxintr(sc); 1220 } 1221 1222 if (csr0 & LE_C0_TINT) { 1223 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1224 pcn_txintr(sc); 1225 } 1226 1227 if (csr0 & LE_C0_ERR) { 1228 if (csr0 & LE_C0_BABL) { 1229 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1230 if_statinc(ifp, if_oerrors); 1231 } 1232 if (csr0 & LE_C0_MISS) { 1233 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1234 if_statinc(ifp, if_ierrors); 1235 } 1236 if (csr0 & LE_C0_MERR) { 1237 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1238 printf("%s: memory error\n", 1239 device_xname(sc->sc_dev)); 1240 wantinit = 1; 1241 break; 1242 } 1243 } 1244 1245 if ((csr0 & LE_C0_RXON) == 0) { 1246 printf("%s: receiver disabled\n", 1247 device_xname(sc->sc_dev)); 1248 if_statinc(ifp, if_ierrors); 1249 wantinit = 1; 1250 } 1251 1252 if ((csr0 & LE_C0_TXON) == 0) { 1253 printf("%s: transmitter disabled\n", 1254 device_xname(sc->sc_dev)); 1255 if_statinc(ifp, if_oerrors); 1256 wantinit = 1; 1257 } 1258 } 1259 1260 if (handled) { 1261 if (wantinit) 1262 pcn_init(ifp); 1263 1264 /* Try to get more packets going. */ 1265 if_schedule_deferred_start(ifp); 1266 } 1267 1268 return handled; 1269 } 1270 1271 /* 1272 * pcn_spnd: 1273 * 1274 * Suspend the chip. 1275 */ 1276 static void 1277 pcn_spnd(struct pcn_softc *sc) 1278 { 1279 int i; 1280 1281 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1282 1283 for (i = 0; i < 10000; i++) { 1284 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1285 return; 1286 delay(5); 1287 } 1288 1289 printf("%s: WARNING: chip failed to enter suspended state\n", 1290 device_xname(sc->sc_dev)); 1291 } 1292 1293 /* 1294 * pcn_txintr: 1295 * 1296 * Helper; handle transmit interrupts. 1297 */ 1298 static void 1299 pcn_txintr(struct pcn_softc *sc) 1300 { 1301 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1302 struct pcn_txsoft *txs; 1303 uint32_t tmd1, tmd2, tmd; 1304 int i, j; 1305 1306 /* 1307 * Go through our Tx list and free mbufs for those 1308 * frames which have been transmitted. 1309 */ 1310 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1311 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1312 txs = &sc->sc_txsoft[i]; 1313 1314 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1315 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1316 1317 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1318 if (tmd1 & LE_T1_OWN) 1319 break; 1320 1321 /* 1322 * Slightly annoying -- we have to loop through the 1323 * descriptors we've used looking for ERR, since it 1324 * can appear on any descriptor in the chain. 1325 */ 1326 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1327 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1328 if (tmd & LE_T1_ERR) { 1329 if_statinc(ifp, if_oerrors); 1330 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1331 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1332 else 1333 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1334 if (tmd2 & LE_T2_UFLO) { 1335 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1336 sc->sc_xmtsp++; 1337 printf("%s: transmit " 1338 "underrun; new threshold: " 1339 "%s\n", 1340 device_xname(sc->sc_dev), 1341 sc->sc_xmtsp_desc[ 1342 sc->sc_xmtsp]); 1343 pcn_spnd(sc); 1344 pcn_csr_write(sc, LE_CSR80, 1345 LE_C80_RCVFW(sc->sc_rcvfw) | 1346 LE_C80_XMTSP(sc->sc_xmtsp) | 1347 LE_C80_XMTFW(sc->sc_xmtfw)); 1348 pcn_csr_write(sc, LE_CSR5, 1349 sc->sc_csr5); 1350 } else { 1351 printf("%s: transmit " 1352 "underrun\n", 1353 device_xname(sc->sc_dev)); 1354 } 1355 } else if (tmd2 & LE_T2_BUFF) { 1356 printf("%s: transmit buffer error\n", 1357 device_xname(sc->sc_dev)); 1358 } 1359 if (tmd2 & LE_T2_LCOL) 1360 if_statinc(ifp, if_collisions); 1361 if (tmd2 & LE_T2_RTRY) 1362 if_statadd(ifp, if_collisions, 16); 1363 goto next_packet; 1364 } 1365 if (j == txs->txs_lastdesc) 1366 break; 1367 } 1368 if (tmd1 & LE_T1_ONE) 1369 if_statinc(ifp, if_collisions); 1370 else if (tmd & LE_T1_MORE) { 1371 /* Real number is unknown. */ 1372 if_statadd(ifp, if_collisions, 2); 1373 } 1374 if_statinc(ifp, if_opackets); 1375 next_packet: 1376 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1377 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1378 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1379 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1380 m_freem(txs->txs_mbuf); 1381 txs->txs_mbuf = NULL; 1382 } 1383 1384 /* Update the dirty transmit buffer pointer. */ 1385 sc->sc_txsdirty = i; 1386 1387 /* 1388 * If there are no more pending transmissions, cancel the watchdog 1389 * timer. 1390 */ 1391 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1392 ifp->if_timer = 0; 1393 } 1394 1395 /* 1396 * pcn_rxintr: 1397 * 1398 * Helper; handle receive interrupts. 1399 */ 1400 static int 1401 pcn_rxintr(struct pcn_softc *sc) 1402 { 1403 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1404 struct pcn_rxsoft *rxs; 1405 struct mbuf *m; 1406 uint32_t rmd1; 1407 int i, len; 1408 1409 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1410 rxs = &sc->sc_rxsoft[i]; 1411 1412 PCN_CDRXSYNC(sc, i, 1413 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1414 1415 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1416 1417 if (rmd1 & LE_R1_OWN) 1418 break; 1419 1420 /* 1421 * Check for errors and make sure the packet fit into 1422 * a single buffer. We have structured this block of 1423 * code the way it is in order to compress it into 1424 * one test in the common case (no error). 1425 */ 1426 if (__predict_false((rmd1 & (LE_R1_STP | LE_R1_ENP |LE_R1_ERR)) 1427 != (LE_R1_STP | LE_R1_ENP))) { 1428 /* Make sure the packet is in a single buffer. */ 1429 if ((rmd1 & (LE_R1_STP | LE_R1_ENP)) != 1430 (LE_R1_STP | LE_R1_ENP)) { 1431 printf("%s: packet spilled into next buffer\n", 1432 device_xname(sc->sc_dev)); 1433 return 1; /* pcn_intr() will re-init */ 1434 } 1435 1436 /* 1437 * If the packet had an error, simple recycle the 1438 * buffer. 1439 */ 1440 if (rmd1 & LE_R1_ERR) { 1441 if_statinc(ifp, if_ierrors); 1442 /* 1443 * If we got an overflow error, chances 1444 * are there will be a CRC error. In 1445 * this case, just print the overflow 1446 * error, and skip the others. 1447 */ 1448 if (rmd1 & LE_R1_OFLO) 1449 printf("%s: overflow error\n", 1450 device_xname(sc->sc_dev)); 1451 else { 1452 #define PRINTIT(x, str) \ 1453 if (rmd1 & (x)) \ 1454 printf("%s: %s\n", \ 1455 device_xname(sc->sc_dev), \ 1456 str); 1457 PRINTIT(LE_R1_FRAM, "framing error"); 1458 PRINTIT(LE_R1_CRC, "CRC error"); 1459 PRINTIT(LE_R1_BUFF, "buffer error"); 1460 } 1461 #undef PRINTIT 1462 PCN_INIT_RXDESC(sc, i); 1463 continue; 1464 } 1465 } 1466 1467 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1468 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1469 1470 /* 1471 * No errors; receive the packet. 1472 */ 1473 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1474 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1475 else 1476 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1477 1478 /* 1479 * The LANCE family includes the CRC with every packet; 1480 * trim it off here. 1481 */ 1482 len -= ETHER_CRC_LEN; 1483 1484 /* 1485 * If the packet is small enough to fit in a 1486 * single header mbuf, allocate one and copy 1487 * the data into it. This greatly reduces 1488 * memory consumption when we receive lots 1489 * of small packets. 1490 * 1491 * Otherwise, we add a new buffer to the receive 1492 * chain. If this fails, we drop the packet and 1493 * recycle the old buffer. 1494 */ 1495 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1496 MGETHDR(m, M_DONTWAIT, MT_DATA); 1497 if (m == NULL) 1498 goto dropit; 1499 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1500 m->m_data += 2; 1501 memcpy(mtod(m, void *), 1502 mtod(rxs->rxs_mbuf, void *), len); 1503 PCN_INIT_RXDESC(sc, i); 1504 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1505 rxs->rxs_dmamap->dm_mapsize, 1506 BUS_DMASYNC_PREREAD); 1507 } else { 1508 m = rxs->rxs_mbuf; 1509 if (pcn_add_rxbuf(sc, i) != 0) { 1510 dropit: 1511 if_statinc(ifp, if_ierrors); 1512 PCN_INIT_RXDESC(sc, i); 1513 bus_dmamap_sync(sc->sc_dmat, 1514 rxs->rxs_dmamap, 0, 1515 rxs->rxs_dmamap->dm_mapsize, 1516 BUS_DMASYNC_PREREAD); 1517 continue; 1518 } 1519 } 1520 1521 m_set_rcvif(m, ifp); 1522 m->m_pkthdr.len = m->m_len = len; 1523 1524 /* Pass it on. */ 1525 if_percpuq_enqueue(ifp->if_percpuq, m); 1526 } 1527 1528 /* Update the receive pointer. */ 1529 sc->sc_rxptr = i; 1530 return 0; 1531 } 1532 1533 /* 1534 * pcn_tick: 1535 * 1536 * One second timer, used to tick the MII. 1537 */ 1538 static void 1539 pcn_tick(void *arg) 1540 { 1541 struct pcn_softc *sc = arg; 1542 int s; 1543 1544 s = splnet(); 1545 mii_tick(&sc->sc_mii); 1546 splx(s); 1547 1548 callout_schedule(&sc->sc_tick_ch, hz); 1549 } 1550 1551 /* 1552 * pcn_reset: 1553 * 1554 * Perform a soft reset on the PCnet-PCI. 1555 */ 1556 static void 1557 pcn_reset(struct pcn_softc *sc) 1558 { 1559 1560 /* 1561 * The PCnet-PCI chip is reset by reading from the 1562 * RESET register. Note that while the NE2100 LANCE 1563 * boards require a write after the read, the PCnet-PCI 1564 * chips do not require this. 1565 * 1566 * Since we don't know if we're in 16-bit or 32-bit 1567 * mode right now, issue both (it's safe) in the 1568 * hopes that one will succeed. 1569 */ 1570 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1571 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1572 1573 /* Wait 1ms for it to finish. */ 1574 delay(1000); 1575 1576 /* 1577 * Select 32-bit I/O mode by issuing a 32-bit write to the 1578 * RDP. Since the RAP is 0 after a reset, writing a 0 1579 * to RDP is safe (since it simply clears CSR0). 1580 */ 1581 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1582 } 1583 1584 /* 1585 * pcn_init: [ifnet interface function] 1586 * 1587 * Initialize the interface. Must be called at splnet(). 1588 */ 1589 static int 1590 pcn_init(struct ifnet *ifp) 1591 { 1592 struct pcn_softc *sc = ifp->if_softc; 1593 struct pcn_rxsoft *rxs; 1594 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1595 int i, error = 0; 1596 uint32_t reg; 1597 1598 /* Cancel any pending I/O. */ 1599 pcn_stop(ifp, 0); 1600 1601 /* Reset the chip to a known state. */ 1602 pcn_reset(sc); 1603 1604 /* 1605 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1606 * else. 1607 * 1608 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1609 * because the structure layout is compatible with ILACC, 1610 * but the burst mode is only available in SSTYLE 3, and 1611 * burst mode should provide some performance enhancement. 1612 */ 1613 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1614 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1615 else 1616 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1617 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1618 1619 /* Initialize the transmit descriptor ring. */ 1620 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1621 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1622 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1623 sc->sc_txfree = PCN_NTXDESC; 1624 sc->sc_txnext = 0; 1625 1626 /* Initialize the transmit job descriptors. */ 1627 for (i = 0; i < PCN_TXQUEUELEN; i++) 1628 sc->sc_txsoft[i].txs_mbuf = NULL; 1629 sc->sc_txsfree = PCN_TXQUEUELEN; 1630 sc->sc_txsnext = 0; 1631 sc->sc_txsdirty = 0; 1632 1633 /* 1634 * Initialize the receive descriptor and receive job 1635 * descriptor rings. 1636 */ 1637 for (i = 0; i < PCN_NRXDESC; i++) { 1638 rxs = &sc->sc_rxsoft[i]; 1639 if (rxs->rxs_mbuf == NULL) { 1640 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1641 printf("%s: unable to allocate or map rx " 1642 "buffer %d, error = %d\n", 1643 device_xname(sc->sc_dev), i, error); 1644 /* 1645 * XXX Should attempt to run with fewer receive 1646 * XXX buffers instead of just failing. 1647 */ 1648 pcn_rxdrain(sc); 1649 goto out; 1650 } 1651 } else 1652 PCN_INIT_RXDESC(sc, i); 1653 } 1654 sc->sc_rxptr = 0; 1655 1656 /* Initialize MODE for the initialization block. */ 1657 sc->sc_mode = 0; 1658 if (ifp->if_flags & IFF_PROMISC) 1659 sc->sc_mode |= LE_C15_PROM; 1660 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1661 sc->sc_mode |= LE_C15_DRCVBC; 1662 1663 /* 1664 * If we have MII, simply select MII in the MODE register, 1665 * and clear ASEL. Otherwise, let ASEL stand (for now), 1666 * and leave PORTSEL alone (it is ignored with ASEL is set). 1667 */ 1668 if (sc->sc_flags & PCN_F_HAS_MII) { 1669 pcn_bcr_write(sc, LE_BCR2, 1670 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1671 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1672 1673 /* 1674 * Disable MII auto-negotiation. We handle that in 1675 * our own MII layer. 1676 */ 1677 pcn_bcr_write(sc, LE_BCR32, 1678 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1679 } 1680 1681 /* 1682 * Set the Tx and Rx descriptor ring addresses in the init 1683 * block, the TLEN and RLEN other fields of the init block 1684 * MODE register. 1685 */ 1686 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1687 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1688 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1689 (((uint32_t)ffs(PCN_NTXDESC) - 1) << 28) | 1690 ((ffs(PCN_NRXDESC) - 1) << 20)); 1691 1692 /* Set the station address in the init block. */ 1693 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1694 (enaddr[1] << 8) | (enaddr[2] << 16) | 1695 ((uint32_t)enaddr[3] << 24)); 1696 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1697 (enaddr[5] << 8)); 1698 1699 /* Set the multicast filter in the init block. */ 1700 pcn_set_filter(sc); 1701 1702 /* Initialize CSR3. */ 1703 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM | LE_C3_IDONM | LE_C3_DXSUFLO); 1704 1705 /* Initialize CSR4. */ 1706 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS | LE_C4_APAD_XMT | 1707 LE_C4_MFCOM | LE_C4_RCVCCOM | LE_C4_TXSTRTM); 1708 1709 /* Initialize CSR5. */ 1710 sc->sc_csr5 = LE_C5_LTINTEN | LE_C5_SINTE; 1711 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1712 1713 /* 1714 * If we have an Am79c971 or greater, initialize CSR7. 1715 * 1716 * XXX Might be nice to use the MII auto-poll interrupt someday. 1717 */ 1718 switch (sc->sc_variant->pcv_chipid) { 1719 case PARTID_Am79c970: 1720 case PARTID_Am79c970A: 1721 /* Not available on these chips. */ 1722 break; 1723 1724 default: 1725 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1726 break; 1727 } 1728 1729 /* 1730 * On the Am79c970A and greater, initialize BCR18 to 1731 * enable burst mode. 1732 * 1733 * Also enable the "no underflow" option on the Am79c971 and 1734 * higher, which prevents the chip from generating transmit 1735 * underflows, yet sill provides decent performance. Note if 1736 * chip is not connected to external SRAM, then we still have 1737 * to handle underflow errors (the NOUFLO bit is ignored in 1738 * that case). 1739 */ 1740 reg = pcn_bcr_read(sc, LE_BCR18); 1741 switch (sc->sc_variant->pcv_chipid) { 1742 case PARTID_Am79c970: 1743 break; 1744 1745 case PARTID_Am79c970A: 1746 reg |= LE_B18_BREADE | LE_B18_BWRITE; 1747 break; 1748 1749 default: 1750 reg |= LE_B18_BREADE | LE_B18_BWRITE | LE_B18_NOUFLO; 1751 break; 1752 } 1753 pcn_bcr_write(sc, LE_BCR18, reg); 1754 1755 /* 1756 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1757 */ 1758 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1759 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1760 1761 /* 1762 * Send the init block to the chip, and wait for it 1763 * to be processed. 1764 */ 1765 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1766 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1767 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1768 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1769 delay(100); 1770 for (i = 0; i < 10000; i++) { 1771 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1772 break; 1773 delay(10); 1774 } 1775 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1776 if (i == 10000) { 1777 printf("%s: timeout processing init block\n", 1778 device_xname(sc->sc_dev)); 1779 error = EIO; 1780 goto out; 1781 } 1782 1783 /* Set the media. */ 1784 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1785 goto out; 1786 1787 /* Enable interrupts and external activity (and ACK IDON). */ 1788 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT | LE_C0_IDON); 1789 1790 if (sc->sc_flags & PCN_F_HAS_MII) { 1791 /* Start the one second MII clock. */ 1792 callout_schedule(&sc->sc_tick_ch, hz); 1793 } 1794 1795 /* ...all done! */ 1796 ifp->if_flags |= IFF_RUNNING; 1797 1798 out: 1799 if (error) 1800 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1801 return error; 1802 } 1803 1804 /* 1805 * pcn_rxdrain: 1806 * 1807 * Drain the receive queue. 1808 */ 1809 static void 1810 pcn_rxdrain(struct pcn_softc *sc) 1811 { 1812 struct pcn_rxsoft *rxs; 1813 int i; 1814 1815 for (i = 0; i < PCN_NRXDESC; i++) { 1816 rxs = &sc->sc_rxsoft[i]; 1817 if (rxs->rxs_mbuf != NULL) { 1818 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1819 m_freem(rxs->rxs_mbuf); 1820 rxs->rxs_mbuf = NULL; 1821 } 1822 } 1823 } 1824 1825 /* 1826 * pcn_stop: [ifnet interface function] 1827 * 1828 * Stop transmission on the interface. 1829 */ 1830 static void 1831 pcn_stop(struct ifnet *ifp, int disable) 1832 { 1833 struct pcn_softc *sc = ifp->if_softc; 1834 struct pcn_txsoft *txs; 1835 int i; 1836 1837 if (sc->sc_flags & PCN_F_HAS_MII) { 1838 /* Stop the one second clock. */ 1839 callout_stop(&sc->sc_tick_ch); 1840 1841 /* Down the MII. */ 1842 mii_down(&sc->sc_mii); 1843 } 1844 1845 /* Stop the chip. */ 1846 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1847 1848 /* Release any queued transmit buffers. */ 1849 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1850 txs = &sc->sc_txsoft[i]; 1851 if (txs->txs_mbuf != NULL) { 1852 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1853 m_freem(txs->txs_mbuf); 1854 txs->txs_mbuf = NULL; 1855 } 1856 } 1857 1858 /* Mark the interface as down and cancel the watchdog timer. */ 1859 ifp->if_flags &= ~IFF_RUNNING; 1860 ifp->if_timer = 0; 1861 1862 if (disable) 1863 pcn_rxdrain(sc); 1864 } 1865 1866 /* 1867 * pcn_add_rxbuf: 1868 * 1869 * Add a receive buffer to the indicated descriptor. 1870 */ 1871 static int 1872 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1873 { 1874 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1875 struct mbuf *m; 1876 int error; 1877 1878 MGETHDR(m, M_DONTWAIT, MT_DATA); 1879 if (m == NULL) 1880 return ENOBUFS; 1881 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1882 1883 MCLGET(m, M_DONTWAIT); 1884 if ((m->m_flags & M_EXT) == 0) { 1885 m_freem(m); 1886 return ENOBUFS; 1887 } 1888 1889 if (rxs->rxs_mbuf != NULL) 1890 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1891 1892 rxs->rxs_mbuf = m; 1893 1894 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1895 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1896 BUS_DMA_READ | BUS_DMA_NOWAIT); 1897 if (error) { 1898 printf("%s: can't load rx DMA map %d, error = %d\n", 1899 device_xname(sc->sc_dev), idx, error); 1900 panic("pcn_add_rxbuf"); 1901 } 1902 1903 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1904 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1905 1906 PCN_INIT_RXDESC(sc, idx); 1907 1908 return 0; 1909 } 1910 1911 /* 1912 * pcn_set_filter: 1913 * 1914 * Set up the receive filter. 1915 */ 1916 static void 1917 pcn_set_filter(struct pcn_softc *sc) 1918 { 1919 struct ethercom *ec = &sc->sc_ethercom; 1920 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1921 struct ether_multi *enm; 1922 struct ether_multistep step; 1923 uint32_t crc; 1924 1925 /* 1926 * Set up the multicast address filter by passing all multicast 1927 * addresses through a CRC generator, and then using the high 1928 * order 6 bits as an index into the 64-bit logical address 1929 * filter. The high order bits select the word, while the rest 1930 * of the bits select the bit within the word. 1931 */ 1932 1933 if (ifp->if_flags & IFF_PROMISC) 1934 goto allmulti; 1935 1936 sc->sc_initblock.init_ladrf[0] = 1937 sc->sc_initblock.init_ladrf[1] = 1938 sc->sc_initblock.init_ladrf[2] = 1939 sc->sc_initblock.init_ladrf[3] = 0; 1940 1941 ETHER_LOCK(ec); 1942 ETHER_FIRST_MULTI(step, ec, enm); 1943 while (enm != NULL) { 1944 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1945 /* 1946 * We must listen to a range of multicast addresses. 1947 * For now, just accept all multicasts, rather than 1948 * trying to set only those filter bits needed to match 1949 * the range. (At this time, the only use of address 1950 * ranges is for IP multicast routing, for which the 1951 * range is big enough to require all bits set.) 1952 */ 1953 ETHER_UNLOCK(ec); 1954 goto allmulti; 1955 } 1956 1957 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1958 1959 /* Just want the 6 most significant bits. */ 1960 crc >>= 26; 1961 1962 /* Set the corresponding bit in the filter. */ 1963 sc->sc_initblock.init_ladrf[crc >> 4] |= 1964 htole16(1 << (crc & 0xf)); 1965 1966 ETHER_NEXT_MULTI(step, enm); 1967 } 1968 ETHER_UNLOCK(ec); 1969 1970 ifp->if_flags &= ~IFF_ALLMULTI; 1971 return; 1972 1973 allmulti: 1974 ifp->if_flags |= IFF_ALLMULTI; 1975 sc->sc_initblock.init_ladrf[0] = 1976 sc->sc_initblock.init_ladrf[1] = 1977 sc->sc_initblock.init_ladrf[2] = 1978 sc->sc_initblock.init_ladrf[3] = 0xffff; 1979 } 1980 1981 /* 1982 * pcn_79c970_mediainit: 1983 * 1984 * Initialize media for the Am79c970. 1985 */ 1986 static void 1987 pcn_79c970_mediainit(struct pcn_softc *sc) 1988 { 1989 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1990 struct mii_data * const mii = &sc->sc_mii; 1991 const char *sep = ""; 1992 1993 mii->mii_ifp = ifp; 1994 1995 ifmedia_init(&mii->mii_media, IFM_IMASK, pcn_79c970_mediachange, 1996 pcn_79c970_mediastatus); 1997 1998 #define ADD(str, m, d) \ 1999 do { \ 2000 aprint_normal("%s%s", sep, str); \ 2001 ifmedia_add(&mii->mii_media, IFM_ETHER | (m), (d), NULL); \ 2002 sep = ", "; \ 2003 } while (/*CONSTCOND*/0) 2004 2005 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2006 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2007 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2008 ADD("10base5-FDX", IFM_10_5 | IFM_FDX, PORTSEL_AUI); 2009 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2010 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2011 ADD("10baseT-FDX", IFM_10_T | IFM_FDX, PORTSEL_10T); 2012 ADD("auto", IFM_AUTO, 0); 2013 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2014 ADD("auto-FDX", IFM_AUTO | IFM_FDX, 0); 2015 aprint_normal("\n"); 2016 2017 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2018 } 2019 2020 /* 2021 * pcn_79c970_mediastatus: [ifmedia interface function] 2022 * 2023 * Get the current interface media status (Am79c970 version). 2024 */ 2025 static void 2026 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2027 { 2028 struct pcn_softc *sc = ifp->if_softc; 2029 2030 /* 2031 * The currently selected media is always the active media. 2032 * Note: We have no way to determine what media the AUTO 2033 * process picked. 2034 */ 2035 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2036 } 2037 2038 /* 2039 * pcn_79c970_mediachange: [ifmedia interface function] 2040 * 2041 * Set hardware to newly-selected media (Am79c970 version). 2042 */ 2043 static int 2044 pcn_79c970_mediachange(struct ifnet *ifp) 2045 { 2046 struct pcn_softc *sc = ifp->if_softc; 2047 uint32_t reg; 2048 2049 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2050 /* 2051 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2052 */ 2053 reg = pcn_bcr_read(sc, LE_BCR2); 2054 reg |= LE_B2_ASEL; 2055 pcn_bcr_write(sc, LE_BCR2, reg); 2056 } else { 2057 /* 2058 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2059 */ 2060 reg = pcn_bcr_read(sc, LE_BCR2); 2061 reg &= ~LE_B2_ASEL; 2062 pcn_bcr_write(sc, LE_BCR2, reg); 2063 2064 reg = pcn_csr_read(sc, LE_CSR15); 2065 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2066 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2067 pcn_csr_write(sc, LE_CSR15, reg); 2068 } 2069 2070 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2071 reg = LE_B9_FDEN; 2072 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2073 reg |= LE_B9_AUIFD; 2074 pcn_bcr_write(sc, LE_BCR9, reg); 2075 } else 2076 pcn_bcr_write(sc, LE_BCR9, 0); 2077 2078 return 0; 2079 } 2080 2081 /* 2082 * pcn_79c971_mediainit: 2083 * 2084 * Initialize media for the Am79c971. 2085 */ 2086 static void 2087 pcn_79c971_mediainit(struct pcn_softc *sc) 2088 { 2089 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2090 struct mii_data * const mii = &sc->sc_mii; 2091 2092 /* We have MII. */ 2093 sc->sc_flags |= PCN_F_HAS_MII; 2094 2095 /* 2096 * The built-in 10BASE-T interface is mapped to the MII 2097 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2098 * word that tells us which PHY to use. 2099 * This driver used to ignore all but the first PHY to 2100 * answer, but this code was removed to support multiple 2101 * external PHYs. As the default instance will be the first 2102 * one to answer, no harm is done by letting the possibly 2103 * non-connected internal PHY show up. 2104 */ 2105 2106 /* Initialize our media structures and probe the MII. */ 2107 mii->mii_ifp = ifp; 2108 mii->mii_readreg = pcn_mii_readreg; 2109 mii->mii_writereg = pcn_mii_writereg; 2110 mii->mii_statchg = pcn_mii_statchg; 2111 2112 sc->sc_ethercom.ec_mii = mii; 2113 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 2114 2115 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 2116 MII_OFFSET_ANY, 0); 2117 if (LIST_FIRST(&mii->mii_phys) == NULL) { 2118 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 2119 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 2120 } else 2121 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2122 } 2123 2124 /* 2125 * pcn_mii_readreg: [mii interface function] 2126 * 2127 * Read a PHY register on the MII. 2128 */ 2129 static int 2130 pcn_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2131 { 2132 struct pcn_softc *sc = device_private(self); 2133 2134 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2135 *val = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2136 if (*val == 0xffff) 2137 return -1; 2138 2139 return 0; 2140 } 2141 2142 /* 2143 * pcn_mii_writereg: [mii interface function] 2144 * 2145 * Write a PHY register on the MII. 2146 */ 2147 static int 2148 pcn_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2149 { 2150 struct pcn_softc *sc = device_private(self); 2151 2152 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2153 pcn_bcr_write(sc, LE_BCR34, val); 2154 2155 return 0; 2156 } 2157 2158 /* 2159 * pcn_mii_statchg: [mii interface function] 2160 * 2161 * Callback from MII layer when media changes. 2162 */ 2163 static void 2164 pcn_mii_statchg(struct ifnet *ifp) 2165 { 2166 struct pcn_softc *sc = ifp->if_softc; 2167 2168 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2169 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2170 else 2171 pcn_bcr_write(sc, LE_BCR9, 0); 2172 } 2173
Indexes created Fri Sep 26 20:09:58 GMT 2025