1 /* $NetBSD: pgtimer.c,v 1.1 2026/07/19 01:48:24 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2025 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pgtimer.c,v 1.1 2026/07/19 01:48:24 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 41 #include <machine/clockvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 struct pgtimer_softc { 46 device_t sc_dev; 47 bus_space_tag_t sc_st; 48 bus_space_handle_t sc_sh; 49 uint32_t sc_reg_shift; 50 void *sc_ih; 51 uint32_t sc_freq; 52 struct clock_attach_args sc_clock_args; 53 void (*sc_handler)(struct clockframe *); 54 struct evcnt *sc_evcnt; 55 }; 56 57 #define TIMER_CSR 0 58 #define CSR_ENAB __BIT(0) 59 #define CSR_IPEND __BIT(1) 60 #define TIMER_VAL 1 61 62 #define REG_OFF(sc, r) ((r) << (sc)->sc_reg_shift) 63 64 #define REG_READ(sc, r) \ 65 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, REG_OFF((sc), (r))) 66 #define REG_WRITE(sc, r, v) \ 67 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, REG_OFF((sc), (r)), (v)) 68 69 static const struct device_compatible_entry compat_data[] = { 70 { .compat = "pg68k,ioctl010-timer" }, 71 DEVICE_COMPAT_EOL 72 }; 73 74 static uint32_t 75 pgtimer_us_to_ticks(struct pgtimer_softc *sc, unsigned int interval_us) 76 { 77 const uint32_t tick_ns = 1000000000 / sc->sc_freq; 78 const uint64_t interval_ns = interval_us * 1000; 79 const uint64_t ticks = interval_ns / tick_ns; 80 81 if (ticks == 0 || ticks > 0xffff) { 82 panic("%s: impossible interval %u us (ticks=%llu)", __func__, 83 interval_us, ticks); 84 } 85 86 return (uint32_t)ticks; 87 } 88 89 static void 90 pgtimer_initclock(void *arg, unsigned int interval_us, 91 struct evcnt *ev, void (*func)(struct clockframe *)) 92 { 93 struct pgtimer_softc *sc = arg; 94 const uint32_t ticks = pgtimer_us_to_ticks(sc, interval_us); 95 96 sc->sc_handler = func; 97 sc->sc_evcnt = ev; 98 99 /* 100 * Changing the counter reload value implicitly disables the 101 * timer. The reload value is set by writing the high byte 102 * followed by the load byte to the Value register. The reload 103 * value is unpredictable until both bytes have been written. 104 */ 105 REG_WRITE(sc, TIMER_VAL, (uint8_t)(ticks >> 8)); 106 REG_WRITE(sc, TIMER_VAL, (uint8_t)ticks); 107 REG_WRITE(sc, TIMER_CSR, CSR_ENAB); 108 } 109 110 #define CLOCK_HANDLER() \ 111 do { \ 112 /* Clear interrupt condition. */ \ 113 REG_READ(sc, TIMER_CSR); \ 114 \ 115 /* Timer auto-reloads. */ \ 116 \ 117 /* Increment the counter and call the handler. */ \ 118 sc->sc_evcnt->ev_count++; \ 119 sc->sc_handler((struct clockframe *)v); \ 120 } while (/*CONSTCOND*/0) 121 122 static int 123 pgtimer_hardclock(void *v) 124 { 125 struct pgtimer_softc *sc = clock_devices[CLOCK_HARDCLOCK]; 126 127 CLOCK_HANDLER(); 128 return 1; 129 } 130 131 static int 132 pgtimer_statclock(void *v) 133 { 134 struct pgtimer_softc *sc = clock_devices[CLOCK_STATCLOCK]; 135 136 CLOCK_HANDLER(); 137 return 1; 138 } 139 140 static void *pgtimer_isrs[NCLOCKS] = { 141 [CLOCK_HARDCLOCK] = pgtimer_hardclock, 142 [CLOCK_STATCLOCK] = pgtimer_statclock, 143 }; 144 145 static int 146 pgtimer_match(device_t parent, cfdata_t cf, void *aux) 147 { 148 struct fdt_attach_args * const faa = aux; 149 150 return of_compatible_match(faa->faa_phandle, compat_data); 151 } 152 153 static void 154 pgtimer_attach(device_t parent, device_t self, void *aux) 155 { 156 struct pgtimer_softc * const sc = device_private(self); 157 struct fdt_attach_args * const faa = aux; 158 const int phandle = faa->faa_phandle; 159 bus_addr_t addr; 160 bus_size_t size; 161 char intrstr[128]; 162 struct clk *clk; 163 uint32_t clk_div; 164 int which, error; 165 166 sc->sc_dev = self; 167 sc->sc_st = faa->faa_bst; 168 169 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 170 aprint_error(": couldn't get registers\n"); 171 return; 172 } 173 174 if (of_getprop_uint32(phandle, "reg-shift", &sc->sc_reg_shift)) { 175 /* missing or bad reg-shift property, assume 0 */ 176 sc->sc_reg_shift = 0; 177 } 178 179 error = bus_space_map(sc->sc_st, addr, size, 0, &sc->sc_sh); 180 if (error) { 181 aprint_error(": couldn't map registers (error=%d)\n", error); 182 return; 183 } 184 185 /* Make sure the timer is disabled. */ 186 REG_WRITE(sc, TIMER_CSR, 0); 187 188 clk = fdtbus_clock_get_index(phandle, 0); 189 if (clk == NULL) { 190 aprint_error(": couldn't get clock handle\n"); 191 return; 192 } 193 194 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 195 aprint_error(": failed to decode interrupt\n"); 196 return; 197 } 198 199 /* 200 * The input to the I/O controller is the main system clock, 201 * which the timer divides itself internally. Firmware will 202 * provide this value in the device tree. 203 */ 204 if (of_getprop_uint32(phandle, "clock-div", &clk_div)) { 205 /* default to divide-by-16 */ 206 clk_div = 16; 207 } 208 209 sc->sc_freq = clk_get_rate(clk) / clk_div; 210 211 aprint_naive("\n"); 212 aprint_normal(": frequency %u Hz\n", sc->sc_freq); 213 214 which = clock_from_phandle(phandle); 215 if (which == CLOCK_NONE || pgtimer_isrs[which] == NULL) { 216 return; 217 } 218 219 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SCHED, 220 FDT_INTR_MPSAFE, pgtimer_isrs[which], NULL, device_xname(self)); 221 if (sc->sc_ih == NULL) { 222 aprint_error_dev(self, "failed to establish interrupt at %s\n", 223 intrstr); 224 return; 225 } 226 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 227 228 sc->sc_clock_args.ca_initfunc = pgtimer_initclock; 229 sc->sc_clock_args.ca_arg = sc; 230 sc->sc_clock_args.ca_which = which; 231 clock_attach(self, &sc->sc_clock_args); 232 } 233 234 CFATTACH_DECL_NEW(pgtimer, sizeof(struct pgtimer_softc), 235 pgtimer_match, pgtimer_attach, NULL, NULL); 236
Indexes created Fri Jul 31 00:23:59 UTC 2026