| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| jh7100-beaglev-starlight.dts | 16 phy-handle = <&phy>;
20 phy: ethernet-phy@7 { label
|
| jh7100-starfive-visionfive-v1.dts | 22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
32 * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
36 phy: ethernet-phy@0 { label
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| rk3228-evb.dts | 20 vcc_phy: vcc-phy-regulator {
43 phy-supply = <&vcc_phy>;
44 phy-mode = "rmii";
45 phy-handle = <&phy>;
53 phy: ethernet-phy@0 { label
54 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
58 phy-is-integrated
[all...] |
| zynq-ebaz4205.dts | 34 phy-mode = "mii";
35 phy-handle = <&phy>;
37 /* PHY clock */
41 phy: ethernet-phy@0 { label
|
| imx6dl-eckelmann-ci4x10.dts | 27 /* This clock is provided by the phy (KSZ8091RNB) */
297 phy-mode = "rmii";
298 phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
299 phy-handle = <&phy>;
307 phy: ethernet-phy@1 { label
308 compatible = "ethernet-phy-ieee802.3-c22";
|
| rk3229-xms6.dts | 66 vcc_phy: vcc-phy-regulator {
154 phy-handle = <&phy>;
155 phy-mode = "rmii";
156 phy-supply = <&vcc_phy>;
164 phy: ethernet-phy@0 { label
165 compatible = "ethernet-phy-id1234.d400",
166 "ethernet-phy-ieee802.3-c22";
169 phy-is-integrated
[all...] |
| imx6q-tbs2910.dts | 108 phy-mode = "rgmii-id";
109 phy-handle = <&phy>;
116 phy: ethernet-phy@4 { label
|
| imx6qdl-ds.dtsi | 85 phy-mode = "rgmii-id";
86 phy-handle = <&phy>;
94 phy: ethernet-phy@1 { label
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/ |
| tegra194-p3668.dtsi | 31 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
32 phy-handle = <&phy>;
33 phy-mode = "rgmii-id";
39 phy: phy@0 { label
40 compatible = "ethernet-phy-ieee802.3-c22";
44 #phy-cells = <0>;
|
| tegra186-p3310.dtsi | 38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
47 phy: phy@0 { label
48 compatible = "ethernet-phy-ieee802.3-c22";
54 #phy-cells = <0>;
|
| tegra194-p2888.dtsi | 34 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
35 phy-handle = <&phy>;
36 phy-mode = "rgmii-id";
42 phy: phy@0 { label
43 compatible = "ethernet-phy-ieee802.3-c22";
47 #phy-cells = <0>;
|
| tegra186-p3509-0000+p3636-0001.dts | 41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
49 phy: phy@0 { label
50 compatible = "ethernet-phy-ieee802.3-c22";
54 #phy-cells = <0>;
221 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-1";
228 phy-names = "usb2-0"
[all...] |
| /src/sys/dev/pci/igc/ |
| igc_base.c | 19 * igc_acquire_phy_base - Acquire rights to access PHY
22 * Acquire access rights to the correct PHY.
38 * igc_release_phy_base - Release rights to access PHY
41 * A wrapper to release access rights to the correct PHY.
98 * igc_power_down_phy_copper_base - Remove link during PHY power down
101 * In the case of a PHY power down to save power, or to turn off link during a
107 struct igc_phy_info *phy = &hw->phy; local in function:igc_power_down_phy_copper_base
109 if (!(phy->ops.check_reset_block))
113 if (phy->ops.check_reset_block(hw)
[all...] |
| /src/sys/arch/arm/samsung/ |
| exynos_ehci.c | 74 struct fdtbus_phy *phy; local in function:exynos_ehci_attach
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| exynos_ohci.c | 74 struct fdtbus_phy *phy; local in function:exynos_ohci_attach
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| /src/sys/arch/arm/ti/ |
| ti_ehci.c | 77 struct fdtbus_phy *phy; local in function:ti_ehci_attach
124 phy = fdtbus_phy_get_index(phandle, n);
125 if (phy && fdtbus_phy_enable(phy, true) != 0) {
126 aprint_error(": couldn't enable phy\n");
|
| /src/sys/dev/fdt/ |
| ehci_fdt.c | 75 struct fdtbus_phy *phy; local in function:ehci_fdt_attach
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| ohci_fdt.c | 75 struct fdtbus_phy *phy; local in function:ohci_fdt_attach
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| fdt_phy.c | 84 struct fdtbus_phy *phy = NULL; local in function:fdtbus_phy_get_index
109 if (of_getprop_uint32(pc_phandle, "#phy-cells", &phy_cells))
118 phy = kmem_alloc(sizeof(*phy), KM_SLEEP);
119 phy->phy_pc = pc;
120 phy->phy_priv = phy_priv;
133 return phy;
142 err = fdtbus_get_index(phandle, "phy-names", phyname, &index);
150 fdtbus_phy_put(struct fdtbus_phy *phy)
152 struct fdtbus_phy_controller *pc = phy->phy_pc
[all...] |
| dwc2_fdt.c | 120 struct fdtbus_phy *phy; local in function:dwc2_fdt_attach
143 /* Enable optional phy */
144 phy = fdtbus_phy_get(phandle, "usb2-phy");
145 if (phy && fdtbus_phy_enable(phy, true) != 0) {
146 aprint_error(": couldn't enable phy\n");
|
| cdns3_fdt.c | 93 struct fdtbus_phy *phy; local in function:cdns3_fdt_attach
172 /* Enable PHY devices */
174 phy = fdtbus_phy_get_index(phandle, i);
175 if (phy == NULL)
177 if (fdtbus_phy_enable(phy, true) != 0)
178 aprint_error_dev(self, "couldn't enable phy #%d\n", i);
|
| /src/sys/arch/hpcmips/vr/ |
| vrdmaau.c | 96 u_int32_t phy; local in function:vrdmaau_set_aiuin
101 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
104 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAH_REG_W, phy >> 16);
105 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAL_REG_W, phy & 0xffff);
113 u_int32_t phy; local in function:vrdmaau_set_aiuout
118 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
121 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAH_REG_W, phy >> 16);
122 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAL_REG_W, phy & 0xffff);
130 u_int32_t phy; local in function:vrdmaau_set_fir
135 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sunxi_musb.c | 308 struct fdtbus_phy *phy; local in function:sunxi_musb_attach
342 /* Enable optional phy */
343 phy = fdtbus_phy_get(phandle, "usb");
344 if (phy && fdtbus_phy_enable(phy, true) != 0) {
345 aprint_error(": couldn't enable phy\n");
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_combo_phy.c | 46 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
47 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56 val = I915_READ(ICL_PORT_COMP_DW3(phy));
82 enum phy phy)
87 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
89 val = I915_READ(ICL_PORT_COMP_DW1(phy));
92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val)
141 enum phy phy = PHY_A; local in function:cnl_combo_phy_verify_state
299 enum phy phy; local in function:icl_combo_phys_init
353 enum phy phy; local in function:icl_combo_phys_uninit
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra_ahcisata.c | 297 /* PHY config */
417 struct fdtbus_phy *phy; local in function:tegra_ahcisata_init_clocks
418 for (u_int n = 0; (phy = fdtbus_phy_get_index(sc->sc_phandle, n)) != NULL; n++)
419 if (fdtbus_phy_enable(phy, true) != 0)
420 aprint_error_dev(self, "failed to enable PHY #%d\n", n);
|
