| /src/sys/dev/pci/igc/ |
| igc_base.c | 19 * igc_acquire_phy_base - Acquire rights to access PHY
22 * Acquire access rights to the correct PHY.
38 * igc_release_phy_base - Release rights to access PHY
41 * A wrapper to release access rights to the correct PHY.
98 * igc_power_down_phy_copper_base - Remove link during PHY power down
101 * In the case of a PHY power down to save power, or to turn off link during a
107 struct igc_phy_info *phy = &hw->phy; local
109 if (!(phy->ops.check_reset_block))
113 if (phy->ops.check_reset_block(hw)
[all...] |
| igc_phy.c | 16 * igc_init_phy_ops_generic - Initialize PHY function pointers
24 struct igc_phy_info *phy = &hw->phy; local
28 phy->ops.init_params = igc_null_ops_generic;
29 phy->ops.acquire = igc_null_ops_generic;
30 phy->ops.check_reset_block = igc_null_ops_generic;
31 phy->ops.force_speed_duplex = igc_null_ops_generic;
32 phy->ops.get_info = igc_null_ops_generic;
33 phy->ops.set_page = igc_null_set_page;
34 phy->ops.read_reg = igc_null_read_reg
142 struct igc_phy_info *phy = &hw->phy; local
179 struct igc_phy_info *phy = &hw->phy; local
237 struct igc_phy_info *phy = &hw->phy; local
292 struct igc_phy_info *phy = &hw->phy; local
470 struct igc_phy_info *phy = &hw->phy; local
586 struct igc_phy_info *phy = &hw->phy; local
704 struct igc_phy_info *phy = &hw->phy; local
[all...] |
| /src/sys/arch/arm/samsung/ |
| exynos_ehci.c | 74 struct fdtbus_phy *phy; local
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| exynos_ohci.c | 74 struct fdtbus_phy *phy; local
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| exynos_usbphy.c | 70 { .compat = "samsung,exynos5250-usb2-phy" },
130 struct exynos_usbphy * const phy = priv; local
131 struct exynos_usbphy_softc * const sc = phy->phy_sc;
186 switch (phy->phy_index) {
190 const bus_size_t reg = phy->phy_index == PHY_ID_HSIC0 ?
248 aprint_error(": couldn't get phy registers\n");
256 aprint_error(": couldn't map phy registers\n");
278 clk = fdtbus_clock_get(phandle, "phy");
280 aprint_error(": couldn't enable phy clock\n");
290 aprint_normal(": USB2 PHY\n")
[all...] |
| exynos_usbdrdphy.c | 44 * PHY Registers
93 { .compat = "samsung,exynos5420-usbdrd-phy" },
149 struct exynos_usbdrdphy * const phy = priv; local
150 struct exynos_usbdrdphy_softc * const sc = phy->phy_sc;
154 val = syscon_read_4(sc->sc_pmureg, USBDRD_PHY_CTRL(phy->phy_index));
159 syscon_write_4(sc->sc_pmureg, USBDRD_PHY_CTRL(phy->phy_index), val);
245 aprint_error(": couldn't get phy registers\n");
253 aprint_error(": couldn't map phy registers\n");
271 clk = fdtbus_clock_get(phandle, "phy");
273 aprint_error(": couldn't enable phy clock\n")
[all...] |
| /src/sys/arch/arm/ti/ |
| ti_ehci.c | 77 struct fdtbus_phy *phy; local
124 phy = fdtbus_phy_get_index(phandle, n);
125 if (phy && fdtbus_phy_enable(phy, true) != 0) {
126 aprint_error(": couldn't enable phy\n");
|
| ti_omapmusb.c | 172 struct fdtbus_phy *phy; local
192 phy = fdtbus_phy_get(phandle, "usb2-phy");
193 if (phy && fdtbus_phy_enable(phy, true) != 0) {
194 aprint_error(": couldn't enable phy\n");
|
| /src/sys/dev/fdt/ |
| ehci_fdt.c | 75 struct fdtbus_phy *phy; local
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| ohci_fdt.c | 75 struct fdtbus_phy *phy; local
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| dwc2_fdt.c | 120 struct fdtbus_phy *phy; local
143 /* Enable optional phy */
144 phy = fdtbus_phy_get(phandle, "usb2-phy");
145 if (phy && fdtbus_phy_enable(phy, true) != 0) {
146 aprint_error(": couldn't enable phy\n");
|
| fdt_phy.c | 84 struct fdtbus_phy *phy = NULL; local
109 if (of_getprop_uint32(pc_phandle, "#phy-cells", &phy_cells))
118 phy = kmem_alloc(sizeof(*phy), KM_SLEEP);
119 phy->phy_pc = pc;
120 phy->phy_priv = phy_priv;
133 return phy;
142 err = fdtbus_get_index(phandle, "phy-names", phyname, &index);
150 fdtbus_phy_put(struct fdtbus_phy *phy)
152 struct fdtbus_phy_controller *pc = phy->phy_pc
[all...] |
| cdns3_fdt.c | 93 struct fdtbus_phy *phy; local
172 /* Enable PHY devices */
174 phy = fdtbus_phy_get_index(phandle, i);
175 if (phy == NULL)
177 if (fdtbus_phy_enable(phy, true) != 0)
178 aprint_error_dev(self, "couldn't enable phy #%d\n", i);
|
| dwc3_fdt.c | 105 /* Assert USB3 PHY reset */
108 /* Assert USB2 PHY reset */
113 /* Clear USB3 PHY reset */
116 /* Clear USB2 PHY reset */
164 if (of_hasprop(phandle, "snps,dis-del-phy-power-chg-quirk"))
236 struct fdtbus_phy *phy; local
323 /* Enable PHY devices */
324 for (n = 0; (phy = fdtbus_phy_get_index(dwc3_phandle, n)) != NULL; n++) {
325 if (fdtbus_phy_enable(phy, true) != 0)
326 aprint_error_dev(self, "couldn't enable phy #%d\n", n)
[all...] |
| /src/sys/arch/hpcmips/vr/ |
| vrdmaau.c | 96 u_int32_t phy; local
101 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
104 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAH_REG_W, phy >> 16);
105 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAL_REG_W, phy & 0xffff);
113 u_int32_t phy; local
118 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
121 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAH_REG_W, phy >> 16);
122 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAL_REG_W, phy & 0xffff);
130 u_int32_t phy; local
135 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sunxi_musb.c | 308 struct fdtbus_phy *phy; local
342 /* Enable optional phy */
343 phy = fdtbus_phy_get(phandle, "usb");
344 if (phy && fdtbus_phy_enable(phy, true) != 0) {
345 aprint_error(": couldn't enable phy\n");
|
| sunxi_usb3phy.c | 71 { .compat = "allwinner,sun50i-h6-usb3-phy", .value = USB3PHY_H6 },
91 #define PHY_READ(phy, reg) \
92 bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg))
93 #define PHY_WRITE(phy, reg, val) \
94 bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val))
115 struct sunxi_usb3phy * const phy = priv; local
119 val = PHY_READ(phy, SUNXI_PHY_EXTERNAL_CONTROL);
123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val)
170 struct sunxi_usb3phy *phy = &sc->sc_phy; local
[all...] |
| sunxi_usbphy.c | 42 /* PHY control registers */
59 /* PHY registers */
89 { .compat = "allwinner,sun4i-a10-usb-phy", .value = USBPHY_A10 },
90 { .compat = "allwinner,sun5i-a13-usb-phy", .value = USBPHY_A13 },
91 { .compat = "allwinner,sun6i-a31-usb-phy", .value = USBPHY_A31 },
92 { .compat = "allwinner,sun7i-a20-usb-phy", .value = USBPHY_A20 },
93 { .compat = "allwinner,sun8i-a83t-usb-phy", .value = USBPHY_A83T },
94 { .compat = "allwinner,sun8i-h3-usb-phy", .value = USBPHY_H3 },
95 { .compat = "allwinner,sun8i-v3s-usb-phy", .value = USBPHY_H3 },
96 { .compat = "allwinner,sun20i-d1-usb-phy", .value = USBPHY_D1 }
222 struct sunxi_usbphy * const phy = priv; local
352 struct sunxi_usbphy *phy; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_combo_phy.c | 46 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
47 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56 val = I915_READ(ICL_PORT_COMP_DW3(phy));
82 enum phy phy)
87 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
89 val = I915_READ(ICL_PORT_COMP_DW1(phy));
92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val)
141 enum phy phy = PHY_A; local
299 enum phy phy; local
353 enum phy phy; local
[all...] |
| intel_dpio_phy.c | 39 * ports. DPIO is the name given to such a display PHY. These PHYs
42 * sideband. VLV has one such PHY for driving ports B and C, and CHV
43 * adds another PHY for driving port D. Each PHY responds to specific
46 * Each display PHY is made up of one or two channels. Each channel
63 * Additionally the PHY also contains an AUX lane with AUX blocks
72 * For dual channel PHY (VLV/CHV):
85 * For single channel PHY (CHV):
91 * On BXT the entire PHY channel corresponds to the port. That means
101 * Dual channel PHY (VLV/CHV/BXT
277 enum dpio_phy phy; local
600 enum dpio_phy phy; local
626 enum dpio_phy phy; local
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_dwmac.c | 194 int miiclk, phandle_phy, phy = MII_PHY_ANY; local
234 phy_mode = fdtbus_get_string(phandle, "phy-mode");
236 aprint_error(": missing 'phy-mode' property\n");
239 phandle_phy = fdtbus_get_phandle(phandle, "phy-handle");
241 of_getprop_uint32(phandle_phy, "reg", &phy);
251 aprint_error(": unsupported phy-mode '%s'\n", phy_mode);
279 * properties on the phy node for the MAC reset information.
287 aprint_error_dev(self, "PHY reset failed\n");
304 dwc_gmac_attach(sc, phy, miiclk);
|
| /src/sys/arch/arm/nvidia/ |
| tegra_ahcisata.c | 297 /* PHY config */
417 struct fdtbus_phy *phy; local
418 for (u_int n = 0; (phy = fdtbus_phy_get_index(sc->sc_phandle, n)) != NULL; n++)
419 if (fdtbus_phy_enable(phy, true) != 0)
420 aprint_error_dev(self, "failed to enable PHY #%d\n", n);
|
| /src/sys/dev/ic/ |
| arn9280.c | 167 uint32_t phy, reg, ndiv = 0; local
170 phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
173 phy |= (freq << 16) / 15;
174 phy |= AR9280_BMODE | AR9280_FRACMODE;
205 phy |= SM(AR9280_AMODE_REFSEL, 3);
209 phy |= SM(AR9280_AMODE_REFSEL, 2);
213 phy |= (ndiv & 0x1ff) << 17;
214 phy |= (ndiv & ~0x1ff) * 2;
217 phy |= (freq << 15) / 15;
218 phy |= AR9280_FRACMODE
[all...] |
| arn9380.c | 268 uint32_t chansel, phy; local
289 phy = (chansel << 2) | AR9380_FRACMODE;
290 DPRINTFN(DBG_RF, sc, "AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy);
291 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
294 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
|
| /src/sys/dev/pci/ixgbe/ |
| ixgbe_x540.c | 68 struct ixgbe_phy_info *phy = &hw->phy; local
88 /* PHY */
89 phy->ops.init = ixgbe_init_phy_ops_generic;
90 phy->ops.reset = NULL;
91 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
208 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
222 u32 swfw_mask = hw->phy.phy_semaphore_mask;
350 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
539 * FW, PHY module, and PCIe Expansion/Option ROM pointers
[all...] |
