1 /* $NetBSD: pckbc_ebus.c,v 1.4 2021/01/04 14:48:51 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: pckbc_ebus.c,v 1.4 2021/01/04 14:48:51 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/kmem.h> 38 #include <sys/bus.h> 39 #include <sys/intr.h> 40 41 #include <machine/autoconf.h> 42 43 #include <dev/ic/i8042reg.h> 44 #include <dev/ic/pckbcvar.h> 45 #include <dev/pckbport/pckbportvar.h> 46 47 #include <dev/ebus/ebusreg.h> 48 #include <dev/ebus/ebusvar.h> 49 50 #include "opt_tadpmu.h" 51 #include <sparc64/dev/tadpmureg.h> 52 #include <sparc64/dev/tadpmuvar.h> 53 54 struct pckbc_ebus_softc { 55 struct pckbc_softc psc_pckbc; /* real "pckbc" softc */ 56 uint32_t psc_intr[5]; /* Tadpole Viper's pckbc has 3 slots */ 57 }; 58 59 static int pckbc_ebus_match(device_t, cfdata_t, void *); 60 static void pckbc_ebus_attach(device_t, device_t, void *); 61 62 static void pckbc_ebus_intr_establish(struct pckbc_softc *, pckbport_slot_t); 63 64 #define PCKBC_PROM_DEVICE_NAME "8042" 65 #define PCKBC_PROM_DEVICE_NAME2 "kb_ps2" 66 67 CFATTACH_DECL_NEW(pckbc_ebus, sizeof(struct pckbc_ebus_softc), 68 pckbc_ebus_match, pckbc_ebus_attach, NULL, NULL); 69 70 71 static int 72 pckbc_ebus_match(device_t parent, cfdata_t cf, void *aux) 73 { 74 struct ebus_attach_args *ea = aux; 75 76 if (strcmp(ea->ea_name, PCKBC_PROM_DEVICE_NAME) == 0 || 77 strcmp(ea->ea_name, PCKBC_PROM_DEVICE_NAME2) == 0) 78 return 1; 79 return 0; 80 } 81 82 static void 83 pckbc_ebus_attach(device_t parent, device_t self, void *aux) 84 { 85 struct pckbc_ebus_softc *sc = device_private(self); 86 struct pckbc_softc *psc = (struct pckbc_softc *) sc; 87 struct ebus_attach_args *ea = aux; 88 struct pckbc_internal *t; 89 bus_space_tag_t iot; 90 bus_addr_t ioaddr; 91 int stdin_node, node; 92 int isconsole, i; 93 94 psc->sc_dv = self; 95 iot = ea->ea_bustag; 96 ioaddr = EBUS_ADDR_FROM_REG(&ea->ea_reg[0]); 97 98 stdin_node = prom_instance_to_package(prom_stdin()); 99 isconsole = 0; 100 for (node = prom_firstchild(ea->ea_node); 101 node != 0; node = prom_nextsibling(node)) 102 if (node == stdin_node) { 103 isconsole = 1; 104 break; 105 } 106 107 psc->intr_establish = pckbc_ebus_intr_establish; 108 109 if (ea->ea_nintr < PCKBC_NSLOTS) { 110 aprint_error(": no intr %d", ea->ea_nintr); 111 112 /* 113 * XXX OpenBIOS doesn't provide interrupts for pckbc 114 * currently, so use the interrupt numbers described in 115 * QEMU's hw/sparc64/sun4u.c::isa_irq_handler. 116 */ 117 if (strcmp(machine_model, "OpenBiosTeam,OpenBIOS") == 0) { 118 sc->psc_intr[PCKBC_KBD_SLOT] = 0x29; 119 sc->psc_intr[PCKBC_AUX_SLOT] = 0x2a; 120 } else { 121 aprint_error("\n"); 122 return; 123 } 124 } else { 125 for (i = 0; i < ea->ea_nintr; i++) 126 sc->psc_intr[i] = ea->ea_intr[i]; 127 } 128 129 if (isconsole) { 130 int status; 131 132 status = pckbc_cnattach(iot, ioaddr, KBCMDP, 0, 133 PCKBC_NEED_AUXWRITE | PCKBC_CANT_TRANSLATE); 134 if (status == 0) 135 aprint_normal(": cnattach ok"); 136 else 137 aprint_error(": cnattach %d", status); 138 } 139 140 if (pckbc_is_console(iot, ioaddr)) { 141 t = &pckbc_consdata; 142 pckbc_console_attached = 1; 143 } else { 144 bus_space_handle_t ioh_d, ioh_c; 145 146 if (bus_space_map(iot, ioaddr + KBDATAP, 1, 0, &ioh_d) != 0) { 147 aprint_error(": unable to map data register\n"); 148 return; 149 } 150 151 if (bus_space_map(iot, ioaddr + KBCMDP, 1, 0, &ioh_c) != 0) { 152 bus_space_unmap(iot, ioh_d, 1); 153 aprint_error(": unable to map cmd register\n"); 154 return; 155 } 156 157 t = kmem_zalloc(sizeof(struct pckbc_internal), KM_SLEEP); 158 t->t_iot = iot; 159 t->t_ioh_d = ioh_d; 160 t->t_ioh_c = ioh_c; 161 t->t_addr = ioaddr; 162 t->t_cmdbyte = KC8_CPU; /* initial command: enable ports */ 163 callout_init(&t->t_cleanup, 0); 164 165 (void) pckbc_poll_data1(t, PCKBC_KBD_SLOT); /* flush */ 166 167 if (pckbc_send_cmd(iot, ioh_c, KBC_SELFTEST) == 0) 168 aprint_error(": unable to request self test"); 169 else { 170 int response; 171 172 response = pckbc_poll_data1(t, PCKBC_KBD_SLOT); 173 if (response == 0x55) 174 aprint_normal(": selftest ok"); 175 else 176 aprint_error(": selftest failed (0x%02x)", 177 response); 178 } 179 } 180 181 /* crosslink */ 182 t->t_sc = psc; 183 psc->id = t; 184 185 /* finish off the attach */ 186 aprint_normal("\n"); 187 pckbc_attach(psc); 188 #ifdef HAVE_TADPMU 189 /* now look for a tadpmu child device */ 190 char name[64], *p; 191 int pmu = 0; 192 for (node = prom_firstchild(ea->ea_node); 193 node != 0; node = prom_nextsibling(node)) { 194 if((p = prom_getpropstringA(node, "name", name, 64)) != NULL) { 195 if (strcmp(name, "tadpmu") == 0) { 196 pmu = node; 197 break; 198 } 199 } 200 } 201 if (pmu != 0) { 202 void *irq; 203 204 bus_space_handle_t hcmd, hdata; 205 if (bus_space_map(iot, ioaddr + TADPMU_CMD, 1, 0, &hcmd) != 0) { 206 bus_space_unmap(iot, hcmd, 1); 207 aprint_error(": unable to map PMU cmd register\n"); 208 return; 209 } 210 if (bus_space_map(iot, ioaddr + TADPMU_DATA, 1, 0, &hdata) != 0) { 211 bus_space_unmap(iot, hdata, 1); 212 aprint_error(": unable to map PMU data register\n"); 213 return; 214 } 215 tadpmu_init(iot, hcmd, hdata); 216 irq = bus_intr_establish(iot, sc->psc_intr[2], IPL_TTY, 217 tadpmu_intr, sc); 218 if (irq == NULL) { 219 aprint_error("failed to establish tadpmu interrupt\n"); 220 } 221 } 222 #endif 223 } 224 225 static void 226 pckbc_ebus_intr_establish(struct pckbc_softc *sc, pckbport_slot_t slot) 227 { 228 struct pckbc_ebus_softc *psc = (struct pckbc_ebus_softc *)sc; 229 void *res; 230 231 /* We assume that interrupt order is the same as slot order. */ 232 res = bus_intr_establish(sc->id->t_iot, psc->psc_intr[slot], 233 IPL_TTY, pckbcintr, sc); 234 if (res == NULL) 235 aprint_error_dev(sc->sc_dv, 236 "unable to establish %s slot interrupt\n", 237 pckbc_slot_names[slot]); 238 239 return; 240 } 241
Indexes created Sun Oct 26 13:09:57 GMT 2025