1 /* $NetBSD: amdgpu_psp.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Author: Huang Rui 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_psp.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $"); 30 31 #include <linux/firmware.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_ucode.h" 36 #include "soc15_common.h" 37 #include "psp_v3_1.h" 38 #include "psp_v10_0.h" 39 #include "psp_v11_0.h" 40 #include "psp_v12_0.h" 41 42 #include "amdgpu_ras.h" 43 44 static void psp_set_funcs(struct amdgpu_device *adev); 45 46 static int psp_early_init(void *handle) 47 { 48 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 49 struct psp_context *psp = &adev->psp; 50 51 psp_set_funcs(adev); 52 53 switch (adev->asic_type) { 54 case CHIP_VEGA10: 55 case CHIP_VEGA12: 56 psp_v3_1_set_psp_funcs(psp); 57 psp->autoload_supported = false; 58 break; 59 case CHIP_RAVEN: 60 psp_v10_0_set_psp_funcs(psp); 61 psp->autoload_supported = false; 62 break; 63 case CHIP_VEGA20: 64 case CHIP_ARCTURUS: 65 psp_v11_0_set_psp_funcs(psp); 66 psp->autoload_supported = false; 67 break; 68 case CHIP_NAVI10: 69 case CHIP_NAVI14: 70 case CHIP_NAVI12: 71 psp_v11_0_set_psp_funcs(psp); 72 psp->autoload_supported = true; 73 break; 74 case CHIP_RENOIR: 75 psp_v12_0_set_psp_funcs(psp); 76 break; 77 default: 78 return -EINVAL; 79 } 80 81 psp->adev = adev; 82 83 return 0; 84 } 85 86 static int psp_sw_init(void *handle) 87 { 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 struct psp_context *psp = &adev->psp; 90 int ret; 91 92 ret = psp_init_microcode(psp); 93 if (ret) { 94 DRM_ERROR("Failed to load psp firmware!\n"); 95 return ret; 96 } 97 98 ret = psp_mem_training_init(psp); 99 if (ret) { 100 DRM_ERROR("Failed to initialize memory training!\n"); 101 return ret; 102 } 103 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 104 if (ret) { 105 DRM_ERROR("Failed to process memory training!\n"); 106 return ret; 107 } 108 109 return 0; 110 } 111 112 static int psp_sw_fini(void *handle) 113 { 114 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 115 116 psp_mem_training_fini(&adev->psp); 117 release_firmware(adev->psp.sos_fw); 118 adev->psp.sos_fw = NULL; 119 release_firmware(adev->psp.asd_fw); 120 adev->psp.asd_fw = NULL; 121 if (adev->psp.ta_fw) { 122 release_firmware(adev->psp.ta_fw); 123 adev->psp.ta_fw = NULL; 124 } 125 return 0; 126 } 127 128 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 129 uint32_t reg_val, uint32_t mask, bool check_changed) 130 { 131 uint32_t val; 132 int i; 133 struct amdgpu_device *adev = psp->adev; 134 135 for (i = 0; i < adev->usec_timeout; i++) { 136 val = RREG32(reg_index); 137 if (check_changed) { 138 if (val != reg_val) 139 return 0; 140 } else { 141 if ((val & mask) == reg_val) 142 return 0; 143 } 144 udelay(1); 145 } 146 147 return -ETIME; 148 } 149 150 static int 151 psp_cmd_submit_buf(struct psp_context *psp, 152 struct amdgpu_firmware_info *ucode, 153 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 154 { 155 int ret; 156 int index; 157 int timeout = 2000; 158 159 mutex_lock(&psp->mutex); 160 161 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 162 163 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 164 165 index = atomic_inc_return(&psp->fence_value); 166 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 167 if (ret) { 168 atomic_dec(&psp->fence_value); 169 mutex_unlock(&psp->mutex); 170 return ret; 171 } 172 173 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 174 while (*((unsigned int *)psp->fence_buf) != index) { 175 if (--timeout == 0) 176 break; 177 /* 178 * Shouldn't wait for timeout when err_event_athub occurs, 179 * because gpu reset thread triggered and lock resource should 180 * be released for psp resume sequence. 181 */ 182 if (amdgpu_ras_intr_triggered()) 183 break; 184 msleep(1); 185 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 186 } 187 188 /* In some cases, psp response status is not 0 even there is no 189 * problem while the command is submitted. Some version of PSP FW 190 * doesn't write 0 to that field. 191 * So here we would like to only print a warning instead of an error 192 * during psp initialization to avoid breaking hw_init and it doesn't 193 * return -EINVAL. 194 */ 195 if (psp->cmd_buf_mem->resp.status || !timeout) { 196 if (ucode) 197 DRM_WARN("failed to load ucode id (%d) ", 198 ucode->ucode_id); 199 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 200 psp->cmd_buf_mem->cmd_id, 201 psp->cmd_buf_mem->resp.status); 202 if (!timeout) { 203 mutex_unlock(&psp->mutex); 204 return -EINVAL; 205 } 206 } 207 208 /* get xGMI session id from response buffer */ 209 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 210 211 if (ucode) { 212 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 213 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 214 } 215 mutex_unlock(&psp->mutex); 216 217 return ret; 218 } 219 220 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 221 struct psp_gfx_cmd_resp *cmd, 222 uint64_t tmr_mc, uint32_t size) 223 { 224 if (psp_support_vmr_ring(psp)) 225 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 226 else 227 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 228 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 229 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 230 cmd->cmd.cmd_setup_tmr.buf_size = size; 231 } 232 233 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 234 uint64_t pri_buf_mc, uint32_t size) 235 { 236 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 237 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 238 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 239 cmd->cmd.cmd_load_toc.toc_size = size; 240 } 241 242 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 243 static int psp_load_toc(struct psp_context *psp, 244 uint32_t *tmr_size) 245 { 246 int ret; 247 struct psp_gfx_cmd_resp *cmd; 248 249 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 250 if (!cmd) 251 return -ENOMEM; 252 /* Copy toc to psp firmware private buffer */ 253 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 254 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 255 256 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 257 258 ret = psp_cmd_submit_buf(psp, NULL, cmd, 259 psp->fence_buf_mc_addr); 260 if (!ret) 261 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 262 kfree(cmd); 263 return ret; 264 } 265 266 /* Set up Trusted Memory Region */ 267 static int psp_tmr_init(struct psp_context *psp) 268 { 269 int ret; 270 int tmr_size; 271 void *tmr_buf; 272 void **pptr; 273 274 /* 275 * According to HW engineer, they prefer the TMR address be "naturally 276 * aligned" , e.g. the start address be an integer divide of TMR size. 277 * 278 * Note: this memory need be reserved till the driver 279 * uninitializes. 280 */ 281 tmr_size = PSP_TMR_SIZE; 282 283 /* For ASICs support RLC autoload, psp will parse the toc 284 * and calculate the total size of TMR needed */ 285 if (!amdgpu_sriov_vf(psp->adev) && 286 psp->toc_start_addr && 287 psp->toc_bin_size && 288 psp->fw_pri_buf) { 289 ret = psp_load_toc(psp, &tmr_size); 290 if (ret) { 291 DRM_ERROR("Failed to load toc\n"); 292 return ret; 293 } 294 } 295 296 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 297 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 298 AMDGPU_GEM_DOMAIN_VRAM, 299 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 300 301 return ret; 302 } 303 304 static int psp_tmr_load(struct psp_context *psp) 305 { 306 int ret; 307 struct psp_gfx_cmd_resp *cmd; 308 309 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 310 if (!cmd) 311 return -ENOMEM; 312 313 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 314 amdgpu_bo_size(psp->tmr_bo)); 315 DRM_INFO("reserve 0x%lx from 0x%"PRIx64" for PSP TMR\n", 316 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 317 318 ret = psp_cmd_submit_buf(psp, NULL, cmd, 319 psp->fence_buf_mc_addr); 320 321 kfree(cmd); 322 323 return ret; 324 } 325 326 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 327 uint64_t asd_mc, uint32_t size) 328 { 329 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 330 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 331 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 332 cmd->cmd.cmd_load_ta.app_len = size; 333 334 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 335 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 336 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 337 } 338 339 static int psp_asd_load(struct psp_context *psp) 340 { 341 int ret; 342 struct psp_gfx_cmd_resp *cmd; 343 344 /* If PSP version doesn't match ASD version, asd loading will be failed. 345 * add workaround to bypass it for sriov now. 346 * TODO: add version check to make it common 347 */ 348 if (amdgpu_sriov_vf(psp->adev)) 349 return 0; 350 351 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 352 if (!cmd) 353 return -ENOMEM; 354 355 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 356 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 357 358 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 359 psp->asd_ucode_size); 360 361 ret = psp_cmd_submit_buf(psp, NULL, cmd, 362 psp->fence_buf_mc_addr); 363 if (!ret) { 364 psp->asd_context.asd_initialized = true; 365 psp->asd_context.session_id = cmd->resp.session_id; 366 } 367 368 kfree(cmd); 369 370 return ret; 371 } 372 373 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 374 uint32_t session_id) 375 { 376 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 377 cmd->cmd.cmd_unload_ta.session_id = session_id; 378 } 379 380 static int psp_asd_unload(struct psp_context *psp) 381 { 382 int ret; 383 struct psp_gfx_cmd_resp *cmd; 384 385 if (amdgpu_sriov_vf(psp->adev)) 386 return 0; 387 388 if (!psp->asd_context.asd_initialized) 389 return 0; 390 391 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 392 if (!cmd) 393 return -ENOMEM; 394 395 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 396 397 ret = psp_cmd_submit_buf(psp, NULL, cmd, 398 psp->fence_buf_mc_addr); 399 if (!ret) 400 psp->asd_context.asd_initialized = false; 401 402 kfree(cmd); 403 404 return ret; 405 } 406 407 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 408 uint32_t id, uint32_t value) 409 { 410 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 411 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 412 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 413 } 414 415 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 416 uint32_t value) 417 { 418 struct psp_gfx_cmd_resp *cmd = NULL; 419 int ret = 0; 420 421 if (reg >= PSP_REG_LAST) 422 return -EINVAL; 423 424 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 425 if (!cmd) 426 return -ENOMEM; 427 428 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 429 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 430 431 kfree(cmd); 432 return ret; 433 } 434 435 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 436 uint64_t ta_bin_mc, 437 uint32_t ta_bin_size, 438 uint64_t ta_shared_mc, 439 uint32_t ta_shared_size) 440 { 441 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 442 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 443 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 444 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 445 446 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 447 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 448 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 449 } 450 451 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 452 { 453 int ret; 454 455 /* 456 * Allocate 16k memory aligned to 4k from Frame Buffer (local 457 * physical) for xgmi ta <-> Driver 458 */ 459 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 460 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 461 &psp->xgmi_context.xgmi_shared_bo, 462 &psp->xgmi_context.xgmi_shared_mc_addr, 463 &psp->xgmi_context.xgmi_shared_buf); 464 465 return ret; 466 } 467 468 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 469 uint32_t ta_cmd_id, 470 uint32_t session_id) 471 { 472 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 473 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 474 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 475 } 476 477 int psp_ta_invoke(struct psp_context *psp, 478 uint32_t ta_cmd_id, 479 uint32_t session_id) 480 { 481 int ret; 482 struct psp_gfx_cmd_resp *cmd; 483 484 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 485 if (!cmd) 486 return -ENOMEM; 487 488 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 489 490 ret = psp_cmd_submit_buf(psp, NULL, cmd, 491 psp->fence_buf_mc_addr); 492 493 kfree(cmd); 494 495 return ret; 496 } 497 498 static int psp_xgmi_load(struct psp_context *psp) 499 { 500 int ret; 501 struct psp_gfx_cmd_resp *cmd; 502 503 /* 504 * TODO: bypass the loading in sriov for now 505 */ 506 507 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 508 if (!cmd) 509 return -ENOMEM; 510 511 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 512 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 513 514 psp_prep_ta_load_cmd_buf(cmd, 515 psp->fw_pri_mc_addr, 516 psp->ta_xgmi_ucode_size, 517 psp->xgmi_context.xgmi_shared_mc_addr, 518 PSP_XGMI_SHARED_MEM_SIZE); 519 520 ret = psp_cmd_submit_buf(psp, NULL, cmd, 521 psp->fence_buf_mc_addr); 522 523 if (!ret) { 524 psp->xgmi_context.initialized = 1; 525 psp->xgmi_context.session_id = cmd->resp.session_id; 526 } 527 528 kfree(cmd); 529 530 return ret; 531 } 532 533 static int psp_xgmi_unload(struct psp_context *psp) 534 { 535 int ret; 536 struct psp_gfx_cmd_resp *cmd; 537 struct amdgpu_device *adev = psp->adev; 538 539 /* XGMI TA unload currently is not supported on Arcturus */ 540 if (adev->asic_type == CHIP_ARCTURUS) 541 return 0; 542 543 /* 544 * TODO: bypass the unloading in sriov for now 545 */ 546 547 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 548 if (!cmd) 549 return -ENOMEM; 550 551 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 552 553 ret = psp_cmd_submit_buf(psp, NULL, cmd, 554 psp->fence_buf_mc_addr); 555 556 kfree(cmd); 557 558 return ret; 559 } 560 561 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 562 { 563 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 564 } 565 566 static int psp_xgmi_terminate(struct psp_context *psp) 567 { 568 int ret; 569 570 if (!psp->xgmi_context.initialized) 571 return 0; 572 573 ret = psp_xgmi_unload(psp); 574 if (ret) 575 return ret; 576 577 psp->xgmi_context.initialized = 0; 578 579 /* free xgmi shared memory */ 580 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 581 &psp->xgmi_context.xgmi_shared_mc_addr, 582 &psp->xgmi_context.xgmi_shared_buf); 583 584 return 0; 585 } 586 587 static int psp_xgmi_initialize(struct psp_context *psp) 588 { 589 struct ta_xgmi_shared_memory *xgmi_cmd; 590 int ret; 591 592 if (!psp->adev->psp.ta_fw || 593 !psp->adev->psp.ta_xgmi_ucode_size || 594 !psp->adev->psp.ta_xgmi_start_addr) 595 return -ENOENT; 596 597 if (!psp->xgmi_context.initialized) { 598 ret = psp_xgmi_init_shared_buf(psp); 599 if (ret) 600 return ret; 601 } 602 603 /* Load XGMI TA */ 604 ret = psp_xgmi_load(psp); 605 if (ret) 606 return ret; 607 608 /* Initialize XGMI session */ 609 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 610 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 611 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 612 613 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 614 615 return ret; 616 } 617 618 // ras begin 619 static int psp_ras_init_shared_buf(struct psp_context *psp) 620 { 621 int ret; 622 623 /* 624 * Allocate 16k memory aligned to 4k from Frame Buffer (local 625 * physical) for ras ta <-> Driver 626 */ 627 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 628 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 629 &psp->ras.ras_shared_bo, 630 &psp->ras.ras_shared_mc_addr, 631 &psp->ras.ras_shared_buf); 632 633 return ret; 634 } 635 636 static int psp_ras_load(struct psp_context *psp) 637 { 638 int ret; 639 struct psp_gfx_cmd_resp *cmd; 640 641 /* 642 * TODO: bypass the loading in sriov for now 643 */ 644 if (amdgpu_sriov_vf(psp->adev)) 645 return 0; 646 647 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 648 if (!cmd) 649 return -ENOMEM; 650 651 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 652 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 653 654 psp_prep_ta_load_cmd_buf(cmd, 655 psp->fw_pri_mc_addr, 656 psp->ta_ras_ucode_size, 657 psp->ras.ras_shared_mc_addr, 658 PSP_RAS_SHARED_MEM_SIZE); 659 660 ret = psp_cmd_submit_buf(psp, NULL, cmd, 661 psp->fence_buf_mc_addr); 662 663 if (!ret) { 664 psp->ras.ras_initialized = true; 665 psp->ras.session_id = cmd->resp.session_id; 666 } 667 668 kfree(cmd); 669 670 return ret; 671 } 672 673 static int psp_ras_unload(struct psp_context *psp) 674 { 675 int ret; 676 struct psp_gfx_cmd_resp *cmd; 677 678 /* 679 * TODO: bypass the unloading in sriov for now 680 */ 681 if (amdgpu_sriov_vf(psp->adev)) 682 return 0; 683 684 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 685 if (!cmd) 686 return -ENOMEM; 687 688 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 689 690 ret = psp_cmd_submit_buf(psp, NULL, cmd, 691 psp->fence_buf_mc_addr); 692 693 kfree(cmd); 694 695 return ret; 696 } 697 698 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 699 { 700 /* 701 * TODO: bypass the loading in sriov for now 702 */ 703 if (amdgpu_sriov_vf(psp->adev)) 704 return 0; 705 706 return psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 707 } 708 709 int psp_ras_enable_features(struct psp_context *psp, 710 union ta_ras_cmd_input *info, bool enable) 711 { 712 struct ta_ras_shared_memory *ras_cmd; 713 int ret; 714 715 if (!psp->ras.ras_initialized) 716 return -EINVAL; 717 718 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 719 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 720 721 if (enable) 722 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 723 else 724 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 725 726 ras_cmd->ras_in_message = *info; 727 728 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 729 if (ret) 730 return -EINVAL; 731 732 return ras_cmd->ras_status; 733 } 734 735 static int psp_ras_terminate(struct psp_context *psp) 736 { 737 int ret; 738 739 /* 740 * TODO: bypass the terminate in sriov for now 741 */ 742 if (amdgpu_sriov_vf(psp->adev)) 743 return 0; 744 745 if (!psp->ras.ras_initialized) 746 return 0; 747 748 ret = psp_ras_unload(psp); 749 if (ret) 750 return ret; 751 752 psp->ras.ras_initialized = false; 753 754 /* free ras shared memory */ 755 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 756 &psp->ras.ras_shared_mc_addr, 757 &psp->ras.ras_shared_buf); 758 759 return 0; 760 } 761 762 static int psp_ras_initialize(struct psp_context *psp) 763 { 764 int ret; 765 766 /* 767 * TODO: bypass the initialize in sriov for now 768 */ 769 if (amdgpu_sriov_vf(psp->adev)) 770 return 0; 771 772 if (!psp->adev->psp.ta_ras_ucode_size || 773 !psp->adev->psp.ta_ras_start_addr) { 774 dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n"); 775 return 0; 776 } 777 778 if (!psp->ras.ras_initialized) { 779 ret = psp_ras_init_shared_buf(psp); 780 if (ret) 781 return ret; 782 } 783 784 ret = psp_ras_load(psp); 785 if (ret) 786 return ret; 787 788 return 0; 789 } 790 // ras end 791 792 // HDCP start 793 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 794 { 795 int ret; 796 797 /* 798 * Allocate 16k memory aligned to 4k from Frame Buffer (local 799 * physical) for hdcp ta <-> Driver 800 */ 801 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 802 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 803 &psp->hdcp_context.hdcp_shared_bo, 804 &psp->hdcp_context.hdcp_shared_mc_addr, 805 &psp->hdcp_context.hdcp_shared_buf); 806 807 return ret; 808 } 809 810 static int psp_hdcp_load(struct psp_context *psp) 811 { 812 int ret; 813 struct psp_gfx_cmd_resp *cmd; 814 815 /* 816 * TODO: bypass the loading in sriov for now 817 */ 818 if (amdgpu_sriov_vf(psp->adev)) 819 return 0; 820 821 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 822 if (!cmd) 823 return -ENOMEM; 824 825 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 826 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 827 psp->ta_hdcp_ucode_size); 828 829 psp_prep_ta_load_cmd_buf(cmd, 830 psp->fw_pri_mc_addr, 831 psp->ta_hdcp_ucode_size, 832 psp->hdcp_context.hdcp_shared_mc_addr, 833 PSP_HDCP_SHARED_MEM_SIZE); 834 835 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 836 837 if (!ret) { 838 psp->hdcp_context.hdcp_initialized = true; 839 psp->hdcp_context.session_id = cmd->resp.session_id; 840 } 841 842 kfree(cmd); 843 844 return ret; 845 } 846 static int psp_hdcp_initialize(struct psp_context *psp) 847 { 848 int ret; 849 850 /* 851 * TODO: bypass the initialize in sriov for now 852 */ 853 if (amdgpu_sriov_vf(psp->adev)) 854 return 0; 855 856 if (!psp->adev->psp.ta_hdcp_ucode_size || 857 !psp->adev->psp.ta_hdcp_start_addr) { 858 dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n"); 859 return 0; 860 } 861 862 if (!psp->hdcp_context.hdcp_initialized) { 863 ret = psp_hdcp_init_shared_buf(psp); 864 if (ret) 865 return ret; 866 } 867 868 ret = psp_hdcp_load(psp); 869 if (ret) 870 return ret; 871 872 return 0; 873 } 874 875 static int psp_hdcp_unload(struct psp_context *psp) 876 { 877 int ret; 878 struct psp_gfx_cmd_resp *cmd; 879 880 /* 881 * TODO: bypass the unloading in sriov for now 882 */ 883 if (amdgpu_sriov_vf(psp->adev)) 884 return 0; 885 886 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 887 if (!cmd) 888 return -ENOMEM; 889 890 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 891 892 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 893 894 kfree(cmd); 895 896 return ret; 897 } 898 899 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 900 { 901 /* 902 * TODO: bypass the loading in sriov for now 903 */ 904 if (amdgpu_sriov_vf(psp->adev)) 905 return 0; 906 907 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 908 } 909 910 static int psp_hdcp_terminate(struct psp_context *psp) 911 { 912 int ret; 913 914 /* 915 * TODO: bypass the terminate in sriov for now 916 */ 917 if (amdgpu_sriov_vf(psp->adev)) 918 return 0; 919 920 if (!psp->hdcp_context.hdcp_initialized) 921 return 0; 922 923 ret = psp_hdcp_unload(psp); 924 if (ret) 925 return ret; 926 927 psp->hdcp_context.hdcp_initialized = false; 928 929 /* free hdcp shared memory */ 930 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 931 &psp->hdcp_context.hdcp_shared_mc_addr, 932 &psp->hdcp_context.hdcp_shared_buf); 933 934 return 0; 935 } 936 // HDCP end 937 938 // DTM start 939 static int psp_dtm_init_shared_buf(struct psp_context *psp) 940 { 941 int ret; 942 943 /* 944 * Allocate 16k memory aligned to 4k from Frame Buffer (local 945 * physical) for dtm ta <-> Driver 946 */ 947 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 948 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 949 &psp->dtm_context.dtm_shared_bo, 950 &psp->dtm_context.dtm_shared_mc_addr, 951 &psp->dtm_context.dtm_shared_buf); 952 953 return ret; 954 } 955 956 static int psp_dtm_load(struct psp_context *psp) 957 { 958 int ret; 959 struct psp_gfx_cmd_resp *cmd; 960 961 /* 962 * TODO: bypass the loading in sriov for now 963 */ 964 if (amdgpu_sriov_vf(psp->adev)) 965 return 0; 966 967 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 968 if (!cmd) 969 return -ENOMEM; 970 971 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 972 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 973 974 psp_prep_ta_load_cmd_buf(cmd, 975 psp->fw_pri_mc_addr, 976 psp->ta_dtm_ucode_size, 977 psp->dtm_context.dtm_shared_mc_addr, 978 PSP_DTM_SHARED_MEM_SIZE); 979 980 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 981 982 if (!ret) { 983 psp->dtm_context.dtm_initialized = true; 984 psp->dtm_context.session_id = cmd->resp.session_id; 985 } 986 987 kfree(cmd); 988 989 return ret; 990 } 991 992 static int psp_dtm_initialize(struct psp_context *psp) 993 { 994 int ret; 995 996 /* 997 * TODO: bypass the initialize in sriov for now 998 */ 999 if (amdgpu_sriov_vf(psp->adev)) 1000 return 0; 1001 1002 if (!psp->adev->psp.ta_dtm_ucode_size || 1003 !psp->adev->psp.ta_dtm_start_addr) { 1004 dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n"); 1005 return 0; 1006 } 1007 1008 if (!psp->dtm_context.dtm_initialized) { 1009 ret = psp_dtm_init_shared_buf(psp); 1010 if (ret) 1011 return ret; 1012 } 1013 1014 ret = psp_dtm_load(psp); 1015 if (ret) 1016 return ret; 1017 1018 return 0; 1019 } 1020 1021 static int psp_dtm_unload(struct psp_context *psp) 1022 { 1023 int ret; 1024 struct psp_gfx_cmd_resp *cmd; 1025 1026 /* 1027 * TODO: bypass the unloading in sriov for now 1028 */ 1029 if (amdgpu_sriov_vf(psp->adev)) 1030 return 0; 1031 1032 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1033 if (!cmd) 1034 return -ENOMEM; 1035 1036 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1037 1038 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1039 1040 kfree(cmd); 1041 1042 return ret; 1043 } 1044 1045 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1046 { 1047 /* 1048 * TODO: bypass the loading in sriov for now 1049 */ 1050 if (amdgpu_sriov_vf(psp->adev)) 1051 return 0; 1052 1053 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1054 } 1055 1056 static int psp_dtm_terminate(struct psp_context *psp) 1057 { 1058 int ret; 1059 1060 /* 1061 * TODO: bypass the terminate in sriov for now 1062 */ 1063 if (amdgpu_sriov_vf(psp->adev)) 1064 return 0; 1065 1066 if (!psp->dtm_context.dtm_initialized) 1067 return 0; 1068 1069 ret = psp_dtm_unload(psp); 1070 if (ret) 1071 return ret; 1072 1073 psp->dtm_context.dtm_initialized = false; 1074 1075 /* free hdcp shared memory */ 1076 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1077 &psp->dtm_context.dtm_shared_mc_addr, 1078 &psp->dtm_context.dtm_shared_buf); 1079 1080 return 0; 1081 } 1082 // DTM end 1083 1084 static int psp_hw_start(struct psp_context *psp) 1085 { 1086 struct amdgpu_device *adev = psp->adev; 1087 int ret; 1088 1089 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 1090 if (psp->kdb_bin_size && 1091 (psp->funcs->bootloader_load_kdb != NULL)) { 1092 ret = psp_bootloader_load_kdb(psp); 1093 if (ret) { 1094 DRM_ERROR("PSP load kdb failed!\n"); 1095 return ret; 1096 } 1097 } 1098 1099 ret = psp_bootloader_load_sysdrv(psp); 1100 if (ret) { 1101 DRM_ERROR("PSP load sysdrv failed!\n"); 1102 return ret; 1103 } 1104 1105 ret = psp_bootloader_load_sos(psp); 1106 if (ret) { 1107 DRM_ERROR("PSP load sos failed!\n"); 1108 return ret; 1109 } 1110 } 1111 1112 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1113 if (ret) { 1114 DRM_ERROR("PSP create ring failed!\n"); 1115 return ret; 1116 } 1117 1118 ret = psp_tmr_init(psp); 1119 if (ret) { 1120 DRM_ERROR("PSP tmr init failed!\n"); 1121 return ret; 1122 } 1123 1124 ret = psp_tmr_load(psp); 1125 if (ret) { 1126 DRM_ERROR("PSP load tmr failed!\n"); 1127 return ret; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1134 enum psp_gfx_fw_type *type) 1135 { 1136 switch (ucode->ucode_id) { 1137 case AMDGPU_UCODE_ID_SDMA0: 1138 *type = GFX_FW_TYPE_SDMA0; 1139 break; 1140 case AMDGPU_UCODE_ID_SDMA1: 1141 *type = GFX_FW_TYPE_SDMA1; 1142 break; 1143 case AMDGPU_UCODE_ID_SDMA2: 1144 *type = GFX_FW_TYPE_SDMA2; 1145 break; 1146 case AMDGPU_UCODE_ID_SDMA3: 1147 *type = GFX_FW_TYPE_SDMA3; 1148 break; 1149 case AMDGPU_UCODE_ID_SDMA4: 1150 *type = GFX_FW_TYPE_SDMA4; 1151 break; 1152 case AMDGPU_UCODE_ID_SDMA5: 1153 *type = GFX_FW_TYPE_SDMA5; 1154 break; 1155 case AMDGPU_UCODE_ID_SDMA6: 1156 *type = GFX_FW_TYPE_SDMA6; 1157 break; 1158 case AMDGPU_UCODE_ID_SDMA7: 1159 *type = GFX_FW_TYPE_SDMA7; 1160 break; 1161 case AMDGPU_UCODE_ID_CP_CE: 1162 *type = GFX_FW_TYPE_CP_CE; 1163 break; 1164 case AMDGPU_UCODE_ID_CP_PFP: 1165 *type = GFX_FW_TYPE_CP_PFP; 1166 break; 1167 case AMDGPU_UCODE_ID_CP_ME: 1168 *type = GFX_FW_TYPE_CP_ME; 1169 break; 1170 case AMDGPU_UCODE_ID_CP_MEC1: 1171 *type = GFX_FW_TYPE_CP_MEC; 1172 break; 1173 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1174 *type = GFX_FW_TYPE_CP_MEC_ME1; 1175 break; 1176 case AMDGPU_UCODE_ID_CP_MEC2: 1177 *type = GFX_FW_TYPE_CP_MEC; 1178 break; 1179 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1180 *type = GFX_FW_TYPE_CP_MEC_ME2; 1181 break; 1182 case AMDGPU_UCODE_ID_RLC_G: 1183 *type = GFX_FW_TYPE_RLC_G; 1184 break; 1185 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1186 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1187 break; 1188 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1189 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1190 break; 1191 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1192 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1193 break; 1194 case AMDGPU_UCODE_ID_SMC: 1195 *type = GFX_FW_TYPE_SMU; 1196 break; 1197 case AMDGPU_UCODE_ID_UVD: 1198 *type = GFX_FW_TYPE_UVD; 1199 break; 1200 case AMDGPU_UCODE_ID_UVD1: 1201 *type = GFX_FW_TYPE_UVD1; 1202 break; 1203 case AMDGPU_UCODE_ID_VCE: 1204 *type = GFX_FW_TYPE_VCE; 1205 break; 1206 case AMDGPU_UCODE_ID_VCN: 1207 *type = GFX_FW_TYPE_VCN; 1208 break; 1209 case AMDGPU_UCODE_ID_VCN1: 1210 *type = GFX_FW_TYPE_VCN1; 1211 break; 1212 case AMDGPU_UCODE_ID_DMCU_ERAM: 1213 *type = GFX_FW_TYPE_DMCU_ERAM; 1214 break; 1215 case AMDGPU_UCODE_ID_DMCU_INTV: 1216 *type = GFX_FW_TYPE_DMCU_ISR; 1217 break; 1218 case AMDGPU_UCODE_ID_VCN0_RAM: 1219 *type = GFX_FW_TYPE_VCN0_RAM; 1220 break; 1221 case AMDGPU_UCODE_ID_VCN1_RAM: 1222 *type = GFX_FW_TYPE_VCN1_RAM; 1223 break; 1224 case AMDGPU_UCODE_ID_DMCUB: 1225 *type = GFX_FW_TYPE_DMUB; 1226 break; 1227 case AMDGPU_UCODE_ID_MAXIMUM: 1228 default: 1229 return -EINVAL; 1230 } 1231 1232 return 0; 1233 } 1234 1235 static void psp_print_fw_hdr(struct psp_context *psp, 1236 struct amdgpu_firmware_info *ucode) 1237 { 1238 struct amdgpu_device *adev = psp->adev; 1239 struct common_firmware_header *hdr; 1240 1241 switch (ucode->ucode_id) { 1242 case AMDGPU_UCODE_ID_SDMA0: 1243 case AMDGPU_UCODE_ID_SDMA1: 1244 case AMDGPU_UCODE_ID_SDMA2: 1245 case AMDGPU_UCODE_ID_SDMA3: 1246 case AMDGPU_UCODE_ID_SDMA4: 1247 case AMDGPU_UCODE_ID_SDMA5: 1248 case AMDGPU_UCODE_ID_SDMA6: 1249 case AMDGPU_UCODE_ID_SDMA7: 1250 hdr = (struct common_firmware_header *) 1251 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1252 amdgpu_ucode_print_sdma_hdr(hdr); 1253 break; 1254 case AMDGPU_UCODE_ID_CP_CE: 1255 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1256 amdgpu_ucode_print_gfx_hdr(hdr); 1257 break; 1258 case AMDGPU_UCODE_ID_CP_PFP: 1259 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1260 amdgpu_ucode_print_gfx_hdr(hdr); 1261 break; 1262 case AMDGPU_UCODE_ID_CP_ME: 1263 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1264 amdgpu_ucode_print_gfx_hdr(hdr); 1265 break; 1266 case AMDGPU_UCODE_ID_CP_MEC1: 1267 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1268 amdgpu_ucode_print_gfx_hdr(hdr); 1269 break; 1270 case AMDGPU_UCODE_ID_RLC_G: 1271 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1272 amdgpu_ucode_print_rlc_hdr(hdr); 1273 break; 1274 case AMDGPU_UCODE_ID_SMC: 1275 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1276 amdgpu_ucode_print_smc_hdr(hdr); 1277 break; 1278 default: 1279 break; 1280 } 1281 } 1282 1283 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1284 struct psp_gfx_cmd_resp *cmd) 1285 { 1286 int ret; 1287 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1288 1289 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1290 1291 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1292 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1293 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1294 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1295 1296 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1297 if (ret) 1298 DRM_ERROR("Unknown firmware type\n"); 1299 1300 return ret; 1301 } 1302 1303 static int psp_execute_np_fw_load(struct psp_context *psp, 1304 struct amdgpu_firmware_info *ucode) 1305 { 1306 int ret = 0; 1307 1308 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1309 if (ret) 1310 return ret; 1311 1312 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1313 psp->fence_buf_mc_addr); 1314 1315 return ret; 1316 } 1317 1318 static int psp_np_fw_load(struct psp_context *psp) 1319 { 1320 int i, ret; 1321 struct amdgpu_firmware_info *ucode; 1322 struct amdgpu_device* adev = psp->adev; 1323 1324 if (psp->autoload_supported) { 1325 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1326 if (!ucode->fw) 1327 goto out; 1328 1329 ret = psp_execute_np_fw_load(psp, ucode); 1330 if (ret) 1331 return ret; 1332 } 1333 1334 out: 1335 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1336 ucode = &adev->firmware.ucode[i]; 1337 if (!ucode->fw) 1338 continue; 1339 1340 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1341 (psp_smu_reload_quirk(psp) || psp->autoload_supported)) 1342 continue; 1343 1344 if (amdgpu_sriov_vf(adev) && 1345 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1346 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1347 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1348 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1349 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1350 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1351 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1352 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1353 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1354 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1355 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1356 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1357 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 1358 /*skip ucode loading in SRIOV VF */ 1359 continue; 1360 1361 if (psp->autoload_supported && 1362 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1363 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1364 /* skip mec JT when autoload is enabled */ 1365 continue; 1366 1367 psp_print_fw_hdr(psp, ucode); 1368 1369 ret = psp_execute_np_fw_load(psp, ucode); 1370 if (ret) 1371 return ret; 1372 1373 /* Start rlc autoload after psp recieved all the gfx firmware */ 1374 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 1375 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 1376 ret = psp_rlc_autoload(psp); 1377 if (ret) { 1378 DRM_ERROR("Failed to start rlc autoload\n"); 1379 return ret; 1380 } 1381 } 1382 #if 0 1383 /* check if firmware loaded sucessfully */ 1384 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 1385 return -EINVAL; 1386 #endif 1387 } 1388 1389 return 0; 1390 } 1391 1392 static int psp_load_fw(struct amdgpu_device *adev) 1393 { 1394 int ret; 1395 struct psp_context *psp = &adev->psp; 1396 1397 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1398 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1399 goto skip_memalloc; 1400 } 1401 1402 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1403 if (!psp->cmd) 1404 return -ENOMEM; 1405 1406 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1407 AMDGPU_GEM_DOMAIN_GTT, 1408 &psp->fw_pri_bo, 1409 &psp->fw_pri_mc_addr, 1410 &psp->fw_pri_buf); 1411 if (ret) 1412 goto failed; 1413 1414 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1415 AMDGPU_GEM_DOMAIN_VRAM, 1416 &psp->fence_buf_bo, 1417 &psp->fence_buf_mc_addr, 1418 &psp->fence_buf); 1419 if (ret) 1420 goto failed; 1421 1422 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1423 AMDGPU_GEM_DOMAIN_VRAM, 1424 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1425 (void **)&psp->cmd_buf_mem); 1426 if (ret) 1427 goto failed; 1428 1429 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1430 1431 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1432 if (ret) { 1433 DRM_ERROR("PSP ring init failed!\n"); 1434 goto failed; 1435 } 1436 1437 skip_memalloc: 1438 ret = psp_hw_start(psp); 1439 if (ret) 1440 goto failed; 1441 1442 ret = psp_np_fw_load(psp); 1443 if (ret) 1444 goto failed; 1445 1446 ret = psp_asd_load(psp); 1447 if (ret) { 1448 DRM_ERROR("PSP load asd failed!\n"); 1449 return ret; 1450 } 1451 1452 if (adev->gmc.xgmi.num_physical_nodes > 1) { 1453 ret = psp_xgmi_initialize(psp); 1454 /* Warning the XGMI seesion initialize failure 1455 * Instead of stop driver initialization 1456 */ 1457 if (ret) 1458 dev_err(psp->adev->dev, 1459 "XGMI: Failed to initialize XGMI session\n"); 1460 } 1461 1462 if (psp->adev->psp.ta_fw) { 1463 ret = psp_ras_initialize(psp); 1464 if (ret) 1465 dev_err(psp->adev->dev, 1466 "RAS: Failed to initialize RAS\n"); 1467 1468 ret = psp_hdcp_initialize(psp); 1469 if (ret) 1470 dev_err(psp->adev->dev, 1471 "HDCP: Failed to initialize HDCP\n"); 1472 1473 ret = psp_dtm_initialize(psp); 1474 if (ret) 1475 dev_err(psp->adev->dev, 1476 "DTM: Failed to initialize DTM\n"); 1477 } 1478 1479 return 0; 1480 1481 failed: 1482 /* 1483 * all cleanup jobs (xgmi terminate, ras terminate, 1484 * ring destroy, cmd/fence/fw buffers destory, 1485 * psp->cmd destory) are delayed to psp_hw_fini 1486 */ 1487 return ret; 1488 } 1489 1490 static int psp_hw_init(void *handle) 1491 { 1492 int ret; 1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1494 1495 mutex_lock(&adev->firmware.mutex); 1496 /* 1497 * This sequence is just used on hw_init only once, no need on 1498 * resume. 1499 */ 1500 ret = amdgpu_ucode_init_bo(adev); 1501 if (ret) 1502 goto failed; 1503 1504 ret = psp_load_fw(adev); 1505 if (ret) { 1506 DRM_ERROR("PSP firmware loading failed\n"); 1507 goto failed; 1508 } 1509 1510 mutex_unlock(&adev->firmware.mutex); 1511 return 0; 1512 1513 failed: 1514 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1515 mutex_unlock(&adev->firmware.mutex); 1516 return -EINVAL; 1517 } 1518 1519 static int psp_hw_fini(void *handle) 1520 { 1521 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1522 struct psp_context *psp = &adev->psp; 1523 void *tmr_buf; 1524 void **pptr; 1525 1526 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1527 psp->xgmi_context.initialized == 1) 1528 psp_xgmi_terminate(psp); 1529 1530 if (psp->adev->psp.ta_fw) { 1531 psp_ras_terminate(psp); 1532 psp_dtm_terminate(psp); 1533 psp_hdcp_terminate(psp); 1534 } 1535 1536 psp_asd_unload(psp); 1537 1538 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1539 1540 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 1541 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 1542 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1543 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1544 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1545 &psp->fence_buf_mc_addr, &psp->fence_buf); 1546 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1547 (void **)&psp->cmd_buf_mem); 1548 1549 kfree(psp->cmd); 1550 psp->cmd = NULL; 1551 1552 return 0; 1553 } 1554 1555 static int psp_suspend(void *handle) 1556 { 1557 int ret; 1558 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1559 struct psp_context *psp = &adev->psp; 1560 1561 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1562 psp->xgmi_context.initialized == 1) { 1563 ret = psp_xgmi_terminate(psp); 1564 if (ret) { 1565 DRM_ERROR("Failed to terminate xgmi ta\n"); 1566 return ret; 1567 } 1568 } 1569 1570 if (psp->adev->psp.ta_fw) { 1571 ret = psp_ras_terminate(psp); 1572 if (ret) { 1573 DRM_ERROR("Failed to terminate ras ta\n"); 1574 return ret; 1575 } 1576 ret = psp_hdcp_terminate(psp); 1577 if (ret) { 1578 DRM_ERROR("Failed to terminate hdcp ta\n"); 1579 return ret; 1580 } 1581 ret = psp_dtm_terminate(psp); 1582 if (ret) { 1583 DRM_ERROR("Failed to terminate dtm ta\n"); 1584 return ret; 1585 } 1586 } 1587 1588 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1589 if (ret) { 1590 DRM_ERROR("PSP ring stop failed\n"); 1591 return ret; 1592 } 1593 1594 return 0; 1595 } 1596 1597 static int psp_resume(void *handle) 1598 { 1599 int ret; 1600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1601 struct psp_context *psp = &adev->psp; 1602 1603 DRM_INFO("PSP is resuming...\n"); 1604 1605 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 1606 if (ret) { 1607 DRM_ERROR("Failed to process memory training!\n"); 1608 return ret; 1609 } 1610 1611 mutex_lock(&adev->firmware.mutex); 1612 1613 ret = psp_hw_start(psp); 1614 if (ret) 1615 goto failed; 1616 1617 ret = psp_np_fw_load(psp); 1618 if (ret) 1619 goto failed; 1620 1621 ret = psp_asd_load(psp); 1622 if (ret) { 1623 DRM_ERROR("PSP load asd failed!\n"); 1624 goto failed; 1625 } 1626 1627 if (adev->gmc.xgmi.num_physical_nodes > 1) { 1628 ret = psp_xgmi_initialize(psp); 1629 /* Warning the XGMI seesion initialize failure 1630 * Instead of stop driver initialization 1631 */ 1632 if (ret) 1633 dev_err(psp->adev->dev, 1634 "XGMI: Failed to initialize XGMI session\n"); 1635 } 1636 1637 if (psp->adev->psp.ta_fw) { 1638 ret = psp_ras_initialize(psp); 1639 if (ret) 1640 dev_err(psp->adev->dev, 1641 "RAS: Failed to initialize RAS\n"); 1642 1643 ret = psp_hdcp_initialize(psp); 1644 if (ret) 1645 dev_err(psp->adev->dev, 1646 "HDCP: Failed to initialize HDCP\n"); 1647 1648 ret = psp_dtm_initialize(psp); 1649 if (ret) 1650 dev_err(psp->adev->dev, 1651 "DTM: Failed to initialize DTM\n"); 1652 } 1653 1654 mutex_unlock(&adev->firmware.mutex); 1655 1656 return 0; 1657 1658 failed: 1659 DRM_ERROR("PSP resume failed\n"); 1660 mutex_unlock(&adev->firmware.mutex); 1661 return ret; 1662 } 1663 1664 int psp_gpu_reset(struct amdgpu_device *adev) 1665 { 1666 int ret; 1667 1668 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1669 return 0; 1670 1671 mutex_lock(&adev->psp.mutex); 1672 ret = psp_mode1_reset(&adev->psp); 1673 mutex_unlock(&adev->psp.mutex); 1674 1675 return ret; 1676 } 1677 1678 int psp_rlc_autoload_start(struct psp_context *psp) 1679 { 1680 int ret; 1681 struct psp_gfx_cmd_resp *cmd; 1682 1683 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1684 if (!cmd) 1685 return -ENOMEM; 1686 1687 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1688 1689 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1690 psp->fence_buf_mc_addr); 1691 kfree(cmd); 1692 return ret; 1693 } 1694 1695 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1696 uint64_t cmd_gpu_addr, int cmd_size) 1697 { 1698 struct amdgpu_firmware_info ucode = {0}; 1699 1700 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1701 AMDGPU_UCODE_ID_VCN0_RAM; 1702 ucode.mc_addr = cmd_gpu_addr; 1703 ucode.ucode_size = cmd_size; 1704 1705 return psp_execute_np_fw_load(&adev->psp, &ucode); 1706 } 1707 1708 int psp_ring_cmd_submit(struct psp_context *psp, 1709 uint64_t cmd_buf_mc_addr, 1710 uint64_t fence_mc_addr, 1711 int index) 1712 { 1713 unsigned int psp_write_ptr_reg = 0; 1714 struct psp_gfx_rb_frame *write_frame; 1715 struct psp_ring *ring = &psp->km_ring; 1716 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 1717 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 1718 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 1719 struct amdgpu_device *adev = psp->adev; 1720 uint32_t ring_size_dw = ring->ring_size / 4; 1721 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 1722 1723 /* KM (GPCOM) prepare write pointer */ 1724 psp_write_ptr_reg = psp_ring_get_wptr(psp); 1725 1726 /* Update KM RB frame pointer to new frame */ 1727 /* write_frame ptr increments by size of rb_frame in bytes */ 1728 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 1729 if ((psp_write_ptr_reg % ring_size_dw) == 0) 1730 write_frame = ring_buffer_start; 1731 else 1732 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 1733 /* Check invalid write_frame ptr address */ 1734 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 1735 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 1736 ring_buffer_start, ring_buffer_end, write_frame); 1737 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 1738 return -EINVAL; 1739 } 1740 1741 /* Initialize KM RB frame */ 1742 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 1743 1744 /* Update KM RB frame */ 1745 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 1746 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 1747 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 1748 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 1749 write_frame->fence_value = index; 1750 amdgpu_asic_flush_hdp(adev, NULL); 1751 1752 /* Update the write Pointer in DWORDs */ 1753 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 1754 psp_ring_set_wptr(psp, psp_write_ptr_reg); 1755 return 0; 1756 } 1757 1758 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 1759 enum AMDGPU_UCODE_ID ucode_type) 1760 { 1761 struct amdgpu_firmware_info *ucode = NULL; 1762 1763 if (!adev->firmware.fw_size) 1764 return false; 1765 1766 ucode = &adev->firmware.ucode[ucode_type]; 1767 if (!ucode->fw || !ucode->ucode_size) 1768 return false; 1769 1770 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 1771 } 1772 1773 static int psp_set_clockgating_state(void *handle, 1774 enum amd_clockgating_state state) 1775 { 1776 return 0; 1777 } 1778 1779 static int psp_set_powergating_state(void *handle, 1780 enum amd_powergating_state state) 1781 { 1782 return 0; 1783 } 1784 1785 const struct amd_ip_funcs psp_ip_funcs = { 1786 .name = "psp", 1787 .early_init = psp_early_init, 1788 .late_init = NULL, 1789 .sw_init = psp_sw_init, 1790 .sw_fini = psp_sw_fini, 1791 .hw_init = psp_hw_init, 1792 .hw_fini = psp_hw_fini, 1793 .suspend = psp_suspend, 1794 .resume = psp_resume, 1795 .is_idle = NULL, 1796 .check_soft_reset = NULL, 1797 .wait_for_idle = NULL, 1798 .soft_reset = NULL, 1799 .set_clockgating_state = psp_set_clockgating_state, 1800 .set_powergating_state = psp_set_powergating_state, 1801 }; 1802 1803 static const struct amdgpu_psp_funcs psp_funcs = { 1804 .check_fw_loading_status = psp_check_fw_loading_status, 1805 }; 1806 1807 static void psp_set_funcs(struct amdgpu_device *adev) 1808 { 1809 if (NULL == adev->firmware.funcs) 1810 adev->firmware.funcs = &psp_funcs; 1811 } 1812 1813 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 1814 { 1815 .type = AMD_IP_BLOCK_TYPE_PSP, 1816 .major = 3, 1817 .minor = 1, 1818 .rev = 0, 1819 .funcs = &psp_ip_funcs, 1820 }; 1821 1822 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 1823 { 1824 .type = AMD_IP_BLOCK_TYPE_PSP, 1825 .major = 10, 1826 .minor = 0, 1827 .rev = 0, 1828 .funcs = &psp_ip_funcs, 1829 }; 1830 1831 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 1832 { 1833 .type = AMD_IP_BLOCK_TYPE_PSP, 1834 .major = 11, 1835 .minor = 0, 1836 .rev = 0, 1837 .funcs = &psp_ip_funcs, 1838 }; 1839 1840 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 1841 { 1842 .type = AMD_IP_BLOCK_TYPE_PSP, 1843 .major = 12, 1844 .minor = 0, 1845 .rev = 0, 1846 .funcs = &psp_ip_funcs, 1847 }; 1848
Indexes created Sun Sep 21 20:09:37 GMT 2025