HomeSort by: relevance | last modified time | path
    Searched defs:rate_parent (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/arm/nxp/
imx6_ccm.c 159 const u_int rate_parent)
162 uint64_t freq = rate_parent;
175 const u_int rate_parent)
178 uint64_t freq = rate_parent;
193 struct imx6_clk *iclk, const u_int rate_parent)
196 uint64_t freq = rate_parent;
214 struct imx6_clk *iclk, const u_int rate_parent)
234 uint64_t rate_parent = imxccm_clk_get_rate(sc, &parent->base); local in function:imxccm_clk_get_rate_fixed_factor
236 return rate_parent * fixed_factor->mult / fixed_factor->div;
250 uint64_t rate_parent = imxccm_clk_get_rate(sc, &parent->base) local in function:imxccm_clk_get_rate_pll
314 uint64_t rate_parent = imxccm_clk_get_rate(sc, &parent->base); local in function:imxccm_clk_get_rate_pfd
424 u_int rate_parent = imxccm_clk_get_rate(sc, &parent->base); local in function:imxccm_clk_set_rate_div
    [all...]
  /src/sys/arch/arm/nvidia/
tegra124_car.c 1033 const u_int rate_parent = tegra124_car_clock_get_rate(sc, local in function:tegra124_car_clock_get_rate_pll
1045 rate = (uint64_t)rate_parent * divn;
1062 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent); local in function:tegra124_car_clock_set_rate_pll
1063 if (rate_parent == 0)
1068 const u_int divn = rate / rate_parent;
1109 const u_int divn = (rate << pldiv) / rate_parent;
tegra210_car.c 1155 const u_int rate_parent = tegra210_car_clock_get_rate(sc, local in function:tegra210_car_clock_get_rate_pll
1173 rate = (uint64_t)rate_parent * divn;
1190 const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent); local in function:tegra210_car_clock_set_rate_pll
1191 if (rate_parent == 0)
1196 const u_int divn = rate / rate_parent;
1237 const u_int divn = (rate << pldiv) / rate_parent;
  /src/sys/arch/arm/samsung/
exynos5410_clock.c 586 const u_int rate_parent = exynos5410_clock_get_rate(sc, local in function:exynos5410_clock_get_rate_pll
591 return PLL_FREQ(rate_parent, v);
exynos5422_clock.c 763 const u_int rate_parent = exynos5422_clock_get_rate(sc, local in function:exynos5422_clock_get_rate_pll
768 return PLL_FREQ(rate_parent, v);

Completed in 31 milliseconds