| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_sumo_smc.c | 172 u32 regoffset = 0; local in function:sumo_set_tdp_limit
179 regoffset = RCU_SclkDpmTdpLimit01;
183 regoffset = RCU_SclkDpmTdpLimit01;
187 regoffset = RCU_SclkDpmTdpLimit23;
191 regoffset = RCU_SclkDpmTdpLimit23;
195 regoffset = RCU_SclkDpmTdpLimit47;
199 regoffset = RCU_SclkDpmTdpLimit47;
206 sclk_dpm_tdp_limit = RREG32_RCU(regoffset);
209 WREG32_RCU(regoffset, sclk_dpm_tdp_limit);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_dac.c | 246 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); local in function:nv17_dac_sample_load
264 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
265 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
271 if (regoffset == 0x68) {
285 saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
302 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput);
305 temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
306 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, temp | 1);
315 sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
317 sample &= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
[all...] |
| nouveau_dispnv04_tvnv17.c | 55 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); local in function:nv42_tv_sample_load
66 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
76 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
95 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
97 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
100 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
109 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
115 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
122 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
123 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl)
[all...] |
| /src/sys/external/isc/atheros_hal/dist/ar5212/ |
| ar2316.c | 519 uint32_t reg32, regoffset; local in function:ar2316SetPowerTable
592 regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
598 OS_REG_WRITE(ah, regoffset, reg32);
599 regoffset += 4;
|
| ar2317.c | 497 uint32_t reg32, regoffset; local in function:ar2317SetPowerTable
570 regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
576 OS_REG_WRITE(ah, regoffset, reg32);
577 regoffset += 4;
|
| ar2413.c | 513 uint32_t reg32, regoffset; local in function:ar2413SetPowerTable
586 regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
592 OS_REG_WRITE(ah, regoffset, reg32);
593 regoffset += 4;
|
| ar2425.c | 513 uint32_t i, reg32, regoffset; local in function:ar2425SetPowerTable
548 regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
554 OS_REG_WRITE(ah, regoffset, reg32);
555 regoffset += 4;
|
| ar5413.c | 549 uint32_t reg32, regoffset; local in function:ar5413SetPowerTable
622 regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
628 OS_REG_WRITE(ah, regoffset, reg32);
629 regoffset += 4;
|
