1 /* $NetBSD: savage_bci.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* savage_bci.c -- BCI support for Savage 4 * 5 * Copyright 2004 Felix Kuehling 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sub license, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 24 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: savage_bci.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $"); 30 31 #include <linux/delay.h> 32 #include <linux/pci.h> 33 #include <linux/slab.h> 34 #include <linux/uaccess.h> 35 36 #include <drm/drm_device.h> 37 #include <drm/drm_file.h> 38 #include <drm/drm_print.h> 39 #include <drm/savage_drm.h> 40 41 #include "savage_drv.h" 42 43 /* Need a long timeout for shadow status updates can take a while 44 * and so can waiting for events when the queue is full. */ 45 #define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ 46 #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ 47 #define SAVAGE_FREELIST_DEBUG 0 48 49 static int savage_do_cleanup_bci(struct drm_device *dev); 50 51 static int 52 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) 53 { 54 uint32_t mask = dev_priv->status_used_mask; 55 uint32_t threshold = dev_priv->bci_threshold_hi; 56 uint32_t status; 57 int i; 58 59 #if SAVAGE_BCI_DEBUG 60 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) 61 DRM_ERROR("Trying to emit %d words " 62 "(more than guaranteed space in COB)\n", n); 63 #endif 64 65 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 66 mb(); 67 status = dev_priv->status_ptr[0]; 68 if ((status & mask) < threshold) 69 return 0; 70 udelay(1); 71 } 72 73 #if SAVAGE_BCI_DEBUG 74 DRM_ERROR("failed!\n"); 75 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); 76 #endif 77 return -EBUSY; 78 } 79 80 static int 81 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) 82 { 83 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 84 uint32_t status; 85 int i; 86 87 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 88 status = SAVAGE_READ(SAVAGE_STATUS_WORD0); 89 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed) 90 return 0; 91 udelay(1); 92 } 93 94 #if SAVAGE_BCI_DEBUG 95 DRM_ERROR("failed!\n"); 96 DRM_INFO(" status=0x%08x\n", status); 97 #endif 98 return -EBUSY; 99 } 100 101 static int 102 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) 103 { 104 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 105 uint32_t status; 106 int i; 107 108 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 109 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0); 110 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed) 111 return 0; 112 udelay(1); 113 } 114 115 #if SAVAGE_BCI_DEBUG 116 DRM_ERROR("failed!\n"); 117 DRM_INFO(" status=0x%08x\n", status); 118 #endif 119 return -EBUSY; 120 } 121 122 /* 123 * Waiting for events. 124 * 125 * The BIOSresets the event tag to 0 on mode changes. Therefore we 126 * never emit 0 to the event tag. If we find a 0 event tag we know the 127 * BIOS stomped on it and return success assuming that the BIOS waited 128 * for engine idle. 129 * 130 * Note: if the Xserver uses the event tag it has to follow the same 131 * rule. Otherwise there may be glitches every 2^16 events. 132 */ 133 static int 134 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) 135 { 136 uint32_t status; 137 int i; 138 139 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 140 mb(); 141 status = dev_priv->status_ptr[1]; 142 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 143 (status & 0xffff) == 0) 144 return 0; 145 udelay(1); 146 } 147 148 #if SAVAGE_BCI_DEBUG 149 DRM_ERROR("failed!\n"); 150 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 151 #endif 152 153 return -EBUSY; 154 } 155 156 static int 157 savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e) 158 { 159 uint32_t status; 160 int i; 161 162 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 163 status = SAVAGE_READ(SAVAGE_STATUS_WORD1); 164 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 165 (status & 0xffff) == 0) 166 return 0; 167 udelay(1); 168 } 169 170 #if SAVAGE_BCI_DEBUG 171 DRM_ERROR("failed!\n"); 172 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 173 #endif 174 175 return -EBUSY; 176 } 177 178 uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 179 unsigned int flags) 180 { 181 uint16_t count; 182 BCI_LOCALS; 183 184 if (dev_priv->status_ptr) { 185 /* coordinate with Xserver */ 186 count = dev_priv->status_ptr[1023]; 187 if (count < dev_priv->event_counter) 188 dev_priv->event_wrap++; 189 } else { 190 count = dev_priv->event_counter; 191 } 192 count = (count + 1) & 0xffff; 193 if (count == 0) { 194 count++; /* See the comment above savage_wait_event_*. */ 195 dev_priv->event_wrap++; 196 } 197 dev_priv->event_counter = count; 198 if (dev_priv->status_ptr) 199 dev_priv->status_ptr[1023] = (uint32_t) count; 200 201 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { 202 unsigned int wait_cmd = BCI_CMD_WAIT; 203 if ((flags & SAVAGE_WAIT_2D)) 204 wait_cmd |= BCI_CMD_WAIT_2D; 205 if ((flags & SAVAGE_WAIT_3D)) 206 wait_cmd |= BCI_CMD_WAIT_3D; 207 BEGIN_BCI(2); 208 BCI_WRITE(wait_cmd); 209 } else { 210 BEGIN_BCI(1); 211 } 212 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count); 213 214 return count; 215 } 216 217 /* 218 * Freelist management 219 */ 220 static int savage_freelist_init(struct drm_device * dev) 221 { 222 drm_savage_private_t *dev_priv = dev->dev_private; 223 struct drm_device_dma *dma = dev->dma; 224 struct drm_buf *buf; 225 drm_savage_buf_priv_t *entry; 226 int i; 227 DRM_DEBUG("count=%d\n", dma->buf_count); 228 229 dev_priv->head.next = &dev_priv->tail; 230 dev_priv->head.prev = NULL; 231 dev_priv->head.buf = NULL; 232 233 dev_priv->tail.next = NULL; 234 dev_priv->tail.prev = &dev_priv->head; 235 dev_priv->tail.buf = NULL; 236 237 for (i = 0; i < dma->buf_count; i++) { 238 buf = dma->buflist[i]; 239 entry = buf->dev_private; 240 241 SET_AGE(&entry->age, 0, 0); 242 entry->buf = buf; 243 244 entry->next = dev_priv->head.next; 245 entry->prev = &dev_priv->head; 246 dev_priv->head.next->prev = entry; 247 dev_priv->head.next = entry; 248 } 249 250 return 0; 251 } 252 253 static struct drm_buf *savage_freelist_get(struct drm_device * dev) 254 { 255 drm_savage_private_t *dev_priv = dev->dev_private; 256 drm_savage_buf_priv_t *tail = dev_priv->tail.prev; 257 uint16_t event; 258 unsigned int wrap; 259 DRM_DEBUG("\n"); 260 261 UPDATE_EVENT_COUNTER(); 262 if (dev_priv->status_ptr) 263 event = dev_priv->status_ptr[1] & 0xffff; 264 else 265 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 266 wrap = dev_priv->event_wrap; 267 if (event > dev_priv->event_counter) 268 wrap--; /* hardware hasn't passed the last wrap yet */ 269 270 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); 271 DRM_DEBUG(" head=0x%04x %d\n", event, wrap); 272 273 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) { 274 drm_savage_buf_priv_t *next = tail->next; 275 drm_savage_buf_priv_t *prev = tail->prev; 276 prev->next = next; 277 next->prev = prev; 278 tail->next = tail->prev = NULL; 279 return tail->buf; 280 } 281 282 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf); 283 return NULL; 284 } 285 286 void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf) 287 { 288 drm_savage_private_t *dev_priv = dev->dev_private; 289 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; 290 291 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap); 292 293 if (entry->next != NULL || entry->prev != NULL) { 294 DRM_ERROR("entry already on freelist.\n"); 295 return; 296 } 297 298 prev = &dev_priv->head; 299 next = prev->next; 300 prev->next = entry; 301 next->prev = entry; 302 entry->prev = prev; 303 entry->next = next; 304 } 305 306 /* 307 * Command DMA 308 */ 309 static int savage_dma_init(drm_savage_private_t * dev_priv) 310 { 311 unsigned int i; 312 313 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / 314 (SAVAGE_DMA_PAGE_SIZE * 4); 315 dev_priv->dma_pages = kmalloc_array(dev_priv->nr_dma_pages, 316 sizeof(drm_savage_dma_page_t), 317 GFP_KERNEL); 318 if (dev_priv->dma_pages == NULL) 319 return -ENOMEM; 320 321 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 322 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); 323 dev_priv->dma_pages[i].used = 0; 324 dev_priv->dma_pages[i].flushed = 0; 325 } 326 SET_AGE(&dev_priv->last_dma_age, 0, 0); 327 328 dev_priv->first_dma_page = 0; 329 dev_priv->current_dma_page = 0; 330 331 return 0; 332 } 333 334 void savage_dma_reset(drm_savage_private_t * dev_priv) 335 { 336 uint16_t event; 337 unsigned int wrap, i; 338 event = savage_bci_emit_event(dev_priv, 0); 339 wrap = dev_priv->event_wrap; 340 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 341 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 342 dev_priv->dma_pages[i].used = 0; 343 dev_priv->dma_pages[i].flushed = 0; 344 } 345 SET_AGE(&dev_priv->last_dma_age, event, wrap); 346 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 347 } 348 349 void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page) 350 { 351 uint16_t event; 352 unsigned int wrap; 353 354 /* Faked DMA buffer pages don't age. */ 355 if (dev_priv->cmd_dma == &dev_priv->fake_dma) 356 return; 357 358 UPDATE_EVENT_COUNTER(); 359 if (dev_priv->status_ptr) 360 event = dev_priv->status_ptr[1] & 0xffff; 361 else 362 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 363 wrap = dev_priv->event_wrap; 364 if (event > dev_priv->event_counter) 365 wrap--; /* hardware hasn't passed the last wrap yet */ 366 367 if (dev_priv->dma_pages[page].age.wrap > wrap || 368 (dev_priv->dma_pages[page].age.wrap == wrap && 369 dev_priv->dma_pages[page].age.event > event)) { 370 if (dev_priv->wait_evnt(dev_priv, 371 dev_priv->dma_pages[page].age.event) 372 < 0) 373 DRM_ERROR("wait_evnt failed!\n"); 374 } 375 } 376 377 uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n) 378 { 379 unsigned int cur = dev_priv->current_dma_page; 380 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - 381 dev_priv->dma_pages[cur].used; 382 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) / 383 SAVAGE_DMA_PAGE_SIZE; 384 uint32_t *dma_ptr; 385 unsigned int i; 386 387 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n", 388 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); 389 390 if (cur + nr_pages < dev_priv->nr_dma_pages) { 391 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 392 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 393 if (n < rest) 394 rest = n; 395 dev_priv->dma_pages[cur].used += rest; 396 n -= rest; 397 cur++; 398 } else { 399 dev_priv->dma_flush(dev_priv); 400 nr_pages = 401 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE; 402 for (i = cur; i < dev_priv->nr_dma_pages; ++i) { 403 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; 404 dev_priv->dma_pages[i].used = 0; 405 dev_priv->dma_pages[i].flushed = 0; 406 } 407 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle; 408 dev_priv->first_dma_page = cur = 0; 409 } 410 for (i = cur; nr_pages > 0; ++i, --nr_pages) { 411 #if SAVAGE_DMA_DEBUG 412 if (dev_priv->dma_pages[i].used) { 413 DRM_ERROR("unflushed page %u: used=%u\n", 414 i, dev_priv->dma_pages[i].used); 415 } 416 #endif 417 if (n > SAVAGE_DMA_PAGE_SIZE) 418 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; 419 else 420 dev_priv->dma_pages[i].used = n; 421 n -= SAVAGE_DMA_PAGE_SIZE; 422 } 423 dev_priv->current_dma_page = --i; 424 425 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n", 426 i, dev_priv->dma_pages[i].used, n); 427 428 savage_dma_wait(dev_priv, dev_priv->current_dma_page); 429 430 return dma_ptr; 431 } 432 433 static void savage_dma_flush(drm_savage_private_t * dev_priv) 434 { 435 unsigned int first = dev_priv->first_dma_page; 436 unsigned int cur = dev_priv->current_dma_page; 437 uint16_t event; 438 unsigned int wrap, pad, align, len, i; 439 unsigned long phys_addr; 440 BCI_LOCALS; 441 442 if (first == cur && 443 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) 444 return; 445 446 /* pad length to multiples of 2 entries 447 * align start of next DMA block to multiles of 8 entries */ 448 pad = -dev_priv->dma_pages[cur].used & 1; 449 align = -(dev_priv->dma_pages[cur].used + pad) & 7; 450 451 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, " 452 "pad=%u, align=%u\n", 453 first, cur, dev_priv->dma_pages[first].flushed, 454 dev_priv->dma_pages[cur].used, pad, align); 455 456 /* pad with noops */ 457 if (pad) { 458 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 459 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 460 dev_priv->dma_pages[cur].used += pad; 461 while (pad != 0) { 462 *dma_ptr++ = BCI_CMD_WAIT; 463 pad--; 464 } 465 } 466 467 mb(); 468 469 /* do flush ... */ 470 phys_addr = dev_priv->cmd_dma->offset + 471 (first * SAVAGE_DMA_PAGE_SIZE + 472 dev_priv->dma_pages[first].flushed) * 4; 473 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + 474 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; 475 476 DRM_DEBUG("phys_addr=%lx, len=%u\n", 477 phys_addr | dev_priv->dma_type, len); 478 479 BEGIN_BCI(3); 480 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1); 481 BCI_WRITE(phys_addr | dev_priv->dma_type); 482 BCI_DMA(len); 483 484 /* fix alignment of the start of the next block */ 485 dev_priv->dma_pages[cur].used += align; 486 487 /* age DMA pages */ 488 event = savage_bci_emit_event(dev_priv, 0); 489 wrap = dev_priv->event_wrap; 490 for (i = first; i < cur; ++i) { 491 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 492 dev_priv->dma_pages[i].used = 0; 493 dev_priv->dma_pages[i].flushed = 0; 494 } 495 /* age the current page only when it's full */ 496 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { 497 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); 498 dev_priv->dma_pages[cur].used = 0; 499 dev_priv->dma_pages[cur].flushed = 0; 500 /* advance to next page */ 501 cur++; 502 if (cur == dev_priv->nr_dma_pages) 503 cur = 0; 504 dev_priv->first_dma_page = dev_priv->current_dma_page = cur; 505 } else { 506 dev_priv->first_dma_page = cur; 507 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; 508 } 509 SET_AGE(&dev_priv->last_dma_age, event, wrap); 510 511 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur, 512 dev_priv->dma_pages[cur].used, 513 dev_priv->dma_pages[cur].flushed); 514 } 515 516 static void savage_fake_dma_flush(drm_savage_private_t * dev_priv) 517 { 518 unsigned int i, j; 519 BCI_LOCALS; 520 521 if (dev_priv->first_dma_page == dev_priv->current_dma_page && 522 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) 523 return; 524 525 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n", 526 dev_priv->first_dma_page, dev_priv->current_dma_page, 527 dev_priv->dma_pages[dev_priv->current_dma_page].used); 528 529 for (i = dev_priv->first_dma_page; 530 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; 531 ++i) { 532 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 533 i * SAVAGE_DMA_PAGE_SIZE; 534 #if SAVAGE_DMA_DEBUG 535 /* Sanity check: all pages except the last one must be full. */ 536 if (i < dev_priv->current_dma_page && 537 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { 538 DRM_ERROR("partial DMA page %u: used=%u", 539 i, dev_priv->dma_pages[i].used); 540 } 541 #endif 542 BEGIN_BCI(dev_priv->dma_pages[i].used); 543 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { 544 BCI_WRITE(dma_ptr[j]); 545 } 546 dev_priv->dma_pages[i].used = 0; 547 } 548 549 /* reset to first page */ 550 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 551 } 552 553 int savage_driver_load(struct drm_device *dev, unsigned long chipset) 554 { 555 drm_savage_private_t *dev_priv; 556 557 dev_priv = kzalloc(sizeof(drm_savage_private_t), GFP_KERNEL); 558 if (dev_priv == NULL) 559 return -ENOMEM; 560 561 dev->dev_private = (void *)dev_priv; 562 563 dev_priv->chipset = (enum savage_family)chipset; 564 565 pci_set_master(dev->pdev); 566 567 return 0; 568 } 569 570 571 /* 572 * Initialize mappings. On Savage4 and SavageIX the alignment 573 * and size of the aperture is not suitable for automatic MTRR setup 574 * in drm_legacy_addmap. Therefore we add them manually before the maps are 575 * initialized, and tear them down on last close. 576 */ 577 int savage_driver_firstopen(struct drm_device *dev) 578 { 579 drm_savage_private_t *dev_priv = dev->dev_private; 580 unsigned long mmio_base, fb_base, fb_size, aperture_base; 581 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist 582 * in case we decide we need information on the BAR for BSD in the 583 * future. 584 */ 585 unsigned int fb_rsrc, aper_rsrc; 586 int ret = 0; 587 588 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 589 fb_rsrc = 0; 590 fb_base = pci_resource_start(dev->pdev, 0); 591 fb_size = SAVAGE_FB_SIZE_S3; 592 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; 593 aper_rsrc = 0; 594 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 595 /* this should always be true */ 596 if (pci_resource_len(dev->pdev, 0) == 0x08000000) { 597 /* Don't make MMIO write-cobining! We need 3 598 * MTRRs. */ 599 dev_priv->mtrr_handles[0] = 600 arch_phys_wc_add(fb_base, 0x01000000); 601 dev_priv->mtrr_handles[1] = 602 arch_phys_wc_add(fb_base + 0x02000000, 603 0x02000000); 604 dev_priv->mtrr_handles[2] = 605 arch_phys_wc_add(fb_base + 0x04000000, 606 0x04000000); 607 } else { 608 DRM_ERROR("strange pci_resource_len %08llx\n", 609 (unsigned long long) 610 pci_resource_len(dev->pdev, 0)); 611 } 612 } else if (dev_priv->chipset != S3_SUPERSAVAGE && 613 dev_priv->chipset != S3_SAVAGE2000) { 614 mmio_base = pci_resource_start(dev->pdev, 0); 615 fb_rsrc = 1; 616 fb_base = pci_resource_start(dev->pdev, 1); 617 fb_size = SAVAGE_FB_SIZE_S4; 618 aper_rsrc = 1; 619 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 620 /* this should always be true */ 621 if (pci_resource_len(dev->pdev, 1) == 0x08000000) { 622 /* Can use one MTRR to cover both fb and 623 * aperture. */ 624 dev_priv->mtrr_handles[0] = 625 arch_phys_wc_add(fb_base, 626 0x08000000); 627 } else { 628 DRM_ERROR("strange pci_resource_len %08llx\n", 629 (unsigned long long) 630 pci_resource_len(dev->pdev, 1)); 631 } 632 } else { 633 mmio_base = pci_resource_start(dev->pdev, 0); 634 fb_rsrc = 1; 635 fb_base = pci_resource_start(dev->pdev, 1); 636 fb_size = pci_resource_len(dev->pdev, 1); 637 aper_rsrc = 2; 638 aperture_base = pci_resource_start(dev->pdev, 2); 639 /* Automatic MTRR setup will do the right thing. */ 640 } 641 642 ret = drm_legacy_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, 643 _DRM_REGISTERS, _DRM_READ_ONLY, 644 &dev_priv->mmio); 645 if (ret) 646 return ret; 647 648 ret = drm_legacy_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER, 649 _DRM_WRITE_COMBINING, &dev_priv->fb); 650 if (ret) 651 return ret; 652 653 ret = drm_legacy_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, 654 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, 655 &dev_priv->aperture); 656 return ret; 657 } 658 659 /* 660 * Delete MTRRs and free device-private data. 661 */ 662 void savage_driver_lastclose(struct drm_device *dev) 663 { 664 drm_savage_private_t *dev_priv = dev->dev_private; 665 int i; 666 667 for (i = 0; i < 3; ++i) { 668 arch_phys_wc_del(dev_priv->mtrr_handles[i]); 669 dev_priv->mtrr_handles[i] = 0; 670 } 671 } 672 673 void savage_driver_unload(struct drm_device *dev) 674 { 675 drm_savage_private_t *dev_priv = dev->dev_private; 676 677 kfree(dev_priv); 678 } 679 680 static int savage_do_init_bci(struct drm_device * dev, drm_savage_init_t * init) 681 { 682 drm_savage_private_t *dev_priv = dev->dev_private; 683 684 if (init->fb_bpp != 16 && init->fb_bpp != 32) { 685 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); 686 return -EINVAL; 687 } 688 if (init->depth_bpp != 16 && init->depth_bpp != 32) { 689 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); 690 return -EINVAL; 691 } 692 if (init->dma_type != SAVAGE_DMA_AGP && 693 init->dma_type != SAVAGE_DMA_PCI) { 694 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); 695 return -EINVAL; 696 } 697 698 dev_priv->cob_size = init->cob_size; 699 dev_priv->bci_threshold_lo = init->bci_threshold_lo; 700 dev_priv->bci_threshold_hi = init->bci_threshold_hi; 701 dev_priv->dma_type = init->dma_type; 702 703 dev_priv->fb_bpp = init->fb_bpp; 704 dev_priv->front_offset = init->front_offset; 705 dev_priv->front_pitch = init->front_pitch; 706 dev_priv->back_offset = init->back_offset; 707 dev_priv->back_pitch = init->back_pitch; 708 dev_priv->depth_bpp = init->depth_bpp; 709 dev_priv->depth_offset = init->depth_offset; 710 dev_priv->depth_pitch = init->depth_pitch; 711 712 dev_priv->texture_offset = init->texture_offset; 713 dev_priv->texture_size = init->texture_size; 714 715 dev_priv->sarea = drm_legacy_getsarea(dev); 716 if (!dev_priv->sarea) { 717 DRM_ERROR("could not find sarea!\n"); 718 savage_do_cleanup_bci(dev); 719 return -EINVAL; 720 } 721 if (init->status_offset != 0) { 722 dev_priv->status = drm_legacy_findmap(dev, init->status_offset); 723 if (!dev_priv->status) { 724 DRM_ERROR("could not find shadow status region!\n"); 725 savage_do_cleanup_bci(dev); 726 return -EINVAL; 727 } 728 } else { 729 dev_priv->status = NULL; 730 } 731 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { 732 dev->agp_buffer_token = init->buffers_offset; 733 dev->agp_buffer_map = drm_legacy_findmap(dev, 734 init->buffers_offset); 735 if (!dev->agp_buffer_map) { 736 DRM_ERROR("could not find DMA buffer region!\n"); 737 savage_do_cleanup_bci(dev); 738 return -EINVAL; 739 } 740 drm_legacy_ioremap(dev->agp_buffer_map, dev); 741 if (!dev->agp_buffer_map->handle) { 742 DRM_ERROR("failed to ioremap DMA buffer region!\n"); 743 savage_do_cleanup_bci(dev); 744 return -ENOMEM; 745 } 746 } 747 if (init->agp_textures_offset) { 748 dev_priv->agp_textures = 749 drm_legacy_findmap(dev, init->agp_textures_offset); 750 if (!dev_priv->agp_textures) { 751 DRM_ERROR("could not find agp texture region!\n"); 752 savage_do_cleanup_bci(dev); 753 return -EINVAL; 754 } 755 } else { 756 dev_priv->agp_textures = NULL; 757 } 758 759 if (init->cmd_dma_offset) { 760 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 761 DRM_ERROR("command DMA not supported on " 762 "Savage3D/MX/IX.\n"); 763 savage_do_cleanup_bci(dev); 764 return -EINVAL; 765 } 766 if (dev->dma && dev->dma->buflist) { 767 DRM_ERROR("command and vertex DMA not supported " 768 "at the same time.\n"); 769 savage_do_cleanup_bci(dev); 770 return -EINVAL; 771 } 772 dev_priv->cmd_dma = drm_legacy_findmap(dev, init->cmd_dma_offset); 773 if (!dev_priv->cmd_dma) { 774 DRM_ERROR("could not find command DMA region!\n"); 775 savage_do_cleanup_bci(dev); 776 return -EINVAL; 777 } 778 if (dev_priv->dma_type == SAVAGE_DMA_AGP) { 779 if (dev_priv->cmd_dma->type != _DRM_AGP) { 780 DRM_ERROR("AGP command DMA region is not a " 781 "_DRM_AGP map!\n"); 782 savage_do_cleanup_bci(dev); 783 return -EINVAL; 784 } 785 drm_legacy_ioremap(dev_priv->cmd_dma, dev); 786 if (!dev_priv->cmd_dma->handle) { 787 DRM_ERROR("failed to ioremap command " 788 "DMA region!\n"); 789 savage_do_cleanup_bci(dev); 790 return -ENOMEM; 791 } 792 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { 793 DRM_ERROR("PCI command DMA region is not a " 794 "_DRM_CONSISTENT map!\n"); 795 savage_do_cleanup_bci(dev); 796 return -EINVAL; 797 } 798 } else { 799 dev_priv->cmd_dma = NULL; 800 } 801 802 dev_priv->dma_flush = savage_dma_flush; 803 if (!dev_priv->cmd_dma) { 804 DRM_DEBUG("falling back to faked command DMA.\n"); 805 dev_priv->fake_dma.offset = 0; 806 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; 807 dev_priv->fake_dma.type = _DRM_SHM; 808 dev_priv->fake_dma.handle = kmalloc(SAVAGE_FAKE_DMA_SIZE, 809 GFP_KERNEL); 810 if (!dev_priv->fake_dma.handle) { 811 DRM_ERROR("could not allocate faked DMA buffer!\n"); 812 savage_do_cleanup_bci(dev); 813 return -ENOMEM; 814 } 815 dev_priv->cmd_dma = &dev_priv->fake_dma; 816 dev_priv->dma_flush = savage_fake_dma_flush; 817 } 818 819 dev_priv->sarea_priv = 820 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle + 821 init->sarea_priv_offset); 822 823 /* setup bitmap descriptors */ 824 { 825 unsigned int color_tile_format; 826 unsigned int depth_tile_format; 827 unsigned int front_stride, back_stride, depth_stride; 828 if (dev_priv->chipset <= S3_SAVAGE4) { 829 color_tile_format = dev_priv->fb_bpp == 16 ? 830 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 831 depth_tile_format = dev_priv->depth_bpp == 16 ? 832 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 833 } else { 834 color_tile_format = SAVAGE_BD_TILE_DEST; 835 depth_tile_format = SAVAGE_BD_TILE_DEST; 836 } 837 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); 838 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); 839 depth_stride = 840 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); 841 842 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | 843 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 844 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 845 846 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE | 847 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 848 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 849 850 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | 851 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | 852 (depth_tile_format << SAVAGE_BD_TILE_SHIFT); 853 } 854 855 /* setup status and bci ptr */ 856 dev_priv->event_counter = 0; 857 dev_priv->event_wrap = 0; 858 dev_priv->bci_ptr = (volatile uint32_t *) 859 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); 860 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 861 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; 862 } else { 863 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; 864 } 865 if (dev_priv->status != NULL) { 866 dev_priv->status_ptr = 867 (volatile uint32_t *)dev_priv->status->handle; 868 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; 869 dev_priv->wait_evnt = savage_bci_wait_event_shadow; 870 dev_priv->status_ptr[1023] = dev_priv->event_counter; 871 } else { 872 dev_priv->status_ptr = NULL; 873 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 874 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; 875 } else { 876 dev_priv->wait_fifo = savage_bci_wait_fifo_s4; 877 } 878 dev_priv->wait_evnt = savage_bci_wait_event_reg; 879 } 880 881 /* cliprect functions */ 882 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) 883 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; 884 else 885 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; 886 887 if (savage_freelist_init(dev) < 0) { 888 DRM_ERROR("could not initialize freelist\n"); 889 savage_do_cleanup_bci(dev); 890 return -ENOMEM; 891 } 892 893 if (savage_dma_init(dev_priv) < 0) { 894 DRM_ERROR("could not initialize command DMA\n"); 895 savage_do_cleanup_bci(dev); 896 return -ENOMEM; 897 } 898 899 return 0; 900 } 901 902 static int savage_do_cleanup_bci(struct drm_device * dev) 903 { 904 drm_savage_private_t *dev_priv = dev->dev_private; 905 906 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { 907 kfree(dev_priv->fake_dma.handle); 908 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle && 909 dev_priv->cmd_dma->type == _DRM_AGP && 910 dev_priv->dma_type == SAVAGE_DMA_AGP) 911 drm_legacy_ioremapfree(dev_priv->cmd_dma, dev); 912 913 if (dev_priv->dma_type == SAVAGE_DMA_AGP && 914 dev->agp_buffer_map && dev->agp_buffer_map->handle) { 915 drm_legacy_ioremapfree(dev->agp_buffer_map, dev); 916 /* make sure the next instance (which may be running 917 * in PCI mode) doesn't try to use an old 918 * agp_buffer_map. */ 919 dev->agp_buffer_map = NULL; 920 } 921 922 kfree(dev_priv->dma_pages); 923 924 return 0; 925 } 926 927 static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 928 { 929 drm_savage_init_t *init = data; 930 931 LOCK_TEST_WITH_RETURN(dev, file_priv); 932 933 switch (init->func) { 934 case SAVAGE_INIT_BCI: 935 return savage_do_init_bci(dev, init); 936 case SAVAGE_CLEANUP_BCI: 937 return savage_do_cleanup_bci(dev); 938 } 939 940 return -EINVAL; 941 } 942 943 static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) 944 { 945 drm_savage_private_t *dev_priv = dev->dev_private; 946 drm_savage_event_emit_t *event = data; 947 948 DRM_DEBUG("\n"); 949 950 LOCK_TEST_WITH_RETURN(dev, file_priv); 951 952 event->count = savage_bci_emit_event(dev_priv, event->flags); 953 event->count |= dev_priv->event_wrap << 16; 954 955 return 0; 956 } 957 958 static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) 959 { 960 drm_savage_private_t *dev_priv = dev->dev_private; 961 drm_savage_event_wait_t *event = data; 962 unsigned int event_e, hw_e; 963 unsigned int event_w, hw_w; 964 965 DRM_DEBUG("\n"); 966 967 UPDATE_EVENT_COUNTER(); 968 if (dev_priv->status_ptr) 969 hw_e = dev_priv->status_ptr[1] & 0xffff; 970 else 971 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 972 hw_w = dev_priv->event_wrap; 973 if (hw_e > dev_priv->event_counter) 974 hw_w--; /* hardware hasn't passed the last wrap yet */ 975 976 event_e = event->count & 0xffff; 977 event_w = event->count >> 16; 978 979 /* Don't need to wait if 980 * - event counter wrapped since the event was emitted or 981 * - the hardware has advanced up to or over the event to wait for. 982 */ 983 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e)) 984 return 0; 985 else 986 return dev_priv->wait_evnt(dev_priv, event_e); 987 } 988 989 /* 990 * DMA buffer management 991 */ 992 993 static int savage_bci_get_buffers(struct drm_device *dev, 994 struct drm_file *file_priv, 995 struct drm_dma *d) 996 { 997 struct drm_buf *buf; 998 int i; 999 1000 for (i = d->granted_count; i < d->request_count; i++) { 1001 buf = savage_freelist_get(dev); 1002 if (!buf) 1003 return -EAGAIN; 1004 1005 buf->file_priv = file_priv; 1006 1007 if (copy_to_user(&d->request_indices[i], 1008 &buf->idx, sizeof(buf->idx))) 1009 return -EFAULT; 1010 if (copy_to_user(&d->request_sizes[i], 1011 &buf->total, sizeof(buf->total))) 1012 return -EFAULT; 1013 1014 d->granted_count++; 1015 } 1016 return 0; 1017 } 1018 1019 int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1020 { 1021 struct drm_device_dma *dma = dev->dma; 1022 struct drm_dma *d = data; 1023 int ret = 0; 1024 1025 LOCK_TEST_WITH_RETURN(dev, file_priv); 1026 1027 /* Please don't send us buffers. 1028 */ 1029 if (d->send_count != 0) { 1030 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1031 task_pid_nr(current), d->send_count); 1032 return -EINVAL; 1033 } 1034 1035 /* We'll send you buffers. 1036 */ 1037 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1038 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1039 task_pid_nr(current), d->request_count, dma->buf_count); 1040 return -EINVAL; 1041 } 1042 1043 d->granted_count = 0; 1044 1045 if (d->request_count) { 1046 ret = savage_bci_get_buffers(dev, file_priv, d); 1047 } 1048 1049 return ret; 1050 } 1051 1052 void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) 1053 { 1054 struct drm_device_dma *dma = dev->dma; 1055 drm_savage_private_t *dev_priv = dev->dev_private; 1056 int release_idlelock = 0; 1057 int i; 1058 1059 if (!dma) 1060 return; 1061 if (!dev_priv) 1062 return; 1063 if (!dma->buflist) 1064 return; 1065 1066 if (file_priv->master && file_priv->master->lock.hw_lock) { 1067 drm_legacy_idlelock_take(&file_priv->master->lock); 1068 release_idlelock = 1; 1069 } 1070 1071 for (i = 0; i < dma->buf_count; i++) { 1072 struct drm_buf *buf = dma->buflist[i]; 1073 drm_savage_buf_priv_t *buf_priv = buf->dev_private; 1074 1075 if (buf->file_priv == file_priv && buf_priv && 1076 buf_priv->next == NULL && buf_priv->prev == NULL) { 1077 uint16_t event; 1078 DRM_DEBUG("reclaimed from client\n"); 1079 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); 1080 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); 1081 savage_freelist_put(dev, buf); 1082 } 1083 } 1084 1085 if (release_idlelock) 1086 drm_legacy_idlelock_release(&file_priv->master->lock); 1087 } 1088 1089 const struct drm_ioctl_desc savage_ioctls[] = { 1090 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1091 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), 1092 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), 1093 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), 1094 }; 1095 1096 int savage_max_ioctl = ARRAY_SIZE(savage_ioctls); 1097
Indexes created Thu Oct 02 14:10:14 GMT 2025