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      1 /* $NetBSD: unichromemode.h,v 1.2 2024/02/02 22:33:42 andvar Exp $ */
      2 
      3 /*
      4  * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
      5  * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
      6  *
      7  * Permission is hereby granted, free of charge, to any person obtaining a
      8  * copy of this software and associated documentation files (the "Software"),
      9  * to deal in the Software without restriction, including without limitation
     10  * the rights to use, copy, modify, merge, publish, distribute, sub license,
     11  * and/or sell copies of the Software, and to permit persons to whom the
     12  * Software is furnished to do so, subject to the following conditions:
     13  *
     14  * The above copyright notice and this permission notice (including the
     15  * next paragraph) shall be included in all copies or substantial portions
     16  * of the Software.
     17  *
     18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
     21  * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     24  * DEALINGS IN THE SOFTWARE.
     25  */
     26 
     27 #ifndef _DEV_PCI_UNICHROMEMODE_H
     28 #define _DEV_PCI_UNICHROMEMODE_H
     29 
     30 #define	ARRAY_SIZE(x)	(sizeof((x)) / sizeof((x)[0]))
     31 
     32 struct VPITTable {
     33   unsigned char  Misc;
     34   unsigned char  SR[StdSR];
     35   unsigned char  GR[StdGR];
     36   unsigned char  AR[StdAR];
     37 };
     38 
     39 struct VideoModeTable {
     40   int                               ModeIndex;
     41   struct crt_mode_table             *crtc;
     42   int                               mode_array;
     43 };
     44 
     45 struct patch_table {
     46   int           mode_index;
     47   int           table_length;
     48   struct io_reg *io_reg_table;
     49 };
     50 
     51 struct res_map_refresh {
     52   int       hres;
     53   int       vres;
     54   int       pixclock;
     55   int       vmode_refresh;
     56 };
     57 
     58 struct res_map_refresh res_map_refresh_tbl[] = {
     59 //hres, vres, vclock, vmode_refresh
     60   {640, 480, RES_640X480_60HZ_PIXCLOCK,   60},
     61   {640, 480, RES_640X480_75HZ_PIXCLOCK,   75},
     62   {640, 480, RES_640X480_85HZ_PIXCLOCK,   85},
     63   {640, 480, RES_640X480_100HZ_PIXCLOCK,  100},
     64   {640, 480, RES_640X480_120HZ_PIXCLOCK,  120},
     65   {720, 480, RES_720X480_60HZ_PIXCLOCK,   60},
     66   {720, 576, RES_720X576_60HZ_PIXCLOCK,   60},
     67   {800, 480, RES_800X480_60HZ_PIXCLOCK,   60},
     68   {800, 600, RES_800X600_60HZ_PIXCLOCK,   60},
     69   {800, 600, RES_800X600_75HZ_PIXCLOCK,   75},
     70   {800, 600, RES_800X600_85HZ_PIXCLOCK,   85},
     71   {800, 600, RES_800X600_100HZ_PIXCLOCK,  100},
     72   {800, 600, RES_800X600_120HZ_PIXCLOCK,  120},
     73   {848, 480, RES_848X480_60HZ_PIXCLOCK,   60},
     74   {856, 480, RES_856X480_60HZ_PIXCLOCK,   60},
     75   {1024,512, RES_1024X512_60HZ_PIXCLOCK,  60},
     76   {1024,768, RES_1024X768_60HZ_PIXCLOCK,  60},
     77   {1024,768, RES_1024X768_75HZ_PIXCLOCK,  75},
     78   {1024,768, RES_1024X768_85HZ_PIXCLOCK,  85},
     79   {1024,768, RES_1024X768_100HZ_PIXCLOCK, 100},
     80   {1152,864, RES_1152X864_70HZ_PIXCLOCK,  70},
     81   {1152,864, RES_1152X864_75HZ_PIXCLOCK,  75},
     82   {1280,768, RES_1280X768_60HZ_PIXCLOCK,  60},
     83   {1280,960, RES_1280X960_60HZ_PIXCLOCK,  60},
     84   {1280,1024,RES_1280X1024_60HZ_PIXCLOCK, 60},
     85   {1280,1024,RES_1280X1024_75HZ_PIXCLOCK, 75},
     86   {1280,1024,RES_1280X768_85HZ_PIXCLOCK,  85},
     87   {1440,1050,RES_1440X1050_60HZ_PIXCLOCK, 60},
     88   {1600,1200,RES_1600X1200_60HZ_PIXCLOCK, 60},
     89   {1600,1200,RES_1600X1200_75HZ_PIXCLOCK, 75},
     90   {1280,720, RES_1280X720_60HZ_PIXCLOCK,  60},
     91   {1920,1080,RES_1920X1080_60HZ_PIXCLOCK, 60},
     92   {1400,1050,RES_1400X1050_60HZ_PIXCLOCK, 60},
     93   {1366,768, RES_1366X768_60HZ_PIXCLOCK,60}
     94 };
     95 #define NUM_TOTAL_RES_MAP_REFRESH ARRAY_SIZE(res_map_refresh_tbl)
     96 
     97 struct io_reg CN400_ModeXregs[] = {
     98     {VIASR, SR10, 0xFF, 0x01},
     99     {VIASR, SR15, 0x02, 0x02},
    100     {VIASR, SR16, 0xBF, 0x08},
    101     {VIASR, SR17, 0xFF, 0x1F},
    102     {VIASR, SR18, 0xFF, 0x4E},
    103     {VIASR, SR1A, 0xFB, 0x08},
    104     {VIASR, SR1E, 0x0F, 0x01},
    105     {VIASR, SR2A, 0xF0, 0x00},
    106     {VIACR, CR0A, 0xFF, 0x1E},          /* Cursor Start                        */
    107     {VIACR, CR0B, 0xFF, 0x00},          /* Cursor End                          */
    108     {VIACR, CR0E, 0xFF, 0x00},          /* Cursor Location High                */
    109     {VIACR, CR0F, 0xFF, 0x00},          /* Cursor Localtion Low                */
    110     {VIACR, CR32, 0xFF, 0x00},
    111     {VIACR, CR33, 0xFF, 0x00},
    112     {VIACR, CR34, 0xFF, 0x00},
    113     {VIACR, CR35, 0xFF, 0x00},
    114     {VIACR, CR36, 0x08, 0x00},
    115     {VIACR, CR62, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    116     {VIACR, CR63, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    117     {VIACR, CR64, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    118     {VIACR, CR69, 0xFF, 0x00},
    119     {VIACR, CR6A, 0xFF, 0x40},
    120     {VIACR, CR6B, 0xFF, 0x00},
    121     {VIACR, CR6C, 0xFF, 0x00},
    122     {VIACR, CR7A, 0xFF, 0x01},          /* LCD Scaling Parameter 1             */
    123     {VIACR, CR7B, 0xFF, 0x02},          /* LCD Scaling Parameter 2             */
    124     {VIACR, CR7C, 0xFF, 0x03},          /* LCD Scaling Parameter 3             */
    125     {VIACR, CR7D, 0xFF, 0x04},          /* LCD Scaling Parameter 4             */
    126     {VIACR, CR7E, 0xFF, 0x07},          /* LCD Scaling Parameter 5             */
    127     {VIACR, CR7F, 0xFF, 0x0A},          /* LCD Scaling Parameter 6             */
    128     {VIACR, CR80, 0xFF, 0x0D},          /* LCD Scaling Parameter 7             */
    129     {VIACR, CR81, 0xFF, 0x13},          /* LCD Scaling Parameter 8             */
    130     {VIACR, CR82, 0xFF, 0x16},          /* LCD Scaling Parameter 9             */
    131     {VIACR, CR83, 0xFF, 0x19},          /* LCD Scaling Parameter 10            */
    132     {VIACR, CR84, 0xFF, 0x1C},          /* LCD Scaling Parameter 11            */
    133     {VIACR, CR85, 0xFF, 0x1D},          /* LCD Scaling Parameter 12            */
    134     {VIACR, CR86, 0xFF, 0x1E},          /* LCD Scaling Parameter 13            */
    135     {VIACR, CR87, 0xFF, 0x1F},          /* LCD Scaling Parameter 14            */
    136     {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
    137     {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
    138     {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
    139     {VIACR, CR8B, 0xFF, 0x69},          /* LCD Power Sequence Control 0        */
    140     {VIACR, CR8C, 0xFF, 0x57},          /* LCD Power Sequence Control 1        */
    141     {VIACR, CR8D, 0xFF, 0x00},          /* LCD Power Sequence Control 2        */
    142     {VIACR, CR8E, 0xFF, 0x7B},          /* LCD Power Sequence Control 3        */
    143     {VIACR, CR8F, 0xFF, 0x03},          /* LCD Power Sequence Control 4        */
    144     {VIACR, CR90, 0xFF, 0x30},          /* LCD Power Sequence Control 5        */
    145     {VIACR, CR91, 0xFF, 0xA0},          /* 24/12 bit LVDS Data off             */
    146     {VIACR, CR96, 0xFF, 0x00},
    147     {VIACR, CR97, 0xFF, 0x00},
    148     {VIACR, CR99, 0xFF, 0x00},
    149     {VIACR, CR9B, 0xFF, 0x00}
    150 };
    151 #define NUM_TOTAL_CN400_ModeXregs ARRAY_SIZE(CN400_ModeXregs)
    152 
    153 /* Video Mode Table for VT3314 chipset*/
    154 /* Common Setting for Video Mode */
    155 struct io_reg CN900_ModeXregs[] = {
    156   {VIASR,SR10,0xFF,0x01},
    157   {VIASR,SR15,0x02,0x02},
    158   {VIASR,SR16,0xBF,0x08},
    159   {VIASR,SR17,0xFF,0x1F},
    160   {VIASR,SR18,0xFF,0x4E},
    161   {VIASR,SR1A,0xFB,0x82},
    162   {VIASR,SR1B,0xFF,0xF0},
    163   {VIASR,SR1F,0xFF,0x00},
    164   {VIASR,SR1E,0xFF,0xF1},
    165   {VIASR,SR22,0xFF,0x1F},
    166   {VIASR,SR2A,0x0F,0x0F},
    167   {VIASR,SR2E,0xFF,0xFF},
    168   {VIASR,SR3F,0xFF,0xFF},
    169   {VIASR,SR40,0xFF,0x00},
    170   {VIASR,CR30,0xFF,0x04},
    171   {VIACR,CR32,0xFF,0x00},
    172   {VIACR,CR33,0xFF,0x00},
    173   {VIACR,CR34,0xFF,0x00},
    174   {VIACR,CR35,0xFF,0x00},
    175   {VIACR,CR36,0xFF,0x31},
    176   {VIACR,CR41,0xFF,0x80},
    177   {VIACR,CR42,0xFF,0x00},
    178   {VIACR,CR5D,0x80,0x00},                                      /* Horizontal Retrace Start bit [11] should be 0*/
    179   {VIACR,CR62,0xFF,0x00},                                      /* Secondary Display Starting Address*/
    180   {VIACR,CR63,0xFF,0x00},                                      /* Secondary Display Starting Address*/
    181   {VIACR,CR64,0xFF,0x00},                                      /* Secondary Display Starting Address*/
    182   {VIACR,CR68,0xFF,0x67},                                      /* Default FIFO For IGA2 */
    183   {VIACR,CR69,0xFF,0x00},
    184   {VIACR,CR6A,0xFF,0x40},
    185   {VIACR,CR6B,0xFF,0x00},
    186   {VIACR,CR6C,0xFF,0x00},
    187   {VIACR,CR77,0xFF,0x00},                                      /* LCD scaling Factor*/
    188   {VIACR,CR78,0xFF,0x00},                                      /* LCD scaling Factor */
    189   {VIACR,CR79,0xFF,0x00},                                      /* LCD scaling Factor*/
    190   {VIACR,CR9F,0x03,0x00},                                      /* LCD scaling Factor */
    191   {VIACR,CR7A,0xFF,0x01},                                      /* LCD Scaling Parameter 1*/
    192   {VIACR,CR7B,0xFF,0x02},                                      /* LCD Scaling Parameter 2*/
    193   {VIACR,CR7C,0xFF,0x03},                                      /* LCD Scaling Parameter 3 */
    194   {VIACR,CR7D,0xFF,0x04},                                      /* LCD Scaling Parameter 4*/
    195   {VIACR,CR7E,0xFF,0x07},                                      /* LCD Scaling Parameter 5*/
    196   {VIACR,CR7F,0xFF,0x0A},                                      /* LCD Scaling Parameter 6*/
    197   {VIACR,CR80,0xFF,0x0D},                                      /* LCD Scaling Parameter 7*/
    198   {VIACR,CR81,0xFF,0x13},                                      /* LCD Scaling Parameter 8*/
    199   {VIACR,CR82,0xFF,0x16},                                      /* LCD Scaling Parameter 9*/
    200   {VIACR,CR83,0xFF,0x19},                                      /* LCD Scaling Parameter 10*/
    201   {VIACR,CR84,0xFF,0x1C},                                      /* LCD Scaling Parameter 11*/
    202   {VIACR,CR85,0xFF,0x1D},                                      /* LCD Scaling Parameter 12*/
    203   {VIACR,CR86,0xFF,0x1E},                                      /* LCD Scaling Parameter 13*/
    204   {VIACR,CR87,0xFF,0x1F},                                      /* LCD Scaling Parameter 14*/
    205   {VIACR,CR88,0xFF,0x40},                                      /* LCD Panel Type */
    206   {VIACR,CR89,0xFF,0x00},                                      /* LCD Timing Control 0 */
    207   {VIACR,CR8A,0xFF,0x88},                                      /* LCD Timing Control 1*/
    208   {VIACR,CR8B,0xFF,0x69},                                      /* LCD Power Sequence Control 0*/
    209   {VIACR,CR8C,0xFF,0x57},                                      /* LCD Power Sequence Control 1*/
    210   {VIACR,CR8D,0xFF,0x00},                                      /* LCD Power Sequence Control 2*/
    211   {VIACR,CR8E,0xFF,0x7B},                                      /* LCD Power Sequence Control 3*/
    212   {VIACR,CR8F,0xFF,0x03},                                      /* LCD Power Sequence Control 4*/
    213   {VIACR,CR90,0xFF,0x30},                                      /* LCD Power Sequence Control 5*/
    214   {VIACR,CR91,0xFF,0xA0},                                      /* 24/12 bit LVDS Data off*/
    215   {VIACR,CR96,0xFF,0x00},
    216   {VIACR,CR97,0xFF,0x00},
    217   {VIACR,CR99,0xFF,0x00},
    218   {VIACR,CR9B,0xFF,0x00},
    219   {VIACR,CR9D,0xFF,0x80},
    220   {VIACR,CR9E,0xFF,0x80}
    221 };
    222 #define NUM_TOTAL_CN900_ModeXregs ARRAY_SIZE(CN900_ModeXregs)
    223 
    224 struct io_reg KM400_ModeXregs[] = {
    225     {VIASR, SR10, 0xFF, 0x01},          /* Unlock Register                     */
    226     {VIASR, SR16, 0xFF, 0x08},          /* Display FIFO threshold Control      */
    227     {VIASR, SR17, 0xFF, 0x1F},          /* Display FIFO Control                */
    228     {VIASR, SR18, 0xFF, 0x4E},          /* GFX PREQ threshold                  */
    229     {VIASR, SR1A, 0xFF, 0x0a},          /* GFX PREQ threshold                  */
    230     {VIASR, SR1F, 0xFF, 0x00},          /* Memory Control 0                    */
    231     {VIASR, SR1B, 0xFF, 0xF0},          /* Power Management Control 0          */
    232     {VIASR, SR1E, 0x0F, 0x01},          /* Power Management Control            */
    233     {VIASR, SR20, 0xFF, 0x00},          /* Sequencer Arbiter Control 0         */
    234     {VIASR, SR21, 0xFF, 0x00},          /* Sequencer Arbiter Control 1         */
    235     {VIASR, SR22, 0xFF, 0x1F},          /* Display Arbiter Control 1           */
    236     {VIASR, SR2A, 0xF0, 0x00},          /* Power Management Control 5          */
    237     {VIASR, SR2D, 0xFF, 0xFF},          /* Power Management Control 1          */
    238     {VIASR, SR2E, 0xFF, 0xFF},          /* Power Management Control 2          */
    239     {VIACR, CR0A, 0xFF, 0x1E},          /* Cursor Start                        */
    240     {VIACR, CR0B, 0xFF, 0x00},          /* Cursor End                          */
    241     {VIACR, CR0E, 0xFF, 0x00},          /* Cursor Location High                */
    242     {VIACR, CR0F, 0xFF, 0x00},          /* Cursor Localtion Low                */
    243     {VIACR, CR33, 0xFF, 0x00},
    244     {VIACR, CR55, 0x80, 0x00},
    245     {VIACR, CR5D, 0x80, 0x00},
    246     {VIACR, CR36, 0xFF, 0x01},          /* Power Management 3                   */
    247     {VIACR, CR62, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    248     {VIACR, CR63, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    249     {VIACR, CR64, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    250     {VIACR, CR68, 0xFF, 0x67},          /* Default FIFO For IGA2               */
    251     {VIACR, CR6A, 0x20, 0x20},          /* Extended FIFO On                    */
    252     {VIACR, CR7A, 0xFF, 0x01},          /* LCD Scaling Parameter 1             */
    253     {VIACR, CR7B, 0xFF, 0x02},          /* LCD Scaling Parameter 2             */
    254     {VIACR, CR7C, 0xFF, 0x03},          /* LCD Scaling Parameter 3             */
    255     {VIACR, CR7D, 0xFF, 0x04},          /* LCD Scaling Parameter 4             */
    256     {VIACR, CR7E, 0xFF, 0x07},          /* LCD Scaling Parameter 5             */
    257     {VIACR, CR7F, 0xFF, 0x0A},          /* LCD Scaling Parameter 6             */
    258     {VIACR, CR80, 0xFF, 0x0D},          /* LCD Scaling Parameter 7             */
    259     {VIACR, CR81, 0xFF, 0x13},          /* LCD Scaling Parameter 8             */
    260     {VIACR, CR82, 0xFF, 0x16},          /* LCD Scaling Parameter 9             */
    261     {VIACR, CR83, 0xFF, 0x19},          /* LCD Scaling Parameter 10            */
    262     {VIACR, CR84, 0xFF, 0x1C},          /* LCD Scaling Parameter 11            */
    263     {VIACR, CR85, 0xFF, 0x1D},          /* LCD Scaling Parameter 12            */
    264     {VIACR, CR86, 0xFF, 0x1E},          /* LCD Scaling Parameter 13            */
    265     {VIACR, CR87, 0xFF, 0x1F},          /* LCD Scaling Parameter 14            */
    266     {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
    267     {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
    268     {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
    269     {VIACR, CR8B, 0xFF, 0x2D},          /* LCD Power Sequence Control 0        */
    270     {VIACR, CR8C, 0xFF, 0x2D},          /* LCD Power Sequence Control 1        */
    271     {VIACR, CR8D, 0xFF, 0xC8},          /* LCD Power Sequence Control 2        */
    272     {VIACR, CR8E, 0xFF, 0x36},          /* LCD Power Sequence Control 3        */
    273     {VIACR, CR8F, 0xFF, 0x00},          /* LCD Power Sequence Control 4        */
    274     {VIACR, CR90, 0xFF, 0x10},          /* LCD Power Sequence Control 5        */
    275     {VIACR, CR91, 0xFF, 0xA0},          /* 24/12 bit LVDS Data off             */
    276     {VIACR, CR96, 0xFF, 0x03},          /* TV on DVP0        ; DVP0 Clock Skew */
    277     {VIACR, CR97, 0xFF, 0x03},          /* TV on DFP high    ; DFPH Clock Skew */
    278     {VIACR, CR99, 0xFF, 0x03},          /* DFP low           ; DFPL Clock Skew */
    279     {VIACR, CR9B, 0xFF, 0x07}           /* DVI on DVP1       ; DVP1 Clock Skew */
    280 };
    281 #define NUM_TOTAL_KM400_ModeXregs ARRAY_SIZE(KM400_ModeXregs)
    282 
    283 /* For VT3324: Common Setting for Video Mode */
    284 struct io_reg CX700_ModeXregs[] = {
    285     {VIASR, SR10, 0xFF, 0x01},
    286     {VIASR, SR15, 0x02, 0x02},
    287     {VIASR, SR16, 0xBF, 0x08},
    288     {VIASR, SR17, 0xFF, 0x1F},
    289     {VIASR, SR18, 0xFF, 0x4E},
    290     {VIASR, SR1A, 0xFB, 0x08},
    291     {VIASR, SR1B, 0xFF, 0xF0},
    292     {VIASR, SR1E, 0x0F, 0x01},
    293     {VIASR, SR2A, 0xF0, 0x00},
    294     {VIACR, CR0A, 0xFF, 0x1E},          /* Cursor Start                        */
    295     {VIACR, CR0B, 0xFF, 0x00},          /* Cursor End                          */
    296     {VIACR, CR0E, 0xFF, 0x00},          /* Cursor Location High                */
    297     {VIACR, CR0F, 0xFF, 0x00},          /* Cursor Localtion Low                */
    298     {VIACR, CR32, 0xFF, 0x00},
    299     {VIACR, CR33, 0xFF, 0x00},
    300     {VIACR, CR34, 0xFF, 0x00},
    301     {VIACR, CR35, 0xFF, 0x00},
    302     {VIACR, CR36, 0x08, 0x00},
    303     {VIACR, CR47, 0xC8, 0x00},          /* Clear VCK Plus. */
    304     {VIACR, CR62, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    305     {VIACR, CR63, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    306     {VIACR, CR64, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    307     {VIACR, CRA3, 0xFF, 0x00},          /* Secondary Display Starting Address  */
    308     {VIACR, CR69, 0xFF, 0x00},
    309     {VIACR, CR6A, 0xFF, 0x40},
    310     {VIACR, CR6B, 0xFF, 0x00},
    311     {VIACR, CR6C, 0xFF, 0x00},
    312     {VIACR, CR7A, 0xFF, 0x01},          /* LCD Scaling Parameter 1             */
    313     {VIACR, CR7B, 0xFF, 0x02},          /* LCD Scaling Parameter 2             */
    314     {VIACR, CR7C, 0xFF, 0x03},          /* LCD Scaling Parameter 3             */
    315     {VIACR, CR7D, 0xFF, 0x04},          /* LCD Scaling Parameter 4             */
    316     {VIACR, CR7E, 0xFF, 0x07},          /* LCD Scaling Parameter 5             */
    317     {VIACR, CR7F, 0xFF, 0x0A},          /* LCD Scaling Parameter 6             */
    318     {VIACR, CR80, 0xFF, 0x0D},          /* LCD Scaling Parameter 7             */
    319     {VIACR, CR81, 0xFF, 0x13},          /* LCD Scaling Parameter 8             */
    320     {VIACR, CR82, 0xFF, 0x16},          /* LCD Scaling Parameter 9             */
    321     {VIACR, CR83, 0xFF, 0x19},          /* LCD Scaling Parameter 10            */
    322     {VIACR, CR84, 0xFF, 0x1C},          /* LCD Scaling Parameter 11            */
    323     {VIACR, CR85, 0xFF, 0x1D},          /* LCD Scaling Parameter 12            */
    324     {VIACR, CR86, 0xFF, 0x1E},          /* LCD Scaling Parameter 13            */
    325     {VIACR, CR87, 0xFF, 0x1F},          /* LCD Scaling Parameter 14            */
    326     {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
    327     {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
    328     {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
    329     {VIACR, CRD4, 0xFF, 0x81},          /* Second power sequence control       */
    330     {VIACR, CR8B, 0xFF, 0x5D},          /* LCD Power Sequence Control 0        */
    331     {VIACR, CR8C, 0xFF, 0x2B},          /* LCD Power Sequence Control 1        */
    332     {VIACR, CR8D, 0xFF, 0x6F},          /* LCD Power Sequence Control 2        */
    333     {VIACR, CR8E, 0xFF, 0x2B},          /* LCD Power Sequence Control 3        */
    334     {VIACR, CR8F, 0xFF, 0x01},          /* LCD Power Sequence Control 4        */
    335     {VIACR, CR90, 0xFF, 0x01},          /* LCD Power Sequence Control 5        */
    336     {VIACR, CR91, 0xFF, 0x80},          /* 24/12 bit LVDS Data off             */
    337     {VIACR, CR96, 0xFF, 0x00},
    338     {VIACR, CR97, 0xFF, 0x00},
    339     {VIACR, CR99, 0xFF, 0x00},
    340     {VIACR, CR9B, 0xFF, 0x00},
    341     {VIACR, CRD2, 0xFF, 0x03}           /* LVDS0/LVDS1 Channel format.         */
    342 };
    343 
    344 #define NUM_TOTAL_CX700_ModeXregs ARRAY_SIZE(CX700_ModeXregs)
    345 
    346 /* Video Mode Table */
    347 /* Common Setting for Video Mode */
    348 struct io_reg CLE266_ModeXregs[] = {
    349   {VIASR,SR1E,0xF0,0xF0},
    350   {VIASR,SR2A,0x0F,0x0F},
    351   {VIASR,SR15,0x02,0x02},
    352   {VIASR,SR16,0xBF,0x08},
    353   {VIASR,SR17,0xFF,0x1F},
    354   {VIASR,SR18,0xFF,0x4E},
    355   {VIASR,SR1A,0xFB,0x08},
    356 
    357   {VIACR,CR32,0xFF,0x00},
    358 //  {VIACR,CR33,0xFF,0x08}, // for K800 prefetch mode
    359   {VIACR,CR34,0xFF,0x00},
    360   {VIACR,CR35,0xFF,0x00},
    361   {VIACR,CR36,0x08,0x00},
    362   {VIACR,CR6A,0xFF,0x80},
    363   {VIACR,CR6A,0xFF,0xC0},
    364 
    365   {VIACR,CR55,0x80,0x00},
    366   {VIACR,CR5D,0x80,0x00},
    367 
    368   {VIAGR,GR20,0xFF,0x00},
    369   {VIAGR,GR21,0xFF,0x00},
    370   {VIAGR,GR22,0xFF,0x00},
    371                             // LCD Parameters
    372   {VIACR,CR7A,0xFF,0x01},   // LCD Parameter 1
    373   {VIACR,CR7B,0xFF,0x02},   // LCD Parameter 2
    374   {VIACR,CR7C,0xFF,0x03},   // LCD Parameter 3
    375   {VIACR,CR7D,0xFF,0x04},   // LCD Parameter 4
    376   {VIACR,CR7E,0xFF,0x07},   // LCD Parameter 5
    377   {VIACR,CR7F,0xFF,0x0A},   // LCD Parameter 6
    378   {VIACR,CR80,0xFF,0x0D},   // LCD Parameter 7
    379   {VIACR,CR81,0xFF,0x13},   // LCD Parameter 8
    380   {VIACR,CR82,0xFF,0x16},   // LCD Parameter 9
    381   {VIACR,CR83,0xFF,0x19},   // LCD Parameter 10
    382   {VIACR,CR84,0xFF,0x1C},   // LCD Parameter 11
    383   {VIACR,CR85,0xFF,0x1D},   // LCD Parameter 12
    384   {VIACR,CR86,0xFF,0x1E},   // LCD Parameter 13
    385   {VIACR,CR87,0xFF,0x1F},   // LCD Parameter 14
    386 
    387 };
    388 
    389 #define NUM_TOTAL_CLE266_ModeXregs ARRAY_SIZE(CLE266_ModeXregs)
    390 
    391 /* Mode:1024X768 */
    392 struct io_reg PM1024x768[] = {
    393   {VIASR,0x16,0xBF,0x0C},
    394   {VIASR,0x18,0xFF,0x4C}
    395 };
    396 
    397 struct patch_table res_patch_table[]= {
    398   {VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768}
    399 };
    400 #define NUM_TOTAL_PATCH_MODE ARRAY_SIZE(res_patch_table)
    401 
    402 // struct VPITTable {
    403 //  unsigned char  Misc;
    404 //  unsigned char  SR[StdSR];
    405 //  unsigned char  CR[StdCR];
    406 //  unsigned char  GR[StdGR];
    407 //  unsigned char  AR[StdAR];
    408 // };
    409 
    410 struct VPITTable VPIT = {
    411     // Msic
    412     0xC7,
    413     // Sequencer
    414     {0x01,0x0F,0x00,0x0E },
    415     // Graphic Controller
    416     {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF},
    417     // Attribute Controller
    418     {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
    419      0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
    420      0x01,0x00,0x0F,0x00}
    421 };
    422 
    423 /********************/
    424 /* Mode Table       */
    425 /********************/
    426 
    427 // 640x480
    428 struct crt_mode_table CRTM640x480[] = {
    429   //r_rate,vclk,hsp,vsp
    430   //HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    431   {REFRESH_60, CLK_25_175M ,M640X480_R60_HSP, M640X480_R60_VSP,\
    432   {800, 640, 648, 144, 656, 96,  525, 480, 480, 45,  490, 2}},
    433   {REFRESH_75, CLK_31_500M ,M640X480_R75_HSP, M640X480_R75_VSP,\
    434   {840, 640, 640, 200, 656, 64,  500, 480, 480, 20,  481, 3}},
    435   {REFRESH_85, CLK_36_000M ,M640X480_R85_HSP, M640X480_R85_VSP,\
    436   {832, 640, 640, 192, 696, 56,  509, 480, 480, 29,  481, 3}},
    437   {REFRESH_100,CLK_43_163M ,M640X480_R100_HSP, M640X480_R100_VSP,\
    438   {848, 640, 640, 208, 680, 64,  509, 480, 480, 29,  481, 3}}, //GTF
    439   {REFRESH_120,CLK_52_406M ,M640X480_R120_HSP, M640X480_R120_VSP,\
    440   {848, 640, 640, 208, 680, 64,  515, 480, 480, 35,  481, 3}}  //GTF
    441 };
    442 
    443 //720x480 (GTF)
    444 struct crt_mode_table CRTM720x480[] = {
    445   //r_rate,vclk,hsp,vsp
    446   //HT, HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    447   {REFRESH_60,CLK_26_880M ,M720X480_R60_HSP, M720X480_R60_VSP,\
    448   {896, 720, 720, 176, 736, 72,  497, 480, 480, 17,  481, 3}}
    449 
    450 };
    451 
    452 //720x576 (GTF)
    453 struct crt_mode_table CRTM720x576[] = {
    454   //r_rate,vclk,hsp,vsp
    455   //HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    456   {REFRESH_60,CLK_32_668M ,M720X576_R60_HSP, M720X576_R60_VSP,\
    457   {912, 720, 720, 192, 744, 72,  597, 576, 576, 21,  577, 3}}
    458 };
    459 
    460 //800x480 (GTF)
    461 struct crt_mode_table CRTM800x480[] = {
    462   //r_rate,vclk,hsp,vsp
    463   //HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    464   {REFRESH_60,CLK_29_581M ,M800X480_R60_HSP,M800X480_R60_VSP,\
    465   {992, 800, 800, 192, 816, 80,  497, 480, 480, 17,  481, 3}}
    466 };
    467 // 800x600
    468 struct crt_mode_table CRTM800x600[] = {
    469   //r_rate,vclk,hsp,vsp
    470   //HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    471   {REFRESH_60, CLK_40_000M ,M800X600_R60_HSP, M800X600_R60_VSP,\
    472   {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28,  601, 4}},
    473   {REFRESH_75, CLK_49_500M ,M800X600_R75_HSP, M800X600_R75_VSP,\
    474   {1056, 800, 800, 256, 816, 80,  625, 600, 600, 25,  601, 3}},
    475   {REFRESH_85, CLK_56_250M ,M800X600_R85_HSP, M800X600_R85_VSP,\
    476   {1048, 800, 800, 248, 832, 64,  631, 600, 600, 31,  601, 3}},
    477   {REFRESH_100,CLK_68_179M ,M800X600_R100_HSP, M800X600_R100_VSP,\
    478   {1072, 800, 800, 272, 848, 88,  636, 600, 600, 36,  601, 3}}, //GTF
    479   {REFRESH_120,CLK_83_950M ,M800X600_R120_HSP, M800X600_R120_VSP,\
    480   {1088, 800, 800, 288, 856, 88,  643, 600, 600, 43,  601, 3}}  //GTF
    481 };
    482 //848x480 (GTF)
    483 struct crt_mode_table CRTM848x480[] = {
    484   //r_rate,vclk,hsp,vsp
    485   //HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    486   {REFRESH_60,CLK_31_490M ,M848X480_R60_HSP, M848X480_R60_VSP,\
    487   {1056, 848, 848, 208, 864, 88,  497, 480, 480, 17,  481, 3}}
    488 };
    489 
    490 //856x480 (GTF) convert to 852x480
    491 struct crt_mode_table CRTM852x480[] = {
    492   //r_rate,vclk,hsp,vsp
    493   //HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    494   {REFRESH_60,CLK_31_728M ,M852X480_R60_HSP, M852X480_R60_VSP,\
    495   {1064, 856, 856, 208, 872, 88,  497, 480, 480, 17,  481, 3}}
    496 
    497 };
    498 
    499 //1024x512 (GTF)
    500 struct crt_mode_table CRTM1024x512[] = {
    501   //r_rate,vclk,hsp,vsp
    502   //HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    503   {REFRESH_60,CLK_41_291M ,M1024X512_R60_HSP, M1024X512_R60_VSP,\
    504   {1296, 1024,1024,272, 1056,104, 531, 512, 512, 19,  513, 3}}
    505 
    506 };
    507 
    508 //1024x576 (GTF)
    509 /*static struct crt_mode_table CRTM1024x576[] = {
    510   //r_rate,vclk,     HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    511   { 60,CLK_46_996M ,{1312, 1024,1024,288, 1064,104, 597, 576, 576, 21,  577, 3}}
    512 
    513 };*/
    514 
    515 // 1024x768
    516 struct crt_mode_table CRTM1024x768[] = {
    517   //r_rate,vclk,hsp,vsp
    518   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    519   {REFRESH_60,CLK_65_000M ,M1024X768_R60_HSP, M1024X768_R60_VSP,\
    520   {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38,  771, 6}},
    521   {REFRESH_75,CLK_78_750M ,M1024X768_R75_HSP, M1024X768_R75_VSP,\
    522   {1312, 1024, 1024, 288, 1040, 96,  800, 768, 768, 32,  769, 3}},
    523   {REFRESH_85,CLK_94_500M ,M1024X768_R85_HSP, M1024X768_R85_VSP,\
    524   {1376, 1024, 1024, 352, 1072, 96,  808, 768, 768, 40,  769, 3}},
    525   {REFRESH_100,CLK_133_308M,M1024X768_R100_HSP, M1024X768_R100_VSP,\
    526   {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46,  769, 3}} //GTF
    527 };
    528 
    529 // 1152x864
    530 struct crt_mode_table CRTM1152x864[] = {
    531   //r_rate,vclk,hsp,vsp
    532   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    533   {REFRESH_75,CLK_108_000M ,M1152X864_R75_HSP, M1152X864_R75_VSP,\
    534   {1600, 1152,1152, 448, 1216, 128, 900, 864, 864, 36,  865, 3}}
    535 
    536 };
    537 
    538 // 1280x720 (GTF)
    539 struct crt_mode_table CRTM1280x720[] = {
    540   //r_rate,vclk,hsp,vsp
    541   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    542   {REFRESH_60,CLK_74_481M ,M1280X720_R60_HSP, M1280X720_R60_VSP,\
    543   {1664,1280, 1280, 384, 1336, 136, 746, 720, 720, 26,  721, 3}}
    544 };
    545 
    546 //1280x768 (GTF)
    547 struct crt_mode_table CRTM1280x768[] = {
    548   //r_rate,vclk,hsp,vsp
    549   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    550   {REFRESH_60,CLK_80_136M ,M1280X768_R60_HSP, M1280X768_R60_VSP,\
    551   {1680,1280, 1280, 400, 1344, 136, 795, 768, 768, 27,  769, 3}}
    552 };
    553 
    554 //1280x960
    555 struct crt_mode_table CRTM1280x960[] = {
    556   //r_rate,vclk,hsp,vsp
    557   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    558   {REFRESH_60,CLK_108_000M ,M1280X960_R60_HSP, M1280X960_R60_VSP,\
    559   {1800,1280, 1280, 520, 1376, 112, 1000,960, 960, 40,  961, 3}}
    560 };
    561 
    562 // 1280x1024
    563 struct crt_mode_table CRTM1280x1024[] = {
    564   //r_rate,vclk,,hsp,vsp
    565   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    566   {REFRESH_60,CLK_108_000M ,M1280X1024_R60_HSP, M1280X1024_R60_VSP,\
    567   {1688,1280, 1280, 408, 1328, 112, 1066,1024,1024,42,  1025,3}},
    568   {REFRESH_75,CLK_135_000M ,M1280X1024_R75_HSP, M1280X1024_R75_VSP,\
    569   {1688,1280, 1280, 408, 1296, 144, 1066,1024,1024,42,  1025,3}},
    570   {REFRESH_85,CLK_157_500M ,M1280X1024_R85_HSP, M1280X1024_R85_VSP,\
    571   {1728,1280, 1280, 448, 1344, 160, 1072,1024,1024,48,  1025,3}}
    572 };
    573 
    574 /* 1366x768 (GTF) */
    575 struct crt_mode_table CRTM1366x768[] = {
    576   // r_rate,  vclk, hsp, vsp
    577   // HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE
    578   {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,\
    579   {1800,1366, 1366, 432, 1440, 144, 795, 768, 768, 27,  769, 3}}
    580 };
    581 
    582 //1368x768 (GTF)
    583 /*static struct crt_mode_table CRTM1368x768[] = {
    584   //r_rate,vclk,     HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    585   { 60,CLK_85_860M ,{1800,1368, 1368, 432, 1440, 144, 795, 768, 768, 27,  769, 3}}
    586 };*/
    587 
    588 //1440x1050 (GTF)
    589 struct crt_mode_table CRTM1440x1050[] = {
    590   //r_rate,vclk,hsp,vsp
    591   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    592   {REFRESH_60 ,CLK_125_104M ,M1440X1050_R60_HSP, M1440X1050_R60_VSP,\
    593   {1936,1440, 1440, 496, 1536, 152, 1077,1040,1040,37,  1041,3}}
    594 };
    595 
    596 // 1600x1200
    597 struct crt_mode_table CRTM1600x1200[] = {
    598   //r_rate,vclk,hsp,vsp
    599   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    600   {REFRESH_60 ,CLK_162_000M ,M1600X1200_R60_HSP, M1600X1200_R60_VSP,\
    601   {2160,1600, 1600, 560, 1664, 192, 1250,1200,1200,50,  1201,3}},
    602   {REFRESH_75 ,CLK_202_500M ,M1600X1200_R75_HSP, M1600X1200_R75_VSP,\
    603   {2160,1600, 1600, 560, 1664, 192, 1250,1200,1200,50,  1201,3}}
    604 
    605 };
    606 
    607 // 1920x1080 (GTF)
    608 struct crt_mode_table CRTM1920x1080[] = {
    609   //r_rate,vclk,hsp,vsp
    610   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    611   {REFRESH_60,CLK_172_798M ,M1920X1080_R60_HSP, M1920X1080_R60_VSP,\
    612   {2576,1920, 1920, 656, 2040, 208, 1118,1080,1080,38, 1081, 3}}
    613 };
    614 
    615 // 1920x1440
    616 struct crt_mode_table CRTM1920x1440[] = {
    617   //r_rate,vclk,hsp,vsp
    618   //HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE
    619   {REFRESH_60,CLK_234_000M ,M1920X1440_R60_HSP, M1920X1440_R60_VSP,\
    620   {2600,1920, 1920, 680, 2048, 208, 1500,1440,1440,60,  1441,3}},
    621   {REFRESH_75,CLK_297_500M ,M1920X1440_R75_HSP, M1920X1440_R75_VSP,\
    622   {2640,1920, 1920, 720, 2064, 224, 1500,1440,1440,60,  1441,3}}
    623 };
    624 
    625 /* 1400x1050 (VESA) */
    626 struct crt_mode_table CRTM1400x1050[] = {
    627   /* r_rate,          vclk,              hsp,             vsp   */
    628   /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
    629   {REFRESH_60,CLK_108_000M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
    630   {1688,1400, 1400, 288, 1448, 112, 1066,1050, 1050,  16, 1051, 3}}
    631 };
    632 
    633 /* Video Mode Table */
    634 // struct VideoModeTable {
    635 //  int                               ModeIndex;
    636 //  struct crt_mode_table             *crtc;
    637 //  int                               mode_array;
    638 // };
    639 struct VideoModeTable CLE266Modes[] = {
    640    /* Display : 640x480 */
    641    { VIA_RES_640X480,  CRTM640x480, ARRAY_SIZE(CRTM640x480)},
    642 
    643    /* Display : 720x480 (GTF)*/
    644    { VIA_RES_720X480,  CRTM720x480, ARRAY_SIZE(CRTM720x480)},
    645 
    646    /* Display : 720x576 (GTF)*/
    647    { VIA_RES_720X576,  CRTM720x576, ARRAY_SIZE(CRTM720x576)},
    648 
    649    /* Display : 800x600 */
    650    { VIA_RES_800X600,  CRTM800x600, ARRAY_SIZE(CRTM800x600)},
    651 
    652    /* Display : 800x480 (GTF)*/
    653    { VIA_RES_800X480,  CRTM800x480, ARRAY_SIZE(CRTM800x480)},
    654 
    655    /* Display : 848x480 (GTF)*/
    656    { VIA_RES_848X480,  CRTM848x480, ARRAY_SIZE(CRTM848x480)},
    657 
    658    /* Display : 852x480 (GTF)*/
    659    { VIA_RES_856X480,  CRTM852x480, ARRAY_SIZE(CRTM852x480)},
    660 
    661    /* Display : 1024x512 (GTF)*/
    662    { VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
    663 
    664     /* Display : 1024x576 (GTF)*/
    665    //{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
    666 
    667    /* Display : 1024x768 */
    668    { VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
    669 
    670    /* Display : 1152x864 */
    671    { VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
    672 
    673    /* Display : 1280x768 (GTF)*/
    674    { VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
    675 
    676    /* Display : 1280x800 (GTF)*/
    677    //{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
    678 
    679    /* Display : 1280x960 */
    680    { VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
    681 
    682    /* Display : 1280x1024 */
    683    { VIA_RES_1280X1024, CRTM1280x1024,ARRAY_SIZE(CRTM1280x1024)},
    684 
    685    /* Display : 1368x768 (GTF)*/
    686    //{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)},
    687 /* Display : 1366x768 (GTF)*/
    688    { VIA_RES_1366X768,CRTM1366x768,ARRAY_SIZE(CRTM1366x768)},
    689 
    690    /* Display : 1440x1050 (GTF)*/
    691    { VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
    692 
    693    /* Display : 1600x1200 */
    694    { VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
    695 
    696    /* Display : 1920x1440 */
    697    { VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
    698 
    699    /* Display : 1280x720 */
    700    { VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
    701 
    702    /* Display : 1920x1080 */
    703    { VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
    704 
    705    /* Display : 1400x1050 */
    706    { VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
    707 };
    708 
    709 #define NUM_TOTAL_MODETABLE ARRAY_SIZE(CLE266Modes)
    710 
    711 
    712 #endif /* _DEV_PCI_UNICHROMEMODE_H */
    713