| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.disasm/ |
| mn10200.s | 205 ror d1 define
|
| mn10300.s | 289 ror d1 define
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.disasm/ |
| mn10200.s | 205 ror d1 define
|
| mn10300.s | 289 ror d1 define
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 32 ror, enumerator in enum:llvm::ARM_AM::ShiftOpc
50 case ARM_AM::ror: return "ror";
62 case ARM_AM::ror: return 3;
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /src/external/gpl3/gdb/dist/sim/arm/ |
| thumbemu.c | 142 int ror = tBITS (7, 11); local
145 val = (val >> ror) | (val << (32 - ror));
498 // ROR{S}<c> <Rd>,<Rm>,#<imm>
1564 ARMword ror = ntBITS (4, 5) << 3; local
1568 val = (val >> ror) | (val << (32 - ror));
1629 case 0xD3: // ROR{S}<c>.W <Rd>,<Rn>,<Rm>
2147 { 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
2170 { 0xE1A00070, t_shift}, /* MOV Rd,Rd,ROR Rs *
[all...] |
| armemu.c | 712 int ror = -1; local
716 case 0x07: ror = 0; break;
717 case 0x47: ror = 8; break;
718 case 0x87: ror = 16; break;
719 case 0xc7: ror = 24; break;
730 if (ror == -1)
740 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
755 int ror = -1; local
759 case 0x07: ror = 0; break;
760 case 0x47: ror = 8; break
837 int ror = -1; local
879 int ror = -1; local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| thumbemu.c | 142 int ror = tBITS (7, 11); local
145 val = (val >> ror) | (val << (32 - ror));
498 // ROR{S}<c> <Rd>,<Rm>,#<imm>
1564 ARMword ror = ntBITS (4, 5) << 3; local
1568 val = (val >> ror) | (val << (32 - ror));
1629 case 0xD3: // ROR{S}<c>.W <Rd>,<Rn>,<Rm>
2147 { 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
2170 { 0xE1A00070, t_shift}, /* MOV Rd,Rd,ROR Rs *
[all...] |
| armemu.c | 712 int ror = -1; local
716 case 0x07: ror = 0; break;
717 case 0x47: ror = 8; break;
718 case 0x87: ror = 16; break;
719 case 0xc7: ror = 24; break;
730 if (ror == -1)
740 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
755 int ror = -1; local
759 case 0x07: ror = 0; break;
760 case 0x47: ror = 8; break
837 int ror = -1; local
879 int ror = -1; local
[all...] |
| /src/external/gpl3/gdb/dist/sim/ft32/ |
| interp.c | 289 static uint32_t ror (uint32_t n, uint32_t b) function
434 case 0x1: result = ror (r_1v, rimmv); break;
|
| /src/external/gpl3/gdb.old/dist/sim/ft32/ |
| interp.c | 289 static uint32_t ror (uint32_t n, uint32_t b) function
434 case 0x1: result = ror (r_1v, rimmv); break;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 37 ROR,
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
94 /// 011 ==> ror
107 case AArch64_AM::ROR: STEnc = 3; break;
205 static inline uint64_t ror(uint64_t elt, unsigned size) { function in namespace:llvm::AArch64_AM
308 pattern = ror(pattern, size);
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-s12z.c | 1860 ror (const struct instruction *insn)
3234 {"ror", 1, 0x10, ror, 0},
3235 {"ror.b", 1, 0x10, ror, 0},
3236 {"ror.w", 1, 0x10, ror, 0},
3237 {"ror.p", 1, 0x10, ror, 0},
3238 {"ror.l", 1, 0x10, ror, 0}
1853 ror (const struct instruction *insn) function
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-s12z.c | 1860 ror (const struct instruction *insn)
3234 {"ror", 1, 0x10, ror, 0},
3235 {"ror.b", 1, 0x10, ror, 0},
3236 {"ror.w", 1, 0x10, ror, 0},
3237 {"ror.p", 1, 0x10, ror, 0},
3238 {"ror.l", 1, 0x10, ror, 0}
1853 ror (const struct instruction *insn) function
[all...] |
