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    Searched defs:rs1 (Results 1 - 25 of 30) sorted by relevancy

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  /src/sys/arch/riscv/riscv/
db_machdep.c 188 register_t rs1 = get_reg_value(tf, i.type_b.b_rs1); local
193 branch_p = (rs1 == rs2);
196 branch_p = ((rs1 & (1 << (i.type_b.b_rs2))) != 0);
199 branch_p = (rs1 < rs2);
203 branch_p = ((uregister_t)rs1 < (uregister_t)rs2);
db_disasm.c 140 unsigned rd, rs1, rs2; local
153 rs1 = INSN16_RS1x(insn);
158 riscv_registers[rs1]);
162 (int32_t)imm, riscv_registers[rs1]);
166 rs1 = INSN16_RS1x(insn);
170 (int32_t)imm, riscv_registers[rs1]);
173 rs1 = INSN16_RS1x(insn);
178 riscv_registers[rs1]);
182 (int32_t)imm, riscv_registers[rs1]);
186 rs1 = INSN16_RS1x(insn)
    [all...]
  /src/sys/arch/sparc/fpu/
fpu.c 305 int opf, rs1, rs2, rd, type, mask, fsr, cx; local
308 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; local
337 rs1 = instr.i_opf.i_rs1;
338 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5);
344 if ((rs1 | rs2 | rd) & mask)
362 rs1 = fs->fs_regs[rs2];
368 rs1 = fs->fs_regs[rs2];
374 rs1 = fs->fs_regs[rs2]
    [all...]
  /src/sys/arch/sparc/sparc/
emul.c 134 union instr *code, int32_t *rd, int32_t *rs1, int32_t *rs2)
173 * ignore the error and return *rd = *rs1.
180 *rd = *rs1 / *rs2;
181 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
184 *rd = *rs1 * *rs2;
185 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
198 if (*rd * *rs2 != *rs1)
202 if (*rd / *rs2 != *rs1)
248 int32_t rs1, rs2; local
274 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0)
388 int32_t rs1, rs2, rd; local
    [all...]
  /src/sys/arch/sparc64/sparc64/
emul.c 132 muldiv(struct trapframe64 *tf, union instr *code, int32_t *rd, int32_t *rs1,
172 * ignore the error and return *rd = *rs1.
179 *rd = *rs1 / *rs2;
180 DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
183 *rd = *rs1 * *rs2;
184 DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
197 if (*rd * *rs2 != *rs1)
201 if (*rd / *rs2 != *rs1)
245 int64_t rs1, rs2; local
271 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0)
380 int32_t rs1, rs2, rd; local
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
SparcDisassembler.cpp 374 unsigned rs1 = fieldFromInstruction(insn, 14, 5); local
392 // Decode rs1.
393 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
531 unsigned rs1 = fieldFromInstruction(insn, 14, 5); local
545 // Decode RS1.
546 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
550 // Decode RS1 | SIMM13.
564 unsigned rs1 = fieldFromInstruction(insn, 14, 5); local
573 // Decode RS1.
574 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder)
593 unsigned rs1 = fieldFromInstruction(insn, 14, 5); local
632 unsigned rs1 = fieldFromInstruction(insn, 14, 5); local
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
dlx-dis.c 39 unsigned char opc, rs1, rs2, rd; variable
171 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
222 (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
256 (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
313 (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
350 (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
423 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
464 rs1 = dlx_get_rs1 (insn_word);
473 " rs1 = 0x%02x\n"
479 opc, rs1, rs2, rd, func, imm16, imm26)
    [all...]
riscv-opc.c 196 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
198 return match_opcode (op, insn) && rs1 == rs2;
367 * The values of rd and rs1 must not be the same. */
369 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
371 return rd != rs1 && match_opcode (op, insn);
381 * - rs = RS1 ([19:15])
383 * The values of rd1, rd2, and rs1 must not be the same. */
431 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
432 return match_opcode (op, insn) && (rs1 == 1 || rs1 == 5)
    [all...]
riscv-dis.c 306 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; local
322 case 's': /* RS1 x8-x15. */
323 case 'w': /* RS1 x8-x15. */
332 case 'U': /* RS1, constrained to equal RD. */
336 case 'c': /* RS1, constrained to equal sp. */
523 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
525 pd->riscv_gpr_names[rs1]);
554 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
557 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
559 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0)
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
dlx-dis.c 39 unsigned char opc, rs1, rs2, rd; variable
171 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
222 (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
256 (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
313 (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
350 (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
423 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
464 rs1 = dlx_get_rs1 (insn_word);
473 " rs1 = 0x%02x\n"
479 opc, rs1, rs2, rd, func, imm16, imm26)
    [all...]
riscv-opc.c 196 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
198 return match_opcode (op, insn) && rs1 == rs2;
375 * The values of rd and rs1 must not be the same. */
377 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
379 return rd != rs1 && match_opcode (op, insn);
389 * - rs = RS1 ([19:15])
391 * The values of rd1, rd2, and rs1 must not be the same. */
439 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
440 return match_opcode (op, insn) && (rs1 == 1 || rs1 == 5)
    [all...]
riscv-dis.c 306 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; local
322 case 's': /* RS1 x8-x15. */
323 case 'w': /* RS1 x8-x15. */
332 case 'U': /* RS1, constrained to equal RD. */
336 case 'c': /* RS1, constrained to equal sp. */
523 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
525 pd->riscv_gpr_names[rs1]);
554 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
557 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
559 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0)
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
dlx-dis.c 39 unsigned char opc, rs1, rs2, rd; variable
171 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
222 (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
256 (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
313 (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
350 (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
423 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
464 rs1 = dlx_get_rs1 (insn_word);
473 " rs1 = 0x%02x\n"
479 opc, rs1, rs2, rd, func, imm16, imm26)
    [all...]
riscv-opc.c 195 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
197 return match_opcode (op, insn) && rs1 == rs2;
334 * The values of rd and rs1 must not be the same. */
336 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
338 return rd != rs1 && match_opcode (op, insn);
348 * - rs = RS1 ([19:15])
350 * The values of rd1, rd2, and rs1 must not be the same. */
riscv-dis.c 310 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; local
326 case 's': /* RS1 x8-x15. */
327 case 'w': /* RS1 x8-x15. */
336 case 'U': /* RS1, constrained to equal RD. */
340 case 'c': /* RS1, constrained to equal sp. */
522 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
523 print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
552 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
555 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
557 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0)
    [all...]
  /src/external/gpl3/gdb/dist/sim/riscv/
sim-main.c 161 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
164 const char *rs1_name = riscv_gpr_names_abi[rs1];
177 "rs1:%-2i:%-4s %0*" PRIxTW " "
181 rs1, rs1_name, (int) sizeof (unsigned_word) * 2,
182 riscv_cpu->regs[rs1],
192 store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]);
199 EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
204 store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm);
210 store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
215 store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2])
159 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; local
689 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; local
841 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; local
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
dlx-dis.c 39 unsigned char opc, rs1, rs2, rd; variable
171 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
222 (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
256 (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
313 (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
350 (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
423 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
464 rs1 = dlx_get_rs1 (insn_word);
473 " rs1 = 0x%02x\n"
479 opc, rs1, rs2, rd, func, imm16, imm26)
    [all...]
riscv-opc.c 195 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
197 return match_opcode (op, insn) && rs1 == rs2;
326 * The values of rd and rs1 must not be the same. */
328 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; local
330 return rd != rs1 && match_opcode (op, insn);
340 * - rs = RS1 ([19:15])
342 * The values of rd1, rd2, and rs1 must not be the same. */
riscv-dis.c 266 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; local
282 case 's': /* RS1 x8-x15. */
283 case 'w': /* RS1 x8-x15. */
292 case 'U': /* RS1, constrained to equal RD. */
296 case 'c': /* RS1, constrained to equal sp. */
478 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
479 print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
508 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
511 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
513 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0)
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/riscv/
sim-main.c 161 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
164 const char *rs1_name = riscv_gpr_names_abi[rs1];
177 "rs1:%-2i:%-4s %0*" PRIxTW " "
181 rs1, rs1_name, (int) sizeof (unsigned_word) * 2,
182 riscv_cpu->regs[rs1],
192 store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]);
199 EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
204 store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm);
210 store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
215 store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2])
159 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; local
689 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; local
841 int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; local
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
tc-dlx.c 327 char rs1[7], rd[7], endm, match = '0'; local
343 rs1[0] = 'r';
344 rs1[1] = '0';
345 rs1[2] = '\0';
363 rs1[i] = str[pb+i];
365 rs1[i] = '\0';
367 if (is_ldst_registers (& rs1[0]))
376 rs1[0] = 'r';
377 rs1[1] = '0';
378 rs1[2] = '\0'
443 char rs1[7], rd[7], endm, match = '0'; local
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-dlx.c 327 char rs1[7], rd[7], endm, match = '0'; local
343 rs1[0] = 'r';
344 rs1[1] = '0';
345 rs1[2] = '\0';
363 rs1[i] = str[pb+i];
365 rs1[i] = '\0';
367 if (is_ldst_registers (& rs1[0]))
376 rs1[0] = 'r';
377 rs1[1] = '0';
378 rs1[2] = '\0'
443 char rs1[7], rd[7], endm, match = '0'; local
    [all...]
  /src/sys/dev/ic/
isp.c 3349 sns_gid_ft_rsp_t *rs0, *rs1; local
3422 rs1 = (sns_gid_ft_rsp_t *) ((uint8_t *)fcp->isp_scratch+OGPOFF);
3423 isp_get_gid_ft_response(isp, rs0, rs1, NGENT);
3429 if (rs1->snscb_cthdr.ct_cmd_resp != LS_ACC) {
3431 if (rs1->snscb_cthdr.ct_reason == 9 &&
3432 rs1->snscb_cthdr.ct_explanation == 7) {
3439 rs1->snscb_cthdr.ct_reason,
3440 rs1->snscb_cthdr.ct_explanation);
3464 if (rs1->snscb_ports[portidx].control & 0x80) {
3472 if ((rs1->snscb_ports[portidx].control & 0x80) == 0)
    [all...]
  /src/external/gpl3/gdb/dist/sim/erc32/
exec.c 226 static int fpexec (uint32_t op3, uint32_t rd, uint32_t rs1, uint32_t rs2,
396 uint32_t cwp, op, op2, op3, asi, rd, cond, rs1, local
409 op3 = rd = rs1 = operand2 = eicc = 0;
414 rs1 = (sregs->inst >> 14) & 0x1f;
425 if (ldep && (sregs->ildreg == rs1))
435 if (ldep && ((sregs->ildreg == rs1) || (sregs->ildreg == rs2)))
455 if (rs1 > 7)
456 rs1 = sregs->r[(cwp + rs1) & 0x7f];
458 rs1 = sregs->g[rs1]
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/erc32/
exec.c 226 static int fpexec (uint32_t op3, uint32_t rd, uint32_t rs1, uint32_t rs2,
396 uint32_t cwp, op, op2, op3, asi, rd, cond, rs1, local
409 op3 = rd = rs1 = operand2 = eicc = 0;
414 rs1 = (sregs->inst >> 14) & 0x1f;
425 if (ldep && (sregs->ildreg == rs1))
435 if (ldep && ((sregs->ildreg == rs1) || (sregs->ildreg == rs2)))
455 if (rs1 > 7)
456 rs1 = sregs->r[(cwp + rs1) & 0x7f];
458 rs1 = sregs->g[rs1]
    [all...]

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