| /src/sys/dev/pci/ixgbe/ |
| ixgbe_x550.c | 3911 u32 rxctrl, pfdtxgswc; local in function:ixgbe_disable_rx_x550
3917 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3918 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3939 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3940 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3941 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3942 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
|
| ixgbe.c | 4057 u32 rxdctl, rxctrl; local in function:ixgbe_init_locked
4214 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4216 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4217 rxctrl |= IXGBE_RXCTRL_RXEN;
4218 ixgbe_enable_rx_dma(hw, rxctrl);
|
| ixgbe_common.c | 3466 * @regval: register value to write to RXCTRL
4892 * should the link come up. This assumes that the RXCTRL.RXEN bit
5309 u32 rxctrl; local in function:ixgbe_disable_rx_generic
5311 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5312 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5323 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5324 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5331 u32 rxctrl; local in function:ixgbe_enable_rx_generic
5333 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5334 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN))
[all...] |
| /src/sys/dev/ic/ |
| malo.c | 83 uint8_t rxctrl; member in struct:malo_rx_desc
1536 DPRINTF(3, "%s: rx intr idx=%d, rxctrl=0x%02x, rssi=%d, "
1540 sc->sc_rxring.cur, desc->rxctrl, desc->rssi, desc->status,
1545 if ((desc->rxctrl & 0x80) == 0)
1630 desc->rxctrl = 0;
|
