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/src/sys/arch/arm/amlogic/
meson_clk_mpll.c	47 uint64_t parent_rate, sdm, n2; local in function:meson_clk_mpll_get_rate 63 val = CLK_READ(sc, mpll->sdm.reg); 64 sdm = __SHIFTOUT(val, mpll->sdm.mask); 71 const uint64_t div = (SDM_DEN * n2) + sdm;
meson_clk.h	302 struct meson_clk_pll_reg sdm; member in struct:meson_clk_mpll 321 .u.mpll.sdm = _sdm, \

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