1 /* $NetBSD: if_sk.c,v 1.114 2025/10/04 04:44:21 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.114 2025/10/04 04:44:21 thorpej Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 static int skc_probe(device_t, cfdata_t, void *); 157 static void skc_attach(device_t, device_t, void *); 158 static int sk_probe(device_t, cfdata_t, void *); 159 static void sk_attach(device_t, device_t, void *); 160 static int skcprint(void *, const char *); 161 static int sk_intr(void *); 162 static void sk_intr_bcom(struct sk_if_softc *); 163 static void sk_intr_xmac(struct sk_if_softc *); 164 static void sk_intr_yukon(struct sk_if_softc *); 165 static void sk_rxeof(struct sk_if_softc *); 166 static void sk_txeof(struct sk_if_softc *); 167 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 static void sk_start(struct ifnet *); 169 static int sk_ioctl(struct ifnet *, u_long, void *); 170 static int sk_init(struct ifnet *); 171 static void sk_unreset_xmac(struct sk_if_softc *); 172 static void sk_init_xmac(struct sk_if_softc *); 173 static void sk_unreset_yukon(struct sk_if_softc *); 174 static void sk_init_yukon(struct sk_if_softc *); 175 static void sk_stop(struct ifnet *, int); 176 static void sk_watchdog(struct ifnet *); 177 static int sk_ifmedia_upd(struct ifnet *); 178 static void sk_reset(struct sk_softc *); 179 static int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 180 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 181 static void *sk_jalloc(struct sk_if_softc *); 182 static void sk_jfree(struct mbuf *, void *, size_t, void *); 183 static int sk_init_rx_ring(struct sk_if_softc *); 184 static int sk_init_tx_ring(struct sk_if_softc *); 185 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 187 static void sk_vpd_read(struct sk_softc *); 188 189 static void sk_update_int_mod(struct sk_softc *); 190 191 static int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 192 static int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 193 static void sk_xmac_miibus_statchg(struct ifnet *); 194 195 static int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 196 static int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 197 static void sk_marv_miibus_statchg(struct ifnet *); 198 199 static uint32_t sk_xmac_hash(void *); 200 static uint32_t sk_yukon_hash(void *); 201 static void sk_setfilt(struct sk_if_softc *, void *, int); 202 static void sk_setmulti(struct sk_if_softc *); 203 static void sk_tick(void *); 204 205 static bool skc_suspend(device_t, const pmf_qual_t *); 206 static bool skc_resume(device_t, const pmf_qual_t *); 207 static bool sk_resume(device_t dv, const pmf_qual_t *); 208 209 /* #define SK_DEBUG 2 */ 210 #ifdef SK_DEBUG 211 #define DPRINTF(x) if (skdebug) printf x 212 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 213 int skdebug = SK_DEBUG; 214 215 static void sk_dump_txdesc(struct sk_tx_desc *, int); 216 static void sk_dump_mbuf(struct mbuf *); 217 static void sk_dump_bytes(const char *, int); 218 #else 219 #define DPRINTF(x) 220 #define DPRINTFN(n, x) 221 #endif 222 223 static int sk_sysctl_handler(SYSCTLFN_PROTO); 224 static int sk_root_num; 225 226 /* supported device vendors */ 227 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 228 static const struct device_compatible_entry compat_data[] = { 229 { .id = PCI_ID_CODE(PCI_VENDOR_3COM, 230 PCI_PRODUCT_3COM_3C940) }, 231 232 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK, 233 PCI_PRODUCT_DLINK_DGE530T) }, 234 235 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK, 236 PCI_PRODUCT_DLINK_DGE560T_2) }, 237 238 { .id = PCI_ID_CODE(PCI_VENDOR_LINKSYS, 239 PCI_PRODUCT_LINKSYS_EG1064) }, 240 241 { .id = PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 242 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE) }, 243 244 { .id = PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 245 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2) }, 246 247 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL, 248 PCI_PRODUCT_MARVELL_SKNET) }, 249 250 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL, 251 PCI_PRODUCT_MARVELL_BELKIN) }, 252 253 PCI_COMPAT_EOL 254 }; 255 256 #define SK_LINKSYS_EG1032_SUBID 0x00151737 257 258 static inline uint32_t 259 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 260 { 261 #ifdef SK_USEIOSPACE 262 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 263 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 264 #else 265 return CSR_READ_4(sc, reg); 266 #endif 267 } 268 269 static inline uint16_t 270 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 271 { 272 #ifdef SK_USEIOSPACE 273 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 274 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 275 #else 276 return CSR_READ_2(sc, reg); 277 #endif 278 } 279 280 static inline uint8_t 281 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 282 { 283 #ifdef SK_USEIOSPACE 284 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 285 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 286 #else 287 return CSR_READ_1(sc, reg); 288 #endif 289 } 290 291 static inline void 292 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 293 { 294 #ifdef SK_USEIOSPACE 295 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 296 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 297 #else 298 CSR_WRITE_4(sc, reg, x); 299 #endif 300 } 301 302 static inline void 303 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 304 { 305 #ifdef SK_USEIOSPACE 306 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 307 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 308 #else 309 CSR_WRITE_2(sc, reg, x); 310 #endif 311 } 312 313 static inline void 314 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 315 { 316 #ifdef SK_USEIOSPACE 317 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 318 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 319 #else 320 CSR_WRITE_1(sc, reg, x); 321 #endif 322 } 323 324 /* 325 * The VPD EEPROM contains Vital Product Data, as suggested in 326 * the PCI 2.1 specification. The VPD data is separated into areas 327 * denoted by resource IDs. The SysKonnect VPD contains an ID string 328 * resource (the name of the adapter), a read-only area resource 329 * containing various key/data fields and a read/write area which 330 * can be used to store asset management information or log messages. 331 * We read the ID string and read-only into buffers attached to 332 * the controller softc structure for later use. At the moment, 333 * we only use the ID string during sk_attach(). 334 */ 335 static uint8_t 336 sk_vpd_readbyte(struct sk_softc *sc, int addr) 337 { 338 int i; 339 340 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 341 for (i = 0; i < SK_TIMEOUT; i++) { 342 DELAY(1); 343 if (sk_win_read_2(sc, 344 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 345 break; 346 } 347 348 if (i == SK_TIMEOUT) 349 return 0; 350 351 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 352 } 353 354 static void 355 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 356 { 357 int i; 358 uint8_t *ptr; 359 360 ptr = (uint8_t *)res; 361 for (i = 0; i < sizeof(struct vpd_res); i++) 362 ptr[i] = sk_vpd_readbyte(sc, i + addr); 363 } 364 365 static void 366 sk_vpd_read(struct sk_softc *sc) 367 { 368 int pos = 0, i; 369 struct vpd_res res; 370 371 if (sc->sk_vpd_prodname != NULL) 372 free(sc->sk_vpd_prodname, M_DEVBUF); 373 if (sc->sk_vpd_readonly != NULL) 374 free(sc->sk_vpd_readonly, M_DEVBUF); 375 sc->sk_vpd_prodname = NULL; 376 sc->sk_vpd_readonly = NULL; 377 378 sk_vpd_read_res(sc, &res, pos); 379 380 if (res.vr_id != VPD_RES_ID) { 381 aprint_error_dev(sc->sk_dev, 382 "bad VPD resource id: expected %x got %x\n", 383 VPD_RES_ID, res.vr_id); 384 return; 385 } 386 387 pos += sizeof(res); 388 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_WAITOK); 389 for (i = 0; i < res.vr_len; i++) 390 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 391 sc->sk_vpd_prodname[i] = '\0'; 392 pos += i; 393 394 sk_vpd_read_res(sc, &res, pos); 395 396 if (res.vr_id != VPD_RES_READ) { 397 aprint_error_dev(sc->sk_dev, 398 "bad VPD resource id: expected %x got %x\n", 399 VPD_RES_READ, res.vr_id); 400 return; 401 } 402 403 pos += sizeof(res); 404 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_WAITOK); 405 for (i = 0; i < res.vr_len ; i++) 406 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 407 } 408 409 static int 410 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 411 { 412 struct sk_if_softc *sc_if = device_private(dev); 413 int i; 414 415 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 416 417 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 418 return -1; 419 420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 421 SK_XM_READ_2(sc_if, XM_PHY_DATA); 422 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 423 for (i = 0; i < SK_TIMEOUT; i++) { 424 DELAY(1); 425 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 426 XM_MMUCMD_PHYDATARDY) 427 break; 428 } 429 430 if (i == SK_TIMEOUT) { 431 aprint_error_dev(sc_if->sk_dev, 432 "phy failed to come ready\n"); 433 return ETIMEDOUT; 434 } 435 } 436 DELAY(1); 437 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 438 return 0; 439 } 440 441 static int 442 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 443 { 444 struct sk_if_softc *sc_if = device_private(dev); 445 int i; 446 447 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 448 449 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 450 for (i = 0; i < SK_TIMEOUT; i++) { 451 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 452 break; 453 } 454 455 if (i == SK_TIMEOUT) { 456 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 457 return ETIMEDOUT; 458 } 459 460 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 461 for (i = 0; i < SK_TIMEOUT; i++) { 462 DELAY(1); 463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 464 break; 465 } 466 467 if (i == SK_TIMEOUT) { 468 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 469 return ETIMEDOUT; 470 } 471 472 return 0; 473 } 474 475 static void 476 sk_xmac_miibus_statchg(struct ifnet *ifp) 477 { 478 struct sk_if_softc *sc_if = ifp->if_softc; 479 struct mii_data *mii = &sc_if->sk_mii; 480 481 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 482 483 /* 484 * If this is a GMII PHY, manually set the XMAC's 485 * duplex mode accordingly. 486 */ 487 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 488 if ((mii->mii_media_active & IFM_FDX) != 0) 489 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 490 else 491 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 492 } 493 } 494 495 static int 496 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 497 { 498 struct sk_if_softc *sc_if = device_private(dev); 499 uint16_t data; 500 int i; 501 502 if (phy != 0 || 503 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 504 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 505 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 506 phy, reg)); 507 return -1; 508 } 509 510 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 511 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 512 513 for (i = 0; i < SK_TIMEOUT; i++) { 514 DELAY(1); 515 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 516 if (data & YU_SMICR_READ_VALID) 517 break; 518 } 519 520 if (i == SK_TIMEOUT) { 521 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 522 return ETIMEDOUT; 523 } 524 525 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 526 SK_TIMEOUT)); 527 528 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 529 530 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 531 phy, reg, *val)); 532 533 return 0; 534 } 535 536 static int 537 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 538 { 539 struct sk_if_softc *sc_if = device_private(dev); 540 int i; 541 542 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 543 phy, reg, val)); 544 545 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 546 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 547 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 548 549 for (i = 0; i < SK_TIMEOUT; i++) { 550 DELAY(1); 551 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 552 break; 553 } 554 555 if (i == SK_TIMEOUT) { 556 printf("%s: phy write timed out\n", 557 device_xname(sc_if->sk_dev)); 558 return ETIMEDOUT; 559 } 560 561 return 0; 562 } 563 564 static void 565 sk_marv_miibus_statchg(struct ifnet *ifp) 566 { 567 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 568 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 569 YUKON_GPCR))); 570 } 571 572 static uint32_t 573 sk_xmac_hash(void *addr) 574 { 575 uint32_t crc; 576 577 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 578 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 579 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 580 return crc; 581 } 582 583 static uint32_t 584 sk_yukon_hash(void *addr) 585 { 586 uint32_t crc; 587 588 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 589 crc &= ((1 << SK_HASH_BITS) - 1); 590 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 591 return crc; 592 } 593 594 static void 595 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 596 { 597 char *addr = addrv; 598 int base = XM_RXFILT_ENTRY(slot); 599 600 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 601 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 602 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 603 } 604 605 static void 606 sk_setmulti(struct sk_if_softc *sc_if) 607 { 608 struct sk_softc *sc = sc_if->sk_softc; 609 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 610 uint32_t hashes[2] = { 0, 0 }; 611 int h = 0, i; 612 struct ethercom *ec = &sc_if->sk_ethercom; 613 struct ether_multi *enm; 614 struct ether_multistep step; 615 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 616 617 /* First, zot all the existing filters. */ 618 switch (sc->sk_type) { 619 case SK_GENESIS: 620 for (i = 1; i < XM_RXFILT_MAX; i++) 621 sk_setfilt(sc_if, (void *)&dummy, i); 622 623 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 624 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 625 break; 626 case SK_YUKON: 627 case SK_YUKON_LITE: 628 case SK_YUKON_LP: 629 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 630 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 631 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 632 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 633 break; 634 } 635 636 /* Now program new ones. */ 637 allmulti: 638 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 639 hashes[0] = 0xFFFFFFFF; 640 hashes[1] = 0xFFFFFFFF; 641 } else { 642 i = 1; 643 /* First find the tail of the list. */ 644 ETHER_LOCK(ec); 645 ETHER_FIRST_MULTI(step, ec, enm); 646 while (enm != NULL) { 647 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 648 ETHER_ADDR_LEN)) { 649 ifp->if_flags |= IFF_ALLMULTI; 650 ETHER_UNLOCK(ec); 651 goto allmulti; 652 } 653 DPRINTFN(2,("multicast address %s\n", 654 ether_sprintf(enm->enm_addrlo))); 655 /* 656 * Program the first XM_RXFILT_MAX multicast groups 657 * into the perfect filter. For all others, 658 * use the hash table. 659 */ 660 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 661 sk_setfilt(sc_if, enm->enm_addrlo, i); 662 i++; 663 } 664 else { 665 switch (sc->sk_type) { 666 case SK_GENESIS: 667 h = sk_xmac_hash(enm->enm_addrlo); 668 break; 669 case SK_YUKON: 670 case SK_YUKON_LITE: 671 case SK_YUKON_LP: 672 h = sk_yukon_hash(enm->enm_addrlo); 673 break; 674 } 675 if (h < 32) 676 hashes[0] |= (1 << h); 677 else 678 hashes[1] |= (1 << (h - 32)); 679 } 680 681 ETHER_NEXT_MULTI(step, enm); 682 } 683 ETHER_UNLOCK(ec); 684 } 685 686 switch (sc->sk_type) { 687 case SK_GENESIS: 688 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 689 XM_MODE_RX_USE_PERFECT); 690 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 691 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 692 break; 693 case SK_YUKON: 694 case SK_YUKON_LITE: 695 case SK_YUKON_LP: 696 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 697 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 698 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 699 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 700 break; 701 } 702 } 703 704 static int 705 sk_init_rx_ring(struct sk_if_softc *sc_if) 706 { 707 struct sk_chain_data *cd = &sc_if->sk_cdata; 708 struct sk_ring_data *rd = sc_if->sk_rdata; 709 int i; 710 711 memset((char *)rd->sk_rx_ring, 0, 712 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 713 714 for (i = 0; i < SK_RX_RING_CNT; i++) { 715 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 716 if (i == (SK_RX_RING_CNT - 1)) { 717 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 718 rd->sk_rx_ring[i].sk_next = 719 htole32(SK_RX_RING_ADDR(sc_if, 0)); 720 } else { 721 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 722 rd->sk_rx_ring[i].sk_next = 723 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 724 } 725 } 726 727 for (i = 0; i < SK_RX_RING_CNT; i++) { 728 if (sk_newbuf(sc_if, i, NULL, 729 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 730 aprint_error_dev(sc_if->sk_dev, 731 "failed alloc of %dth mbuf\n", i); 732 return ENOBUFS; 733 } 734 } 735 sc_if->sk_cdata.sk_rx_prod = 0; 736 sc_if->sk_cdata.sk_rx_cons = 0; 737 738 return 0; 739 } 740 741 static int 742 sk_init_tx_ring(struct sk_if_softc *sc_if) 743 { 744 struct sk_chain_data *cd = &sc_if->sk_cdata; 745 struct sk_ring_data *rd = sc_if->sk_rdata; 746 int i; 747 748 memset(sc_if->sk_rdata->sk_tx_ring, 0, 749 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 750 751 for (i = 0; i < SK_TX_RING_CNT; i++) { 752 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 753 if (i == (SK_TX_RING_CNT - 1)) { 754 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 755 rd->sk_tx_ring[i].sk_next = 756 htole32(SK_TX_RING_ADDR(sc_if, 0)); 757 } else { 758 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 759 rd->sk_tx_ring[i].sk_next = 760 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 761 } 762 } 763 764 sc_if->sk_cdata.sk_tx_prod = 0; 765 sc_if->sk_cdata.sk_tx_cons = 0; 766 sc_if->sk_cdata.sk_tx_cnt = 0; 767 768 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 771 return 0; 772 } 773 774 static int 775 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 776 bus_dmamap_t dmamap) 777 { 778 struct mbuf *m_new = NULL; 779 struct sk_chain *c; 780 struct sk_rx_desc *r; 781 782 if (m == NULL) { 783 void *buf = NULL; 784 785 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 786 if (m_new == NULL) { 787 aprint_error_dev(sc_if->sk_dev, 788 "no memory for rx list -- packet dropped!\n"); 789 return ENOBUFS; 790 } 791 792 /* Allocate the jumbo buffer */ 793 buf = sk_jalloc(sc_if); 794 if (buf == NULL) { 795 m_freem(m_new); 796 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 797 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 798 return ENOBUFS; 799 } 800 801 /* Attach the buffer to the mbuf */ 802 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 803 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 804 805 } else { 806 /* 807 * We're re-using a previously allocated mbuf; 808 * be sure to re-init pointers and lengths to 809 * default values. 810 */ 811 m_new = m; 812 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 813 m_new->m_data = m_new->m_ext.ext_buf; 814 } 815 m_adj(m_new, ETHER_ALIGN); 816 817 c = &sc_if->sk_cdata.sk_rx_chain[i]; 818 r = c->sk_desc; 819 c->sk_mbuf = m_new; 820 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 821 (((vaddr_t)m_new->m_data 822 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 823 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 824 825 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 826 827 return 0; 828 } 829 830 /* 831 * Memory management for jumbo frames. 832 */ 833 834 static int 835 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 836 { 837 struct sk_softc *sc = sc_if->sk_softc; 838 char *ptr, *kva; 839 bus_dma_segment_t seg; 840 int i, rseg, state, error; 841 struct sk_jpool_entry *entry; 842 843 state = error = 0; 844 845 /* Grab a big chunk o' storage. */ 846 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 847 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 848 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 849 return ENOBUFS; 850 } 851 852 state = 1; 853 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 854 BUS_DMA_NOWAIT)) { 855 aprint_error_dev(sc->sk_dev, 856 "can't map dma buffers (%d bytes)\n", 857 SK_JMEM); 858 error = ENOBUFS; 859 goto out; 860 } 861 862 state = 2; 863 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 864 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 865 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 866 error = ENOBUFS; 867 goto out; 868 } 869 870 state = 3; 871 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 872 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 873 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 874 error = ENOBUFS; 875 goto out; 876 } 877 878 state = 4; 879 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 880 DPRINTFN(1,("sk_jumbo_buf = %p\n", sc_if->sk_cdata.sk_jumbo_buf)); 881 882 LIST_INIT(&sc_if->sk_jfree_listhead); 883 LIST_INIT(&sc_if->sk_jinuse_listhead); 884 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 885 886 /* 887 * Now divide it up into 9K pieces and save the addresses 888 * in an array. 889 */ 890 ptr = sc_if->sk_cdata.sk_jumbo_buf; 891 for (i = 0; i < SK_JSLOTS; i++) { 892 sc_if->sk_cdata.sk_jslots[i] = ptr; 893 ptr += SK_JLEN; 894 entry = malloc(sizeof(struct sk_jpool_entry), 895 M_DEVBUF, M_WAITOK); 896 entry->slot = i; 897 if (i) 898 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 899 entry, jpool_entries); 900 else 901 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 902 entry, jpool_entries); 903 } 904 out: 905 if (error != 0) { 906 switch (state) { 907 case 4: 908 bus_dmamap_unload(sc->sc_dmatag, 909 sc_if->sk_cdata.sk_rx_jumbo_map); 910 /* FALLTHROUGH */ 911 case 3: 912 bus_dmamap_destroy(sc->sc_dmatag, 913 sc_if->sk_cdata.sk_rx_jumbo_map); 914 /* FALLTHROUGH */ 915 case 2: 916 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 917 /* FALLTHROUGH */ 918 case 1: 919 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 920 break; 921 default: 922 break; 923 } 924 } 925 926 return error; 927 } 928 929 /* 930 * Allocate a jumbo buffer. 931 */ 932 static void * 933 sk_jalloc(struct sk_if_softc *sc_if) 934 { 935 struct sk_jpool_entry *entry; 936 937 mutex_enter(&sc_if->sk_jpool_mtx); 938 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 939 940 if (entry == NULL) { 941 mutex_exit(&sc_if->sk_jpool_mtx); 942 return NULL; 943 } 944 945 LIST_REMOVE(entry, jpool_entries); 946 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 947 mutex_exit(&sc_if->sk_jpool_mtx); 948 return sc_if->sk_cdata.sk_jslots[entry->slot]; 949 } 950 951 /* 952 * Release a jumbo buffer. 953 */ 954 static void 955 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 956 { 957 struct sk_jpool_entry *entry; 958 struct sk_if_softc *sc; 959 int i; 960 961 /* Extract the softc struct pointer. */ 962 sc = (struct sk_if_softc *)arg; 963 964 if (sc == NULL) 965 panic("sk_jfree: can't find softc pointer!"); 966 967 /* calculate the slot this buffer belongs to */ 968 969 i = ((vaddr_t)buf 970 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 971 972 if ((i < 0) || (i >= SK_JSLOTS)) 973 panic("sk_jfree: asked to free buffer that we don't manage!"); 974 975 mutex_enter(&sc->sk_jpool_mtx); 976 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 977 if (entry == NULL) 978 panic("sk_jfree: buffer not in use!"); 979 entry->slot = i; 980 LIST_REMOVE(entry, jpool_entries); 981 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 982 mutex_exit(&sc->sk_jpool_mtx); 983 984 if (__predict_true(m != NULL)) 985 pool_cache_put(mb_cache, m); 986 } 987 988 /* 989 * Set media options. 990 */ 991 static int 992 sk_ifmedia_upd(struct ifnet *ifp) 993 { 994 struct sk_if_softc *sc_if = ifp->if_softc; 995 int rc; 996 997 (void) sk_init(ifp); 998 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 999 return 0; 1000 return rc; 1001 } 1002 1003 static void 1004 sk_promisc(struct sk_if_softc *sc_if, int on) 1005 { 1006 struct sk_softc *sc = sc_if->sk_softc; 1007 switch (sc->sk_type) { 1008 case SK_GENESIS: 1009 if (on) 1010 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1011 else 1012 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1013 break; 1014 case SK_YUKON: 1015 case SK_YUKON_LITE: 1016 case SK_YUKON_LP: 1017 if (on) 1018 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1019 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1020 else 1021 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1022 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1023 break; 1024 default: 1025 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1026 sc->sk_type); 1027 break; 1028 } 1029 } 1030 1031 static int 1032 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1033 { 1034 struct sk_if_softc *sc_if = ifp->if_softc; 1035 int s, error = 0; 1036 1037 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1038 1039 s = splnet(); 1040 1041 switch (command) { 1042 1043 case SIOCSIFFLAGS: 1044 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1045 if ((error = ifioctl_common(ifp, command, data)) != 0) 1046 break; 1047 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1048 case IFF_RUNNING: 1049 sk_stop(ifp, 1); 1050 break; 1051 case IFF_UP: 1052 sk_init(ifp); 1053 break; 1054 case IFF_UP | IFF_RUNNING: 1055 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1056 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1057 sk_setmulti(sc_if); 1058 } else 1059 sk_init(ifp); 1060 break; 1061 } 1062 sc_if->sk_if_flags = ifp->if_flags; 1063 error = 0; 1064 break; 1065 1066 default: 1067 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1068 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1069 break; 1070 1071 error = 0; 1072 1073 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1074 ; 1075 else if (ifp->if_flags & IFF_RUNNING) { 1076 sk_setmulti(sc_if); 1077 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1078 } 1079 break; 1080 } 1081 1082 splx(s); 1083 return error; 1084 } 1085 1086 static void 1087 sk_update_int_mod(struct sk_softc *sc) 1088 { 1089 uint32_t imtimer_ticks; 1090 1091 /* 1092 * Configure interrupt moderation. The moderation timer 1093 * defers interrupts specified in the interrupt moderation 1094 * timer mask based on the timeout specified in the interrupt 1095 * moderation timer init register. Each bit in the timer 1096 * register represents one tick, so to specify a timeout in 1097 * microseconds, we have to multiply by the correct number of 1098 * ticks-per-microsecond. 1099 */ 1100 switch (sc->sk_type) { 1101 case SK_GENESIS: 1102 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1103 break; 1104 case SK_YUKON_EC: 1105 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1106 break; 1107 default: 1108 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1109 } 1110 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1111 sc->sk_int_mod); 1112 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1113 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1114 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1115 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1116 sc->sk_int_mod_pending = 0; 1117 } 1118 1119 /* 1120 * Lookup: Check the PCI vendor and device, and return a pointer to 1121 * The structure if the IDs match against our list. 1122 */ 1123 1124 /* 1125 * Probe for a SysKonnect GEnesis chip. 1126 */ 1127 1128 static int 1129 skc_probe(device_t parent, cfdata_t match, void *aux) 1130 { 1131 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1132 pcireg_t subid; 1133 1134 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1135 1136 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1137 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1139 subid == SK_LINKSYS_EG1032_SUBID) 1140 return 1; 1141 1142 return pci_compatible_match(pa, compat_data); 1143 } 1144 1145 /* 1146 * Force the GEnesis into reset, then bring it out of reset. 1147 */ 1148 static void 1149 sk_reset(struct sk_softc *sc) 1150 { 1151 DPRINTFN(2, ("sk_reset\n")); 1152 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1154 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1155 if (SK_YUKON_FAMILY(sc->sk_type)) 1156 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1157 1158 DELAY(1000); 1159 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1160 DELAY(2); 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1162 if (SK_YUKON_FAMILY(sc->sk_type)) 1163 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1164 1165 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1166 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1167 CSR_READ_2(sc, SK_LINK_CTRL))); 1168 1169 if (sc->sk_type == SK_GENESIS) { 1170 /* Configure packet arbiter */ 1171 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1172 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1173 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1175 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1176 } 1177 1178 /* Enable RAM interface */ 1179 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1180 1181 sk_update_int_mod(sc); 1182 } 1183 1184 static int 1185 sk_probe(device_t parent, cfdata_t match, void *aux) 1186 { 1187 struct skc_attach_args *sa = aux; 1188 1189 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1190 return 0; 1191 1192 return 1; 1193 } 1194 1195 /* 1196 * Each XMAC chip is attached as a separate logical IP interface. 1197 * Single port cards will have only one logical interface of course. 1198 */ 1199 static void 1200 sk_attach(device_t parent, device_t self, void *aux) 1201 { 1202 struct sk_if_softc *sc_if = device_private(self); 1203 struct mii_data *mii = &sc_if->sk_mii; 1204 struct sk_softc *sc = device_private(parent); 1205 struct skc_attach_args *sa = aux; 1206 struct sk_txmap_entry *entry; 1207 struct ifnet *ifp; 1208 bus_dma_segment_t seg; 1209 bus_dmamap_t dmamap; 1210 void *kva; 1211 int i, rseg; 1212 int mii_flags = 0; 1213 1214 aprint_naive("\n"); 1215 1216 sc_if->sk_dev = self; 1217 sc_if->sk_port = sa->skc_port; 1218 sc_if->sk_softc = sc; 1219 sc->sk_if[sa->skc_port] = sc_if; 1220 1221 if (sa->skc_port == SK_PORT_A) 1222 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1223 if (sa->skc_port == SK_PORT_B) 1224 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1225 1226 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1227 1228 /* 1229 * Get station address for this interface. Note that 1230 * dual port cards actually come with three station 1231 * addresses: one for each port, plus an extra. The 1232 * extra one is used by the SysKonnect driver software 1233 * as a 'virtual' station address for when both ports 1234 * are operating in failover mode. Currently we don't 1235 * use this extra address. 1236 */ 1237 if (! ether_getaddr(self, sc_if->sk_enaddr)) { 1238 for (i = 0; i < ETHER_ADDR_LEN; i++) 1239 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1240 SK_MAC0_0 + (sa->skc_port * 8) + i); 1241 } 1242 1243 aprint_normal(": Ethernet address %s\n", 1244 ether_sprintf(sc_if->sk_enaddr)); 1245 1246 /* 1247 * Set up RAM buffer addresses. The NIC will have a certain 1248 * amount of SRAM on it, somewhere between 512K and 2MB. We 1249 * need to divide this up a) between the transmitter and 1250 * receiver and b) between the two XMACs, if this is a 1251 * dual port NIC. Our algorithm is to divide up the memory 1252 * evenly so that everyone gets a fair share. 1253 */ 1254 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1255 uint32_t chunk, val; 1256 1257 chunk = sc->sk_ramsize / 2; 1258 val = sc->sk_rboff / sizeof(uint64_t); 1259 sc_if->sk_rx_ramstart = val; 1260 val += (chunk / sizeof(uint64_t)); 1261 sc_if->sk_rx_ramend = val - 1; 1262 sc_if->sk_tx_ramstart = val; 1263 val += (chunk / sizeof(uint64_t)); 1264 sc_if->sk_tx_ramend = val - 1; 1265 } else { 1266 uint32_t chunk, val; 1267 1268 chunk = sc->sk_ramsize / 4; 1269 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1270 sizeof(uint64_t); 1271 sc_if->sk_rx_ramstart = val; 1272 val += (chunk / sizeof(uint64_t)); 1273 sc_if->sk_rx_ramend = val - 1; 1274 sc_if->sk_tx_ramstart = val; 1275 val += (chunk / sizeof(uint64_t)); 1276 sc_if->sk_tx_ramend = val - 1; 1277 } 1278 1279 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1280 " tx_ramstart=%#x tx_ramend=%#x\n", 1281 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1282 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1283 1284 /* Read and save PHY type and set PHY address */ 1285 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1286 switch (sc_if->sk_phytype) { 1287 case SK_PHYTYPE_XMAC: 1288 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1289 break; 1290 case SK_PHYTYPE_BCOM: 1291 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1292 break; 1293 case SK_PHYTYPE_MARV_COPPER: 1294 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1295 break; 1296 default: 1297 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1298 sc_if->sk_phytype); 1299 return; 1300 } 1301 1302 /* Allocate the descriptor queues. */ 1303 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1304 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1305 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1306 goto fail; 1307 } 1308 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1309 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1310 aprint_error_dev(sc_if->sk_dev, 1311 "can't map dma buffers (%lu bytes)\n", 1312 (u_long) sizeof(struct sk_ring_data)); 1313 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1314 goto fail; 1315 } 1316 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1317 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1318 &sc_if->sk_ring_map)) { 1319 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1320 bus_dmamem_unmap(sc->sc_dmatag, kva, 1321 sizeof(struct sk_ring_data)); 1322 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1323 goto fail; 1324 } 1325 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1326 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1327 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1328 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1329 bus_dmamem_unmap(sc->sc_dmatag, kva, 1330 sizeof(struct sk_ring_data)); 1331 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1332 goto fail; 1333 } 1334 1335 for (i = 0; i < SK_RX_RING_CNT; i++) 1336 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1337 1338 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1339 for (i = 0; i < SK_TX_RING_CNT; i++) { 1340 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1341 1342 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1343 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1344 aprint_error_dev(sc_if->sk_dev, 1345 "Can't create TX dmamap\n"); 1346 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1347 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1348 bus_dmamem_unmap(sc->sc_dmatag, kva, 1349 sizeof(struct sk_ring_data)); 1350 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1351 goto fail; 1352 } 1353 1354 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK); 1355 entry->dmamap = dmamap; 1356 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1357 } 1358 1359 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1360 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1361 1362 ifp = &sc_if->sk_ethercom.ec_if; 1363 /* Try to allocate memory for jumbo buffers. */ 1364 if (sk_alloc_jumbo_mem(sc_if)) { 1365 aprint_error("%s: jumbo buffer allocation failed\n", 1366 ifp->if_xname); 1367 goto fail; 1368 } 1369 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1370 | ETHERCAP_JUMBO_MTU; 1371 1372 ifp->if_softc = sc_if; 1373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1374 ifp->if_ioctl = sk_ioctl; 1375 ifp->if_start = sk_start; 1376 ifp->if_stop = sk_stop; 1377 ifp->if_init = sk_init; 1378 ifp->if_watchdog = sk_watchdog; 1379 ifp->if_capabilities = 0; 1380 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1381 IFQ_SET_READY(&ifp->if_snd); 1382 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1383 1384 /* 1385 * Do miibus setup. 1386 */ 1387 switch (sc->sk_type) { 1388 case SK_GENESIS: 1389 sk_unreset_xmac(sc_if); 1390 break; 1391 case SK_YUKON: 1392 case SK_YUKON_LITE: 1393 case SK_YUKON_LP: 1394 sk_unreset_yukon(sc_if); 1395 break; 1396 default: 1397 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1398 sc->sk_type); 1399 goto fail; 1400 } 1401 1402 DPRINTFN(2, ("sk_attach: 1\n")); 1403 1404 mii->mii_ifp = ifp; 1405 switch (sc->sk_type) { 1406 case SK_GENESIS: 1407 mii->mii_readreg = sk_xmac_miibus_readreg; 1408 mii->mii_writereg = sk_xmac_miibus_writereg; 1409 mii->mii_statchg = sk_xmac_miibus_statchg; 1410 break; 1411 case SK_YUKON: 1412 case SK_YUKON_LITE: 1413 case SK_YUKON_LP: 1414 mii->mii_readreg = sk_marv_miibus_readreg; 1415 mii->mii_writereg = sk_marv_miibus_writereg; 1416 mii->mii_statchg = sk_marv_miibus_statchg; 1417 mii_flags = MIIF_DOPAUSE; 1418 break; 1419 } 1420 1421 sc_if->sk_ethercom.ec_mii = mii; 1422 ifmedia_init(&mii->mii_media, 0, sk_ifmedia_upd, ether_mediastatus); 1423 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1424 MII_OFFSET_ANY, mii_flags); 1425 if (LIST_EMPTY(&mii->mii_phys)) { 1426 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1427 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 1428 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1429 } else 1430 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1431 1432 callout_init(&sc_if->sk_tick_ch, 0); 1433 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1434 1435 DPRINTFN(2, ("sk_attach: 1\n")); 1436 1437 /* 1438 * Call MI attach routines. 1439 */ 1440 if_attach(ifp); 1441 if_deferred_start_init(ifp, NULL); 1442 1443 ether_ifattach(ifp, sc_if->sk_enaddr); 1444 1445 if (sc->rnd_attached++ == 0) { 1446 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1447 RND_TYPE_NET, RND_FLAG_DEFAULT); 1448 } 1449 1450 if (pmf_device_register(self, NULL, sk_resume)) 1451 pmf_class_network_register(self, ifp); 1452 else 1453 aprint_error_dev(self, "couldn't establish power handler\n"); 1454 1455 DPRINTFN(2, ("sk_attach: end\n")); 1456 1457 return; 1458 1459 fail: 1460 sc->sk_if[sa->skc_port] = NULL; 1461 } 1462 1463 static int 1464 skcprint(void *aux, const char *pnp) 1465 { 1466 struct skc_attach_args *sa = aux; 1467 1468 if (pnp) 1469 aprint_normal("sk port %c at %s", 1470 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1471 else 1472 aprint_normal(" port %c", 1473 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1474 return UNCONF; 1475 } 1476 1477 /* 1478 * Attach the interface. Allocate softc structures, do ifmedia 1479 * setup and ethernet/BPF attach. 1480 */ 1481 static void 1482 skc_attach(device_t parent, device_t self, void *aux) 1483 { 1484 struct sk_softc *sc = device_private(self); 1485 struct pci_attach_args *pa = aux; 1486 struct skc_attach_args skca; 1487 pci_chipset_tag_t pc = pa->pa_pc; 1488 #ifndef SK_USEIOSPACE 1489 pcireg_t memtype; 1490 #endif 1491 pci_intr_handle_t ih; 1492 const char *intrstr = NULL; 1493 bus_addr_t iobase; 1494 bus_size_t iosize; 1495 int rc, sk_nodenum; 1496 uint32_t command; 1497 const char *revstr; 1498 const struct sysctlnode *node; 1499 char intrbuf[PCI_INTRSTR_LEN]; 1500 1501 sc->sk_dev = self; 1502 aprint_naive("\n"); 1503 1504 DPRINTFN(2, ("begin skc_attach\n")); 1505 1506 /* 1507 * Handle power management nonsense. 1508 */ 1509 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1510 1511 if (command == 0x01) { 1512 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1513 if (command & SK_PSTATE_MASK) { 1514 uint32_t xiobase, membase, irq; 1515 1516 /* Save important PCI config data. */ 1517 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1518 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1519 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1520 1521 /* Reset the power state. */ 1522 aprint_normal_dev(sc->sk_dev, 1523 "chip is in D%d power mode -- setting to D0\n", 1524 command & SK_PSTATE_MASK); 1525 command &= 0xFFFFFFFC; 1526 pci_conf_write(pc, pa->pa_tag, 1527 SK_PCI_PWRMGMTCTRL, command); 1528 1529 /* Restore PCI config data. */ 1530 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1531 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1532 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1533 } 1534 } 1535 1536 /* 1537 * The firmware might have configured the interface to revert the 1538 * byte order in all descriptors. Make that undone. 1539 */ 1540 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1541 if (command & SK_REG2_REV_DESC) 1542 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1543 command & ~SK_REG2_REV_DESC); 1544 1545 /* 1546 * Map control/status registers. 1547 */ 1548 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1549 command |= PCI_COMMAND_IO_ENABLE | 1550 PCI_COMMAND_MEM_ENABLE | 1551 PCI_COMMAND_MASTER_ENABLE; 1552 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1553 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1554 1555 #ifdef SK_USEIOSPACE 1556 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1557 aprint_error(": failed to enable I/O ports!\n"); 1558 return; 1559 } 1560 /* 1561 * Map control/status registers. 1562 */ 1563 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1564 &sc->sk_btag, &sc->sk_bhandle, 1565 &iobase, &iosize)) { 1566 aprint_error(": can't find i/o space\n"); 1567 return; 1568 } 1569 #else 1570 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1571 aprint_error(": failed to enable memory mapping!\n"); 1572 return; 1573 } 1574 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1575 switch (memtype) { 1576 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1577 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1578 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1579 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1580 &iobase, &iosize) == 0) 1581 break; 1582 /* FALLTHROUGH */ 1583 default: 1584 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1585 return; 1586 } 1587 1588 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1589 iobase, iosize)); 1590 #endif 1591 sc->sc_dmatag = pa->pa_dmat; 1592 1593 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1594 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1595 1596 /* bail out here if chip is not recognized */ 1597 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1598 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1599 goto fail; 1600 } 1601 if (SK_IS_YUKON2(sc)) { 1602 aprint_error_dev(sc->sk_dev, 1603 "Does not support Yukon2--try msk(4).\n"); 1604 goto fail; 1605 } 1606 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1607 1608 /* Allocate interrupt */ 1609 if (pci_intr_map(pa, &ih)) { 1610 aprint_error(": couldn't map interrupt\n"); 1611 goto fail; 1612 } 1613 1614 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1615 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, 1616 sc, device_xname(sc->sk_dev)); 1617 if (sc->sk_intrhand == NULL) { 1618 aprint_error(": couldn't establish interrupt"); 1619 if (intrstr != NULL) 1620 aprint_error(" at %s", intrstr); 1621 aprint_error("\n"); 1622 goto fail; 1623 } 1624 aprint_normal(": %s\n", intrstr); 1625 1626 /* Reset the adapter. */ 1627 sk_reset(sc); 1628 1629 /* Read and save vital product data from EEPROM. */ 1630 sk_vpd_read(sc); 1631 1632 if (sc->sk_type == SK_GENESIS) { 1633 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1634 /* Read and save RAM size and RAMbuffer offset */ 1635 switch (val) { 1636 case SK_RAMSIZE_512K_64: 1637 sc->sk_ramsize = 0x80000; 1638 sc->sk_rboff = SK_RBOFF_0; 1639 break; 1640 case SK_RAMSIZE_1024K_64: 1641 sc->sk_ramsize = 0x100000; 1642 sc->sk_rboff = SK_RBOFF_80000; 1643 break; 1644 case SK_RAMSIZE_1024K_128: 1645 sc->sk_ramsize = 0x100000; 1646 sc->sk_rboff = SK_RBOFF_0; 1647 break; 1648 case SK_RAMSIZE_2048K_128: 1649 sc->sk_ramsize = 0x200000; 1650 sc->sk_rboff = SK_RBOFF_0; 1651 break; 1652 default: 1653 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1654 val); 1655 goto fail_1; 1656 break; 1657 } 1658 1659 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1660 sc->sk_ramsize, sc->sk_ramsize / 1024, 1661 sc->sk_rboff)); 1662 } else { 1663 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1664 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1665 sc->sk_rboff = SK_RBOFF_0; 1666 1667 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1668 sc->sk_ramsize / 1024, sc->sk_ramsize, 1669 sc->sk_rboff)); 1670 } 1671 1672 /* Read and save physical media type */ 1673 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1674 case SK_PMD_1000BASESX: 1675 sc->sk_pmd = IFM_1000_SX; 1676 break; 1677 case SK_PMD_1000BASELX: 1678 sc->sk_pmd = IFM_1000_LX; 1679 break; 1680 case SK_PMD_1000BASECX: 1681 sc->sk_pmd = IFM_1000_CX; 1682 break; 1683 case SK_PMD_1000BASETX: 1684 case SK_PMD_1000BASETX_ALT: 1685 sc->sk_pmd = IFM_1000_T; 1686 break; 1687 default: 1688 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1689 sk_win_read_1(sc, SK_PMDTYPE)); 1690 goto fail_1; 1691 } 1692 1693 /* determine whether to name it with vpd or just make it up */ 1694 /* Marvell Yukon VPD's can freqently be bogus */ 1695 1696 switch (pa->pa_id) { 1697 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1698 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1699 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1700 case PCI_PRODUCT_3COM_3C940: 1701 case PCI_PRODUCT_DLINK_DGE530T: 1702 case PCI_PRODUCT_DLINK_DGE560T: 1703 case PCI_PRODUCT_DLINK_DGE560T_2: 1704 case PCI_PRODUCT_LINKSYS_EG1032: 1705 case PCI_PRODUCT_LINKSYS_EG1064: 1706 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1707 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1708 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1709 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1710 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1711 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1712 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1713 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1714 sc->sk_name = sc->sk_vpd_prodname; 1715 break; 1716 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1717 /* whoops yukon vpd prodname bears no resemblance to reality */ 1718 switch (sc->sk_type) { 1719 case SK_GENESIS: 1720 sc->sk_name = sc->sk_vpd_prodname; 1721 break; 1722 case SK_YUKON: 1723 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1724 break; 1725 case SK_YUKON_LITE: 1726 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1727 break; 1728 case SK_YUKON_LP: 1729 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1730 break; 1731 default: 1732 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1733 } 1734 1735 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1736 1737 if ( sc->sk_type == SK_YUKON ) { 1738 uint32_t flashaddr; 1739 uint8_t testbyte; 1740 1741 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1742 1743 /* test Flash-Address Register */ 1744 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1745 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1746 1747 if (testbyte != 0) { 1748 /* this is yukon lite Rev. A0 */ 1749 sc->sk_type = SK_YUKON_LITE; 1750 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1751 /* restore Flash-Address Register */ 1752 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1753 } 1754 } 1755 break; 1756 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1757 sc->sk_name = sc->sk_vpd_prodname; 1758 break; 1759 default: 1760 sc->sk_name = "Unknown Marvell"; 1761 } 1762 1763 1764 if ( sc->sk_type == SK_YUKON_LITE ) { 1765 switch (sc->sk_rev) { 1766 case SK_YUKON_LITE_REV_A0: 1767 revstr = "A0"; 1768 break; 1769 case SK_YUKON_LITE_REV_A1: 1770 revstr = "A1"; 1771 break; 1772 case SK_YUKON_LITE_REV_A3: 1773 revstr = "A3"; 1774 break; 1775 default: 1776 revstr = ""; 1777 } 1778 } else { 1779 revstr = ""; 1780 } 1781 1782 /* Announce the product name. */ 1783 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1784 sc->sk_name, revstr, sc->sk_rev); 1785 1786 skca.skc_port = SK_PORT_A; 1787 (void)config_found(sc->sk_dev, &skca, skcprint, CFARGS_NONE); 1788 1789 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1790 skca.skc_port = SK_PORT_B; 1791 (void)config_found(sc->sk_dev, &skca, skcprint, CFARGS_NONE); 1792 } 1793 1794 /* Turn on the 'driver is loaded' LED. */ 1795 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1796 1797 /* skc sysctl setup */ 1798 1799 sc->sk_int_mod = SK_IM_DEFAULT; 1800 sc->sk_int_mod_pending = 0; 1801 1802 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1803 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1804 SYSCTL_DESCR("skc per-controller controls"), 1805 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1806 CTL_EOL)) != 0) { 1807 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1808 goto fail_1; 1809 } 1810 1811 sk_nodenum = node->sysctl_num; 1812 1813 /* interrupt moderation time in usecs */ 1814 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1815 CTLFLAG_READWRITE, 1816 CTLTYPE_INT, "int_mod", 1817 SYSCTL_DESCR("sk interrupt moderation timer"), 1818 sk_sysctl_handler, 0, (void *)sc, 1819 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1820 CTL_EOL)) != 0) { 1821 aprint_normal_dev(sc->sk_dev, 1822 "couldn't create int_mod sysctl node\n"); 1823 goto fail_1; 1824 } 1825 1826 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1827 aprint_error_dev(self, "couldn't establish power handler\n"); 1828 1829 return; 1830 1831 fail_1: 1832 pci_intr_disestablish(pc, sc->sk_intrhand); 1833 fail: 1834 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1835 } 1836 1837 static int 1838 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1839 { 1840 struct sk_softc *sc = sc_if->sk_softc; 1841 struct sk_tx_desc *f = NULL; 1842 uint32_t frag, cur, cnt = 0, sk_ctl; 1843 int i; 1844 struct sk_txmap_entry *entry; 1845 bus_dmamap_t txmap; 1846 1847 DPRINTFN(3, ("sk_encap\n")); 1848 1849 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1850 if (entry == NULL) { 1851 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1852 return ENOBUFS; 1853 } 1854 txmap = entry->dmamap; 1855 1856 cur = frag = *txidx; 1857 1858 #ifdef SK_DEBUG 1859 if (skdebug >= 3) 1860 sk_dump_mbuf(m_head); 1861 #endif 1862 1863 /* 1864 * Start packing the mbufs in this chain into 1865 * the fragment pointers. Stop when we run out 1866 * of fragments or hit the end of the mbuf chain. 1867 */ 1868 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1869 BUS_DMA_NOWAIT)) { 1870 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1871 return ENOBUFS; 1872 } 1873 1874 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1875 1876 /* Sync the DMA map. */ 1877 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1878 BUS_DMASYNC_PREWRITE); 1879 1880 for (i = 0; i < txmap->dm_nsegs; i++) { 1881 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1882 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1883 return ENOBUFS; 1884 } 1885 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1886 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1887 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1888 if (cnt == 0) 1889 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1890 else 1891 sk_ctl |= SK_TXCTL_OWN; 1892 f->sk_ctl = htole32(sk_ctl); 1893 cur = frag; 1894 SK_INC(frag, SK_TX_RING_CNT); 1895 cnt++; 1896 } 1897 1898 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1899 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1900 1901 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1902 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1903 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1904 1905 /* Sync descriptors before handing to chip */ 1906 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1907 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1908 1909 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1910 htole32(SK_TXCTL_OWN); 1911 1912 /* Sync first descriptor to hand it off */ 1913 SK_CDTXSYNC(sc_if, *txidx, 1, 1914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1915 1916 sc_if->sk_cdata.sk_tx_cnt += cnt; 1917 1918 #ifdef SK_DEBUG 1919 if (skdebug >= 3) { 1920 struct sk_tx_desc *desc; 1921 uint32_t idx; 1922 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1923 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1924 sk_dump_txdesc(desc, idx); 1925 } 1926 } 1927 #endif 1928 1929 *txidx = frag; 1930 1931 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1932 1933 return 0; 1934 } 1935 1936 static void 1937 sk_start(struct ifnet *ifp) 1938 { 1939 struct sk_if_softc *sc_if = ifp->if_softc; 1940 struct sk_softc *sc = sc_if->sk_softc; 1941 struct mbuf *m_head = NULL; 1942 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1943 int pkts = 0; 1944 1945 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1946 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1947 1948 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1949 IFQ_POLL(&ifp->if_snd, m_head); 1950 if (m_head == NULL) 1951 break; 1952 1953 /* 1954 * Pack the data into the transmit ring. If we 1955 * don't have room, set the OACTIVE flag and wait 1956 * for the NIC to drain the ring. 1957 */ 1958 if (sk_encap(sc_if, m_head, &idx)) { 1959 ifp->if_flags |= IFF_OACTIVE; 1960 break; 1961 } 1962 1963 /* now we are committed to transmit the packet */ 1964 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1965 pkts++; 1966 1967 /* 1968 * If there's a BPF listener, bounce a copy of this frame 1969 * to him. 1970 */ 1971 bpf_mtap(ifp, m_head, BPF_D_OUT); 1972 } 1973 if (pkts == 0) 1974 return; 1975 1976 /* Transmit */ 1977 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1978 sc_if->sk_cdata.sk_tx_prod = idx; 1979 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1980 1981 /* Set a timeout in case the chip goes out to lunch. */ 1982 ifp->if_timer = 5; 1983 } 1984 } 1985 1986 1987 static void 1988 sk_watchdog(struct ifnet *ifp) 1989 { 1990 struct sk_if_softc *sc_if = ifp->if_softc; 1991 1992 /* 1993 * Reclaim first as there is a possibility of losing Tx completion 1994 * interrupts. 1995 */ 1996 sk_txeof(sc_if); 1997 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1998 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1999 2000 if_statinc(ifp, if_oerrors); 2001 2002 sk_init(ifp); 2003 } 2004 } 2005 2006 #if 0 /* XXX XXX XXX UNUSED */ 2007 static void 2008 sk_shutdown(void *v) 2009 { 2010 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2011 struct sk_softc *sc = sc_if->sk_softc; 2012 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2013 2014 DPRINTFN(2, ("sk_shutdown\n")); 2015 sk_stop(ifp, 1); 2016 2017 /* Turn off the 'driver is loaded' LED. */ 2018 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2019 2020 /* 2021 * Reset the GEnesis controller. Doing this should also 2022 * assert the resets on the attached XMAC(s). 2023 */ 2024 sk_reset(sc); 2025 } 2026 #endif 2027 2028 static void 2029 sk_rxeof(struct sk_if_softc *sc_if) 2030 { 2031 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2032 struct mbuf *m; 2033 struct sk_chain *cur_rx; 2034 struct sk_rx_desc *cur_desc; 2035 int i, cur, total_len = 0; 2036 uint32_t rxstat, sk_ctl; 2037 bus_dmamap_t dmamap; 2038 2039 i = sc_if->sk_cdata.sk_rx_prod; 2040 2041 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2042 2043 for (;;) { 2044 cur = i; 2045 2046 /* Sync the descriptor */ 2047 SK_CDRXSYNC(sc_if, cur, 2048 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2049 2050 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2051 if (sk_ctl & SK_RXCTL_OWN) { 2052 /* Invalidate the descriptor -- it's not ready yet */ 2053 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2054 sc_if->sk_cdata.sk_rx_prod = i; 2055 break; 2056 } 2057 2058 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2059 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2060 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2061 2062 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2063 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2064 2065 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2066 m = cur_rx->sk_mbuf; 2067 cur_rx->sk_mbuf = NULL; 2068 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2069 2070 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2071 2072 SK_INC(i, SK_RX_RING_CNT); 2073 2074 if (rxstat & XM_RXSTAT_ERRFRAME) { 2075 if_statinc(ifp, if_ierrors); 2076 sk_newbuf(sc_if, cur, m, dmamap); 2077 continue; 2078 } 2079 2080 /* 2081 * Try to allocate a new jumbo buffer. If that 2082 * fails, copy the packet to mbufs and put the 2083 * jumbo buffer back in the ring so it can be 2084 * re-used. If allocating mbufs fails, then we 2085 * have to drop the packet. 2086 */ 2087 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2088 struct mbuf *m0; 2089 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2090 total_len + ETHER_ALIGN, 0, ifp); 2091 sk_newbuf(sc_if, cur, m, dmamap); 2092 if (m0 == NULL) { 2093 aprint_error_dev(sc_if->sk_dev, "no receive " 2094 "buffers available -- packet dropped!\n"); 2095 if_statinc(ifp, if_ierrors); 2096 continue; 2097 } 2098 m_adj(m0, ETHER_ALIGN); 2099 m = m0; 2100 } else { 2101 m_set_rcvif(m, ifp); 2102 m->m_pkthdr.len = m->m_len = total_len; 2103 } 2104 2105 /* pass it on. */ 2106 if_percpuq_enqueue(ifp->if_percpuq, m); 2107 } 2108 } 2109 2110 static void 2111 sk_txeof(struct sk_if_softc *sc_if) 2112 { 2113 struct sk_softc *sc = sc_if->sk_softc; 2114 struct sk_tx_desc *cur_tx; 2115 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2116 uint32_t idx, sk_ctl; 2117 struct sk_txmap_entry *entry; 2118 2119 DPRINTFN(3, ("sk_txeof\n")); 2120 2121 /* 2122 * Go through our tx ring and free mbufs for those 2123 * frames that have been sent. 2124 */ 2125 idx = sc_if->sk_cdata.sk_tx_cons; 2126 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2127 SK_CDTXSYNC(sc_if, idx, 1, 2128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2129 2130 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2131 sk_ctl = le32toh(cur_tx->sk_ctl); 2132 #ifdef SK_DEBUG 2133 if (skdebug >= 3) 2134 sk_dump_txdesc(cur_tx, idx); 2135 #endif 2136 if (sk_ctl & SK_TXCTL_OWN) { 2137 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2138 break; 2139 } 2140 if (sk_ctl & SK_TXCTL_LASTFRAG) 2141 if_statinc(ifp, if_opackets); 2142 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2143 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2144 2145 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2146 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2147 2148 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2149 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2150 link); 2151 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2152 2153 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2154 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2155 } 2156 sc_if->sk_cdata.sk_tx_cnt--; 2157 SK_INC(idx, SK_TX_RING_CNT); 2158 } 2159 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2160 ifp->if_timer = 0; 2161 else /* nudge chip to keep tx ring moving */ 2162 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2163 2164 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2165 ifp->if_flags &= ~IFF_OACTIVE; 2166 2167 sc_if->sk_cdata.sk_tx_cons = idx; 2168 } 2169 2170 static void 2171 sk_tick(void *xsc_if) 2172 { 2173 struct sk_if_softc *sc_if = xsc_if; 2174 struct mii_data *mii = &sc_if->sk_mii; 2175 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2176 int i; 2177 2178 DPRINTFN(3, ("sk_tick\n")); 2179 2180 if (!(ifp->if_flags & IFF_UP)) 2181 return; 2182 2183 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2184 sk_intr_bcom(sc_if); 2185 return; 2186 } 2187 2188 /* 2189 * According to SysKonnect, the correct way to verify that 2190 * the link has come back up is to poll bit 0 of the GPIO 2191 * register three times. This pin has the signal from the 2192 * link sync pin connected to it; if we read the same link 2193 * state 3 times in a row, we know the link is up. 2194 */ 2195 for (i = 0; i < 3; i++) { 2196 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2197 break; 2198 } 2199 2200 if (i != 3) { 2201 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2202 return; 2203 } 2204 2205 /* Turn the GP0 interrupt back on. */ 2206 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2207 SK_XM_READ_2(sc_if, XM_ISR); 2208 mii_tick(mii); 2209 if (ifp->if_link_state != LINK_STATE_UP) 2210 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2211 else 2212 callout_stop(&sc_if->sk_tick_ch); 2213 } 2214 2215 static void 2216 sk_intr_bcom(struct sk_if_softc *sc_if) 2217 { 2218 struct mii_data *mii = &sc_if->sk_mii; 2219 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2220 uint16_t status; 2221 2222 2223 DPRINTFN(3, ("sk_intr_bcom\n")); 2224 2225 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2226 2227 /* 2228 * Read the PHY interrupt register to make sure 2229 * we clear any pending interrupts. 2230 */ 2231 sk_xmac_miibus_readreg(sc_if->sk_dev, 2232 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2233 2234 if (!(ifp->if_flags & IFF_RUNNING)) { 2235 sk_init_xmac(sc_if); 2236 return; 2237 } 2238 2239 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2240 uint16_t lstat; 2241 sk_xmac_miibus_readreg(sc_if->sk_dev, 2242 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2243 2244 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2245 (void)mii_mediachg(mii); 2246 /* Turn off the link LED. */ 2247 SK_IF_WRITE_1(sc_if, 0, 2248 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2249 sc_if->sk_link = 0; 2250 } else if (status & BRGPHY_ISR_LNK_CHG) { 2251 sk_xmac_miibus_writereg(sc_if->sk_dev, 2252 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2253 mii_tick(mii); 2254 sc_if->sk_link = 1; 2255 /* Turn on the link LED. */ 2256 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2257 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2258 SK_LINKLED_BLINK_OFF); 2259 mii_pollstat(mii); 2260 } else { 2261 mii_tick(mii); 2262 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2263 } 2264 } 2265 2266 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2267 } 2268 2269 static void 2270 sk_intr_xmac(struct sk_if_softc *sc_if) 2271 { 2272 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2273 2274 DPRINTFN(3, ("sk_intr_xmac\n")); 2275 2276 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2277 if (status & XM_ISR_GP0_SET) { 2278 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2279 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2280 } 2281 2282 if (status & XM_ISR_AUTONEG_DONE) { 2283 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2284 } 2285 } 2286 2287 if (status & XM_IMR_TX_UNDERRUN) 2288 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2289 2290 if (status & XM_IMR_RX_OVERRUN) 2291 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2292 } 2293 2294 static void 2295 sk_intr_yukon(struct sk_if_softc *sc_if) 2296 { 2297 #ifdef SK_DEBUG 2298 int status; 2299 2300 status = 2301 #endif 2302 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2303 2304 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2305 } 2306 2307 static int 2308 sk_intr(void *xsc) 2309 { 2310 struct sk_softc *sc = xsc; 2311 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2312 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2313 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2314 uint32_t status; 2315 int claimed = 0; 2316 2317 if (sc_if0 != NULL) 2318 ifp0 = &sc_if0->sk_ethercom.ec_if; 2319 if (sc_if1 != NULL) 2320 ifp1 = &sc_if1->sk_ethercom.ec_if; 2321 2322 for (;;) { 2323 status = CSR_READ_4(sc, SK_ISSR); 2324 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2325 2326 if (!(status & sc->sk_intrmask)) 2327 break; 2328 2329 claimed = 1; 2330 2331 /* Handle receive interrupts first. */ 2332 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2333 sk_rxeof(sc_if0); 2334 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2335 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2336 } 2337 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2338 sk_rxeof(sc_if1); 2339 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2340 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2341 } 2342 2343 /* Then transmit interrupts. */ 2344 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2345 sk_txeof(sc_if0); 2346 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2347 SK_TXBMU_CLR_IRQ_EOF); 2348 } 2349 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2350 sk_txeof(sc_if1); 2351 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2352 SK_TXBMU_CLR_IRQ_EOF); 2353 } 2354 2355 /* Then MAC interrupts. */ 2356 if (sc_if0 && (status & SK_ISR_MAC1) && 2357 (ifp0->if_flags & IFF_RUNNING)) { 2358 if (sc->sk_type == SK_GENESIS) 2359 sk_intr_xmac(sc_if0); 2360 else 2361 sk_intr_yukon(sc_if0); 2362 } 2363 2364 if (sc_if1 && (status & SK_ISR_MAC2) && 2365 (ifp1->if_flags & IFF_RUNNING)) { 2366 if (sc->sk_type == SK_GENESIS) 2367 sk_intr_xmac(sc_if1); 2368 else 2369 sk_intr_yukon(sc_if1); 2370 2371 } 2372 2373 if (status & SK_ISR_EXTERNAL_REG) { 2374 if (sc_if0 != NULL && 2375 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2376 sk_intr_bcom(sc_if0); 2377 2378 if (sc_if1 != NULL && 2379 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2380 sk_intr_bcom(sc_if1); 2381 } 2382 } 2383 2384 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2385 2386 if (ifp0 != NULL) 2387 if_schedule_deferred_start(ifp0); 2388 if (ifp1 != NULL) 2389 if_schedule_deferred_start(ifp1); 2390 2391 KASSERT(sc->rnd_attached > 0); 2392 rnd_add_uint32(&sc->rnd_source, status); 2393 2394 if (sc->sk_int_mod_pending) 2395 sk_update_int_mod(sc); 2396 2397 return claimed; 2398 } 2399 2400 static void 2401 sk_unreset_xmac(struct sk_if_softc *sc_if) 2402 { 2403 struct sk_softc *sc = sc_if->sk_softc; 2404 static const struct sk_bcom_hack bhack[] = { 2405 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2406 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2407 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2408 { 0, 0 } }; 2409 2410 DPRINTFN(1, ("sk_unreset_xmac\n")); 2411 2412 /* Unreset the XMAC. */ 2413 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2414 DELAY(1000); 2415 2416 /* Reset the XMAC's internal state. */ 2417 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2418 2419 /* Save the XMAC II revision */ 2420 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2421 2422 /* 2423 * Perform additional initialization for external PHYs, 2424 * namely for the 1000baseTX cards that use the XMAC's 2425 * GMII mode. 2426 */ 2427 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2428 int i = 0; 2429 uint32_t val; 2430 uint16_t phyval; 2431 2432 /* Take PHY out of reset. */ 2433 val = sk_win_read_4(sc, SK_GPIO); 2434 if (sc_if->sk_port == SK_PORT_A) 2435 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2436 else 2437 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2438 sk_win_write_4(sc, SK_GPIO, val); 2439 2440 /* Enable GMII mode on the XMAC. */ 2441 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2442 2443 sk_xmac_miibus_writereg(sc_if->sk_dev, 2444 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2445 DELAY(10000); 2446 sk_xmac_miibus_writereg(sc_if->sk_dev, 2447 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2448 2449 /* 2450 * Early versions of the BCM5400 apparently have 2451 * a bug that requires them to have their reserved 2452 * registers initialized to some magic values. I don't 2453 * know what the numbers do, I'm just the messenger. 2454 */ 2455 sk_xmac_miibus_readreg(sc_if->sk_dev, 2456 SK_PHYADDR_BCOM, 0x03, &phyval); 2457 if (phyval == 0x6041) { 2458 while (bhack[i].reg) { 2459 sk_xmac_miibus_writereg(sc_if->sk_dev, 2460 SK_PHYADDR_BCOM, bhack[i].reg, 2461 bhack[i].val); 2462 i++; 2463 } 2464 } 2465 } 2466 } 2467 2468 static void 2469 sk_init_xmac(struct sk_if_softc *sc_if) 2470 { 2471 struct sk_softc *sc = sc_if->sk_softc; 2472 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2473 2474 sk_unreset_xmac(sc_if); 2475 2476 /* Set station address */ 2477 SK_XM_WRITE_2(sc_if, XM_PAR0, 2478 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2479 SK_XM_WRITE_2(sc_if, XM_PAR1, 2480 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2481 SK_XM_WRITE_2(sc_if, XM_PAR2, 2482 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2483 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2484 2485 if (ifp->if_flags & IFF_PROMISC) 2486 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2487 else 2488 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2489 2490 if (ifp->if_flags & IFF_BROADCAST) 2491 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2492 else 2493 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2494 2495 /* We don't need the FCS appended to the packet. */ 2496 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2497 2498 /* We want short frames padded to 60 bytes. */ 2499 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2500 2501 /* 2502 * Enable the reception of all error frames. This is 2503 * a necessary evil due to the design of the XMAC. The 2504 * XMAC's receive FIFO is only 8K in size, however jumbo 2505 * frames can be up to 9000 bytes in length. When bad 2506 * frame filtering is enabled, the XMAC's RX FIFO operates 2507 * in 'store and forward' mode. For this to work, the 2508 * entire frame has to fit into the FIFO, but that means 2509 * that jumbo frames larger than 8192 bytes will be 2510 * truncated. Disabling all bad frame filtering causes 2511 * the RX FIFO to operate in streaming mode, in which 2512 * case the XMAC will start transferring frames out of the 2513 * RX FIFO as soon as the FIFO threshold is reached. 2514 */ 2515 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2516 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2517 XM_MODE_RX_INRANGELEN); 2518 2519 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2520 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2521 else 2522 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2523 2524 /* 2525 * Bump up the transmit threshold. This helps hold off transmit 2526 * underruns when we're blasting traffic from both ports at once. 2527 */ 2528 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2529 2530 /* Set multicast filter */ 2531 sk_setmulti(sc_if); 2532 2533 /* Clear and enable interrupts */ 2534 SK_XM_READ_2(sc_if, XM_ISR); 2535 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2536 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2537 else 2538 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2539 2540 /* Configure MAC arbiter */ 2541 switch (sc_if->sk_xmac_rev) { 2542 case XM_XMAC_REV_B2: 2543 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2544 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2545 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2546 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2547 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2548 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2549 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2550 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2551 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2552 break; 2553 case XM_XMAC_REV_C1: 2554 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2555 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2556 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2557 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2558 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2559 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2560 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2561 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2562 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2563 break; 2564 default: 2565 break; 2566 } 2567 sk_win_write_2(sc, SK_MACARB_CTL, 2568 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2569 2570 sc_if->sk_link = 1; 2571 } 2572 2573 static void 2574 sk_unreset_yukon(struct sk_if_softc *sc_if) 2575 { 2576 uint32_t /*mac, */phy; 2577 struct sk_softc *sc; 2578 2579 DPRINTFN(1, ("sk_unreset_yukon: start: sk_csr=%#x\n", 2580 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2581 2582 sc = sc_if->sk_softc; 2583 if (sc->sk_type == SK_YUKON_LITE && 2584 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2585 /* Take PHY out of reset. */ 2586 sk_win_write_4(sc, SK_GPIO, 2587 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) 2588 & ~SK_GPIO_DAT9); 2589 } 2590 2591 /* GMAC and GPHY Reset */ 2592 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2593 2594 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2595 2596 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2597 DELAY(1000); 2598 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2599 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2600 DELAY(1000); 2601 2602 2603 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2604 2605 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2606 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2607 2608 switch (sc_if->sk_softc->sk_pmd) { 2609 case IFM_1000_SX: 2610 case IFM_1000_LX: 2611 phy |= SK_GPHY_FIBER; 2612 break; 2613 2614 case IFM_1000_CX: 2615 case IFM_1000_T: 2616 phy |= SK_GPHY_COPPER; 2617 break; 2618 } 2619 2620 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2621 2622 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2623 DELAY(1000); 2624 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2625 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2626 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2627 2628 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2629 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2630 } 2631 2632 static void 2633 sk_init_yukon(struct sk_if_softc *sc_if) 2634 { 2635 uint16_t reg; 2636 int i; 2637 2638 DPRINTFN(1, ("sk_init_yukon: start\n")); 2639 sk_unreset_yukon(sc_if); 2640 2641 /* unused read of the interrupt source register */ 2642 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2643 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2644 2645 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2646 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2647 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2648 2649 /* MIB Counter Clear Mode set */ 2650 reg |= YU_PAR_MIB_CLR; 2651 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2652 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2653 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2654 2655 /* MIB Counter Clear Mode clear */ 2656 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2657 reg &= ~YU_PAR_MIB_CLR; 2658 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2659 2660 /* receive control reg */ 2661 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2662 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2663 YU_RCR_CRCR); 2664 2665 /* transmit parameter register */ 2666 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2667 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2668 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a)); 2669 2670 /* serial mode register */ 2671 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2672 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2673 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2674 YU_SMR_IPG_DATA(0x1e)); 2675 2676 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2677 /* Setup Yukon's address */ 2678 for (i = 0; i < 3; i++) { 2679 /* Write Source Address 1 (unicast filter) */ 2680 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2681 sc_if->sk_enaddr[i * 2] | 2682 sc_if->sk_enaddr[i * 2 + 1] << 8); 2683 } 2684 2685 for (i = 0; i < 3; i++) { 2686 reg = sk_win_read_2(sc_if->sk_softc, 2687 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2688 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2689 } 2690 2691 /* Set multicast filter */ 2692 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2693 sk_setmulti(sc_if); 2694 2695 /* enable interrupt mask for counter overflows */ 2696 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2697 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2698 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2699 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2700 2701 /* Configure RX MAC FIFO */ 2702 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2703 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2704 2705 /* Configure TX MAC FIFO */ 2706 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2707 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2708 2709 DPRINTFN(6, ("sk_init_yukon: end\n")); 2710 } 2711 2712 /* 2713 * Note that to properly initialize any part of the GEnesis chip, 2714 * you first have to take it out of reset mode. 2715 */ 2716 static int 2717 sk_init(struct ifnet *ifp) 2718 { 2719 struct sk_if_softc *sc_if = ifp->if_softc; 2720 struct sk_softc *sc = sc_if->sk_softc; 2721 struct mii_data *mii = &sc_if->sk_mii; 2722 int rc = 0, s; 2723 uint32_t imr, imtimer_ticks; 2724 2725 DPRINTFN(1, ("sk_init\n")); 2726 2727 s = splnet(); 2728 2729 if (ifp->if_flags & IFF_RUNNING) { 2730 splx(s); 2731 return 0; 2732 } 2733 2734 /* Cancel pending I/O and free all RX/TX buffers. */ 2735 sk_stop(ifp, 0); 2736 2737 if (sc->sk_type == SK_GENESIS) { 2738 /* Configure LINK_SYNC LED */ 2739 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2740 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2741 SK_LINKLED_LINKSYNC_ON); 2742 2743 /* Configure RX LED */ 2744 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2745 SK_RXLEDCTL_COUNTER_START); 2746 2747 /* Configure TX LED */ 2748 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2749 SK_TXLEDCTL_COUNTER_START); 2750 } 2751 2752 /* Configure I2C registers */ 2753 2754 /* Configure XMAC(s) */ 2755 switch (sc->sk_type) { 2756 case SK_GENESIS: 2757 sk_init_xmac(sc_if); 2758 break; 2759 case SK_YUKON: 2760 case SK_YUKON_LITE: 2761 case SK_YUKON_LP: 2762 sk_init_yukon(sc_if); 2763 break; 2764 } 2765 if ((rc = mii_mediachg(mii)) == ENXIO) 2766 rc = 0; 2767 else if (rc != 0) 2768 goto out; 2769 2770 if (sc->sk_type == SK_GENESIS) { 2771 /* Configure MAC FIFOs */ 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2774 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2775 2776 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2777 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2778 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2779 } 2780 2781 /* Configure transmit arbiter(s) */ 2782 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2783 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2784 2785 /* Configure RAMbuffers */ 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2791 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2792 2793 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2794 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2795 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2796 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2799 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2800 2801 /* Configure BMUs */ 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2804 SK_RX_RING_ADDR(sc_if, 0)); 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2806 2807 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2808 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2809 SK_TX_RING_ADDR(sc_if, 0)); 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2811 2812 /* Init descriptors */ 2813 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2814 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2815 "memory for rx buffers\n"); 2816 sk_stop(ifp, 0); 2817 splx(s); 2818 return ENOBUFS; 2819 } 2820 2821 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2822 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2823 "memory for tx buffers\n"); 2824 sk_stop(ifp, 0); 2825 splx(s); 2826 return ENOBUFS; 2827 } 2828 2829 /* Set interrupt moderation if changed via sysctl. */ 2830 switch (sc->sk_type) { 2831 case SK_GENESIS: 2832 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2833 break; 2834 case SK_YUKON_EC: 2835 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2836 break; 2837 default: 2838 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2839 } 2840 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2841 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2842 sk_win_write_4(sc, SK_IMTIMERINIT, 2843 SK_IM_USECS(sc->sk_int_mod)); 2844 aprint_verbose_dev(sc->sk_dev, 2845 "interrupt moderation is %d us\n", sc->sk_int_mod); 2846 } 2847 2848 /* Configure interrupt handling */ 2849 CSR_READ_4(sc, SK_ISSR); 2850 if (sc_if->sk_port == SK_PORT_A) 2851 sc->sk_intrmask |= SK_INTRS1; 2852 else 2853 sc->sk_intrmask |= SK_INTRS2; 2854 2855 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2856 2857 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2858 2859 /* Start BMUs. */ 2860 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2861 2862 if (sc->sk_type == SK_GENESIS) { 2863 /* Enable XMACs TX and RX state machines */ 2864 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2865 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2866 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2867 } 2868 2869 if (SK_YUKON_FAMILY(sc->sk_type)) { 2870 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2871 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2872 #if 0 2873 /* XXX disable 100Mbps and full duplex mode? */ 2874 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2875 #endif 2876 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2877 } 2878 2879 2880 ifp->if_flags |= IFF_RUNNING; 2881 ifp->if_flags &= ~IFF_OACTIVE; 2882 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2883 2884 out: 2885 splx(s); 2886 return rc; 2887 } 2888 2889 static void 2890 sk_stop(struct ifnet *ifp, int disable) 2891 { 2892 struct sk_if_softc *sc_if = ifp->if_softc; 2893 struct sk_softc *sc = sc_if->sk_softc; 2894 int i; 2895 2896 DPRINTFN(1, ("sk_stop\n")); 2897 2898 callout_stop(&sc_if->sk_tick_ch); 2899 2900 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2901 uint32_t val; 2902 2903 /* Put PHY back into reset. */ 2904 val = sk_win_read_4(sc, SK_GPIO); 2905 if (sc_if->sk_port == SK_PORT_A) { 2906 val |= SK_GPIO_DIR0; 2907 val &= ~SK_GPIO_DAT0; 2908 } else { 2909 val |= SK_GPIO_DIR2; 2910 val &= ~SK_GPIO_DAT2; 2911 } 2912 sk_win_write_4(sc, SK_GPIO, val); 2913 } 2914 2915 /* Turn off various components of this interface. */ 2916 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2917 switch (sc->sk_type) { 2918 case SK_GENESIS: 2919 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2920 SK_TXMACCTL_XMAC_RESET); 2921 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2922 break; 2923 case SK_YUKON: 2924 case SK_YUKON_LITE: 2925 case SK_YUKON_LP: 2926 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2927 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2928 break; 2929 } 2930 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2931 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2932 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2933 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2934 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2935 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2936 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2937 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2938 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2939 2940 /* Disable interrupts */ 2941 if (sc_if->sk_port == SK_PORT_A) 2942 sc->sk_intrmask &= ~SK_INTRS1; 2943 else 2944 sc->sk_intrmask &= ~SK_INTRS2; 2945 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2946 2947 SK_XM_READ_2(sc_if, XM_ISR); 2948 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2949 2950 /* Free RX and TX mbufs still in the queues. */ 2951 for (i = 0; i < SK_RX_RING_CNT; i++) { 2952 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2953 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2954 } 2955 2956 for (i = 0; i < SK_TX_RING_CNT; i++) { 2957 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2958 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2959 } 2960 2961 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2962 } 2963 2964 /* Power Management Framework */ 2965 2966 static bool 2967 skc_suspend(device_t dv, const pmf_qual_t *qual) 2968 { 2969 struct sk_softc *sc = device_private(dv); 2970 2971 DPRINTFN(2, ("skc_suspend\n")); 2972 2973 /* Turn off the driver is loaded LED */ 2974 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2975 2976 return true; 2977 } 2978 2979 static bool 2980 skc_resume(device_t dv, const pmf_qual_t *qual) 2981 { 2982 struct sk_softc *sc = device_private(dv); 2983 2984 DPRINTFN(2, ("skc_resume\n")); 2985 2986 sk_reset(sc); 2987 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2988 2989 return true; 2990 } 2991 2992 static bool 2993 sk_resume(device_t dv, const pmf_qual_t *qual) 2994 { 2995 struct sk_if_softc *sc_if = device_private(dv); 2996 2997 sk_init_yukon(sc_if); 2998 return true; 2999 } 3000 3001 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3002 skc_probe, skc_attach, NULL, NULL); 3003 3004 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3005 sk_probe, sk_attach, NULL, NULL); 3006 3007 #ifdef SK_DEBUG 3008 static void 3009 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3010 { 3011 #define DESC_PRINT(X) \ 3012 if (X) \ 3013 printf("txdesc[%d]." #X "=%#x\n", \ 3014 idx, X); 3015 3016 DESC_PRINT(le32toh(desc->sk_ctl)); 3017 DESC_PRINT(le32toh(desc->sk_next)); 3018 DESC_PRINT(le32toh(desc->sk_data_lo)); 3019 DESC_PRINT(le32toh(desc->sk_data_hi)); 3020 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3021 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3022 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3023 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3024 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3025 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3026 #undef PRINT 3027 } 3028 3029 static void 3030 sk_dump_bytes(const char *data, int len) 3031 { 3032 int c, i, j; 3033 3034 for (i = 0; i < len; i += 16) { 3035 printf("%08x ", i); 3036 c = len - i; 3037 if (c > 16) c = 16; 3038 3039 for (j = 0; j < c; j++) { 3040 printf("%02x ", data[i + j] & 0xff); 3041 if ((j & 0xf) == 7 && j > 0) 3042 printf(" "); 3043 } 3044 3045 for (; j < 16; j++) 3046 printf(" "); 3047 printf(" "); 3048 3049 for (j = 0; j < c; j++) { 3050 int ch = data[i + j] & 0xff; 3051 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3052 } 3053 3054 printf("\n"); 3055 3056 if (c < 16) 3057 break; 3058 } 3059 } 3060 3061 static void 3062 sk_dump_mbuf(struct mbuf *m) 3063 { 3064 int count = m->m_pkthdr.len; 3065 3066 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3067 3068 while (count > 0 && m) { 3069 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3070 m, m->m_data, m->m_len); 3071 sk_dump_bytes(mtod(m, char *), m->m_len); 3072 3073 count -= m->m_len; 3074 m = m->m_next; 3075 } 3076 } 3077 #endif 3078 3079 static int 3080 sk_sysctl_handler(SYSCTLFN_ARGS) 3081 { 3082 int error, t; 3083 struct sysctlnode node; 3084 struct sk_softc *sc; 3085 3086 node = *rnode; 3087 sc = node.sysctl_data; 3088 t = sc->sk_int_mod; 3089 node.sysctl_data = &t; 3090 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3091 if (error || newp == NULL) 3092 return error; 3093 3094 if (t < SK_IM_MIN || t > SK_IM_MAX) 3095 return EINVAL; 3096 3097 /* update the softc with sysctl-changed value, and mark 3098 for hardware update */ 3099 sc->sk_int_mod = t; 3100 sc->sk_int_mod_pending = 1; 3101 return 0; 3102 } 3103 3104 /* 3105 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3106 * set up in skc_attach() 3107 */ 3108 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3109 { 3110 int rc; 3111 const struct sysctlnode *node; 3112 3113 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3114 0, CTLTYPE_NODE, "sk", 3115 SYSCTL_DESCR("sk interface controls"), 3116 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3117 goto err; 3118 } 3119 3120 sk_root_num = node->sysctl_num; 3121 return; 3122 3123 err: 3124 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3125 } 3126
Indexes created Sat Oct 11 08:10:02 GMT 2025