1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h> 13 #include <dt-bindings/clock/qcom,rpmh.h> 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h> 15 #include <dt-bindings/interconnect/qcom,osm-l3.h> 16 #include <dt-bindings/interconnect/qcom,sdm845.h> 17 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 #include <dt-bindings/phy/phy-qcom-qusb2.h> 19 #include <dt-bindings/power/qcom-rpmpd.h> 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 22 #include <dt-bindings/soc/qcom,apr.h> 23 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 24 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 25 #include <dt-bindings/thermal/thermal.h> 26 27 / { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 chosen { }; 69 70 memory@80000000 { 71 device_type = "memory"; 72 /* We expect the bootloader to fill in the size */ 73 reg = <0 0x80000000 0 0>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hyp_mem: memory@85700000 { 82 reg = <0 0x85700000 0 0x600000>; 83 no-map; 84 }; 85 86 xbl_mem: memory@85e00000 { 87 reg = <0 0x85e00000 0 0x100000>; 88 no-map; 89 }; 90 91 aop_mem: memory@85fc0000 { 92 reg = <0 0x85fc0000 0 0x20000>; 93 no-map; 94 }; 95 96 aop_cmd_db_mem: memory@85fe0000 { 97 compatible = "qcom,cmd-db"; 98 reg = <0x0 0x85fe0000 0 0x20000>; 99 no-map; 100 }; 101 102 smem_mem: memory@86000000 { 103 reg = <0x0 0x86000000 0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@86200000 { 108 reg = <0 0x86200000 0 0x2d00000>; 109 no-map; 110 }; 111 112 rmtfs_mem: memory@88f00000 { 113 compatible = "qcom,rmtfs-mem"; 114 reg = <0 0x88f00000 0 0x200000>; 115 no-map; 116 117 qcom,client-id = <1>; 118 qcom,vmid = <15>; 119 }; 120 121 qseecom_mem: memory@8ab00000 { 122 reg = <0 0x8ab00000 0 0x1400000>; 123 no-map; 124 }; 125 126 camera_mem: memory@8bf00000 { 127 reg = <0 0x8bf00000 0 0x500000>; 128 no-map; 129 }; 130 131 ipa_fw_mem: memory@8c400000 { 132 reg = <0 0x8c400000 0 0x10000>; 133 no-map; 134 }; 135 136 ipa_gsi_mem: memory@8c410000 { 137 reg = <0 0x8c410000 0 0x5000>; 138 no-map; 139 }; 140 141 gpu_mem: memory@8c415000 { 142 reg = <0 0x8c415000 0 0x2000>; 143 no-map; 144 }; 145 146 adsp_mem: memory@8c500000 { 147 reg = <0 0x8c500000 0 0x1a00000>; 148 no-map; 149 }; 150 151 wlan_msa_mem: memory@8df00000 { 152 reg = <0 0x8df00000 0 0x100000>; 153 no-map; 154 }; 155 156 mpss_region: memory@8e000000 { 157 reg = <0 0x8e000000 0 0x7800000>; 158 no-map; 159 }; 160 161 venus_mem: memory@95800000 { 162 reg = <0 0x95800000 0 0x500000>; 163 no-map; 164 }; 165 166 cdsp_mem: memory@95d00000 { 167 reg = <0 0x95d00000 0 0x800000>; 168 no-map; 169 }; 170 171 mba_region: memory@96500000 { 172 reg = <0 0x96500000 0 0x200000>; 173 no-map; 174 }; 175 176 slpi_mem: memory@96700000 { 177 reg = <0 0x96700000 0 0x1400000>; 178 no-map; 179 }; 180 181 spss_mem: memory@97b00000 { 182 reg = <0 0x97b00000 0 0x100000>; 183 no-map; 184 }; 185 }; 186 187 cpus { 188 #address-cells = <2>; 189 #size-cells = <0>; 190 191 CPU0: cpu@0 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo385"; 194 reg = <0x0 0x0>; 195 enable-method = "psci"; 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 197 &LITTLE_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 capacity-dmips-mhz = <607>; 200 dynamic-power-coefficient = <100>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 operating-points-v2 = <&cpu0_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 #cooling-cells = <2>; 206 next-level-cache = <&L2_0>; 207 L2_0: l2-cache { 208 compatible = "cache"; 209 next-level-cache = <&L3_0>; 210 L3_0: l3-cache { 211 compatible = "cache"; 212 }; 213 }; 214 }; 215 216 CPU1: cpu@100 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo385"; 219 reg = <0x0 0x100>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <607>; 225 dynamic-power-coefficient = <100>; 226 qcom,freq-domain = <&cpufreq_hw 0>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 next-level-cache = <&L2_100>; 232 L2_100: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU2: cpu@200 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo385"; 241 reg = <0x0 0x200>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <607>; 247 dynamic-power-coefficient = <100>; 248 qcom,freq-domain = <&cpufreq_hw 0>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 next-level-cache = <&L2_200>; 254 L2_200: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU3: cpu@300 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo385"; 263 reg = <0x0 0x300>; 264 enable-method = "psci"; 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 266 &LITTLE_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <607>; 269 dynamic-power-coefficient = <100>; 270 qcom,freq-domain = <&cpufreq_hw 0>; 271 operating-points-v2 = <&cpu0_opp_table>; 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 next-level-cache = <&L2_300>; 276 L2_300: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU4: cpu@400 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo385"; 285 reg = <0x0 0x400>; 286 enable-method = "psci"; 287 capacity-dmips-mhz = <1024>; 288 cpu-idle-states = <&BIG_CPU_SLEEP_0 289 &BIG_CPU_SLEEP_1 290 &CLUSTER_SLEEP_0>; 291 dynamic-power-coefficient = <396>; 292 qcom,freq-domain = <&cpufreq_hw 1>; 293 operating-points-v2 = <&cpu4_opp_table>; 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 next-level-cache = <&L2_400>; 298 L2_400: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 CPU5: cpu@500 { 305 device_type = "cpu"; 306 compatible = "qcom,kryo385"; 307 reg = <0x0 0x500>; 308 enable-method = "psci"; 309 capacity-dmips-mhz = <1024>; 310 cpu-idle-states = <&BIG_CPU_SLEEP_0 311 &BIG_CPU_SLEEP_1 312 &CLUSTER_SLEEP_0>; 313 dynamic-power-coefficient = <396>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 operating-points-v2 = <&cpu4_opp_table>; 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 318 #cooling-cells = <2>; 319 next-level-cache = <&L2_500>; 320 L2_500: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 CPU6: cpu@600 { 327 device_type = "cpu"; 328 compatible = "qcom,kryo385"; 329 reg = <0x0 0x600>; 330 enable-method = "psci"; 331 capacity-dmips-mhz = <1024>; 332 cpu-idle-states = <&BIG_CPU_SLEEP_0 333 &BIG_CPU_SLEEP_1 334 &CLUSTER_SLEEP_0>; 335 dynamic-power-coefficient = <396>; 336 qcom,freq-domain = <&cpufreq_hw 1>; 337 operating-points-v2 = <&cpu4_opp_table>; 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 340 #cooling-cells = <2>; 341 next-level-cache = <&L2_600>; 342 L2_600: l2-cache { 343 compatible = "cache"; 344 next-level-cache = <&L3_0>; 345 }; 346 }; 347 348 CPU7: cpu@700 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo385"; 351 reg = <0x0 0x700>; 352 enable-method = "psci"; 353 capacity-dmips-mhz = <1024>; 354 cpu-idle-states = <&BIG_CPU_SLEEP_0 355 &BIG_CPU_SLEEP_1 356 &CLUSTER_SLEEP_0>; 357 dynamic-power-coefficient = <396>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 operating-points-v2 = <&cpu4_opp_table>; 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 362 #cooling-cells = <2>; 363 next-level-cache = <&L2_700>; 364 L2_700: l2-cache { 365 compatible = "cache"; 366 next-level-cache = <&L3_0>; 367 }; 368 }; 369 370 cpu-map { 371 cluster0 { 372 core0 { 373 cpu = <&CPU0>; 374 }; 375 376 core1 { 377 cpu = <&CPU1>; 378 }; 379 380 core2 { 381 cpu = <&CPU2>; 382 }; 383 384 core3 { 385 cpu = <&CPU3>; 386 }; 387 388 core4 { 389 cpu = <&CPU4>; 390 }; 391 392 core5 { 393 cpu = <&CPU5>; 394 }; 395 396 core6 { 397 cpu = <&CPU6>; 398 }; 399 400 core7 { 401 cpu = <&CPU7>; 402 }; 403 }; 404 }; 405 406 idle-states { 407 entry-method = "psci"; 408 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "little-power-down"; 412 arm,psci-suspend-param = <0x40000003>; 413 entry-latency-us = <350>; 414 exit-latency-us = <461>; 415 min-residency-us = <1890>; 416 local-timer-stop; 417 }; 418 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "little-rail-power-down"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <360>; 424 exit-latency-us = <531>; 425 min-residency-us = <3934>; 426 local-timer-stop; 427 }; 428 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 430 compatible = "arm,idle-state"; 431 idle-state-name = "big-power-down"; 432 arm,psci-suspend-param = <0x40000003>; 433 entry-latency-us = <264>; 434 exit-latency-us = <621>; 435 min-residency-us = <952>; 436 local-timer-stop; 437 }; 438 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 440 compatible = "arm,idle-state"; 441 idle-state-name = "big-rail-power-down"; 442 arm,psci-suspend-param = <0x40000004>; 443 entry-latency-us = <702>; 444 exit-latency-us = <1061>; 445 min-residency-us = <4488>; 446 local-timer-stop; 447 }; 448 449 CLUSTER_SLEEP_0: cluster-sleep-0 { 450 compatible = "arm,idle-state"; 451 idle-state-name = "cluster-power-down"; 452 arm,psci-suspend-param = <0x400000F4>; 453 entry-latency-us = <3263>; 454 exit-latency-us = <6562>; 455 min-residency-us = <9987>; 456 local-timer-stop; 457 }; 458 }; 459 }; 460 461 cpu0_opp_table: cpu0_opp_table { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 cpu0_opp1: opp-300000000 { 466 opp-hz = /bits/ 64 <300000000>; 467 opp-peak-kBps = <800000 4800000>; 468 }; 469 470 cpu0_opp2: opp-403200000 { 471 opp-hz = /bits/ 64 <403200000>; 472 opp-peak-kBps = <800000 4800000>; 473 }; 474 475 cpu0_opp3: opp-480000000 { 476 opp-hz = /bits/ 64 <480000000>; 477 opp-peak-kBps = <800000 6451200>; 478 }; 479 480 cpu0_opp4: opp-576000000 { 481 opp-hz = /bits/ 64 <576000000>; 482 opp-peak-kBps = <800000 6451200>; 483 }; 484 485 cpu0_opp5: opp-652800000 { 486 opp-hz = /bits/ 64 <652800000>; 487 opp-peak-kBps = <800000 7680000>; 488 }; 489 490 cpu0_opp6: opp-748800000 { 491 opp-hz = /bits/ 64 <748800000>; 492 opp-peak-kBps = <1804000 9216000>; 493 }; 494 495 cpu0_opp7: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <1804000 9216000>; 498 }; 499 500 cpu0_opp8: opp-902400000 { 501 opp-hz = /bits/ 64 <902400000>; 502 opp-peak-kBps = <1804000 10444800>; 503 }; 504 505 cpu0_opp9: opp-979200000 { 506 opp-hz = /bits/ 64 <979200000>; 507 opp-peak-kBps = <1804000 11980800>; 508 }; 509 510 cpu0_opp10: opp-1056000000 { 511 opp-hz = /bits/ 64 <1056000000>; 512 opp-peak-kBps = <1804000 11980800>; 513 }; 514 515 cpu0_opp11: opp-1132800000 { 516 opp-hz = /bits/ 64 <1132800000>; 517 opp-peak-kBps = <2188000 13516800>; 518 }; 519 520 cpu0_opp12: opp-1228800000 { 521 opp-hz = /bits/ 64 <1228800000>; 522 opp-peak-kBps = <2188000 15052800>; 523 }; 524 525 cpu0_opp13: opp-1324800000 { 526 opp-hz = /bits/ 64 <1324800000>; 527 opp-peak-kBps = <2188000 16588800>; 528 }; 529 530 cpu0_opp14: opp-1420800000 { 531 opp-hz = /bits/ 64 <1420800000>; 532 opp-peak-kBps = <3072000 18124800>; 533 }; 534 535 cpu0_opp15: opp-1516800000 { 536 opp-hz = /bits/ 64 <1516800000>; 537 opp-peak-kBps = <3072000 19353600>; 538 }; 539 540 cpu0_opp16: opp-1612800000 { 541 opp-hz = /bits/ 64 <1612800000>; 542 opp-peak-kBps = <4068000 19353600>; 543 }; 544 545 cpu0_opp17: opp-1689600000 { 546 opp-hz = /bits/ 64 <1689600000>; 547 opp-peak-kBps = <4068000 20889600>; 548 }; 549 550 cpu0_opp18: opp-1766400000 { 551 opp-hz = /bits/ 64 <1766400000>; 552 opp-peak-kBps = <4068000 22425600>; 553 }; 554 }; 555 556 cpu4_opp_table: cpu4_opp_table { 557 compatible = "operating-points-v2"; 558 opp-shared; 559 560 cpu4_opp1: opp-300000000 { 561 opp-hz = /bits/ 64 <300000000>; 562 opp-peak-kBps = <800000 4800000>; 563 }; 564 565 cpu4_opp2: opp-403200000 { 566 opp-hz = /bits/ 64 <403200000>; 567 opp-peak-kBps = <800000 4800000>; 568 }; 569 570 cpu4_opp3: opp-480000000 { 571 opp-hz = /bits/ 64 <480000000>; 572 opp-peak-kBps = <1804000 4800000>; 573 }; 574 575 cpu4_opp4: opp-576000000 { 576 opp-hz = /bits/ 64 <576000000>; 577 opp-peak-kBps = <1804000 4800000>; 578 }; 579 580 cpu4_opp5: opp-652800000 { 581 opp-hz = /bits/ 64 <652800000>; 582 opp-peak-kBps = <1804000 4800000>; 583 }; 584 585 cpu4_opp6: opp-748800000 { 586 opp-hz = /bits/ 64 <748800000>; 587 opp-peak-kBps = <1804000 4800000>; 588 }; 589 590 cpu4_opp7: opp-825600000 { 591 opp-hz = /bits/ 64 <825600000>; 592 opp-peak-kBps = <2188000 9216000>; 593 }; 594 595 cpu4_opp8: opp-902400000 { 596 opp-hz = /bits/ 64 <902400000>; 597 opp-peak-kBps = <2188000 9216000>; 598 }; 599 600 cpu4_opp9: opp-979200000 { 601 opp-hz = /bits/ 64 <979200000>; 602 opp-peak-kBps = <2188000 9216000>; 603 }; 604 605 cpu4_opp10: opp-1056000000 { 606 opp-hz = /bits/ 64 <1056000000>; 607 opp-peak-kBps = <3072000 9216000>; 608 }; 609 610 cpu4_opp11: opp-1132800000 { 611 opp-hz = /bits/ 64 <1132800000>; 612 opp-peak-kBps = <3072000 11980800>; 613 }; 614 615 cpu4_opp12: opp-1209600000 { 616 opp-hz = /bits/ 64 <1209600000>; 617 opp-peak-kBps = <4068000 11980800>; 618 }; 619 620 cpu4_opp13: opp-1286400000 { 621 opp-hz = /bits/ 64 <1286400000>; 622 opp-peak-kBps = <4068000 11980800>; 623 }; 624 625 cpu4_opp14: opp-1363200000 { 626 opp-hz = /bits/ 64 <1363200000>; 627 opp-peak-kBps = <4068000 15052800>; 628 }; 629 630 cpu4_opp15: opp-1459200000 { 631 opp-hz = /bits/ 64 <1459200000>; 632 opp-peak-kBps = <4068000 15052800>; 633 }; 634 635 cpu4_opp16: opp-1536000000 { 636 opp-hz = /bits/ 64 <1536000000>; 637 opp-peak-kBps = <5412000 15052800>; 638 }; 639 640 cpu4_opp17: opp-1612800000 { 641 opp-hz = /bits/ 64 <1612800000>; 642 opp-peak-kBps = <5412000 15052800>; 643 }; 644 645 cpu4_opp18: opp-1689600000 { 646 opp-hz = /bits/ 64 <1689600000>; 647 opp-peak-kBps = <5412000 19353600>; 648 }; 649 650 cpu4_opp19: opp-1766400000 { 651 opp-hz = /bits/ 64 <1766400000>; 652 opp-peak-kBps = <6220000 19353600>; 653 }; 654 655 cpu4_opp20: opp-1843200000 { 656 opp-hz = /bits/ 64 <1843200000>; 657 opp-peak-kBps = <6220000 19353600>; 658 }; 659 660 cpu4_opp21: opp-1920000000 { 661 opp-hz = /bits/ 64 <1920000000>; 662 opp-peak-kBps = <7216000 19353600>; 663 }; 664 665 cpu4_opp22: opp-1996800000 { 666 opp-hz = /bits/ 64 <1996800000>; 667 opp-peak-kBps = <7216000 20889600>; 668 }; 669 670 cpu4_opp23: opp-2092800000 { 671 opp-hz = /bits/ 64 <2092800000>; 672 opp-peak-kBps = <7216000 20889600>; 673 }; 674 675 cpu4_opp24: opp-2169600000 { 676 opp-hz = /bits/ 64 <2169600000>; 677 opp-peak-kBps = <7216000 20889600>; 678 }; 679 680 cpu4_opp25: opp-2246400000 { 681 opp-hz = /bits/ 64 <2246400000>; 682 opp-peak-kBps = <7216000 20889600>; 683 }; 684 685 cpu4_opp26: opp-2323200000 { 686 opp-hz = /bits/ 64 <2323200000>; 687 opp-peak-kBps = <7216000 20889600>; 688 }; 689 690 cpu4_opp27: opp-2400000000 { 691 opp-hz = /bits/ 64 <2400000000>; 692 opp-peak-kBps = <7216000 22425600>; 693 }; 694 695 cpu4_opp28: opp-2476800000 { 696 opp-hz = /bits/ 64 <2476800000>; 697 opp-peak-kBps = <7216000 22425600>; 698 }; 699 700 cpu4_opp29: opp-2553600000 { 701 opp-hz = /bits/ 64 <2553600000>; 702 opp-peak-kBps = <7216000 22425600>; 703 }; 704 705 cpu4_opp30: opp-2649600000 { 706 opp-hz = /bits/ 64 <2649600000>; 707 opp-peak-kBps = <7216000 22425600>; 708 }; 709 710 cpu4_opp31: opp-2745600000 { 711 opp-hz = /bits/ 64 <2745600000>; 712 opp-peak-kBps = <7216000 25497600>; 713 }; 714 715 cpu4_opp32: opp-2803200000 { 716 opp-hz = /bits/ 64 <2803200000>; 717 opp-peak-kBps = <7216000 25497600>; 718 }; 719 }; 720 721 pmu { 722 compatible = "arm,armv8-pmuv3"; 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 timer { 727 compatible = "arm,armv8-timer"; 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 732 }; 733 734 clocks { 735 xo_board: xo-board { 736 compatible = "fixed-clock"; 737 #clock-cells = <0>; 738 clock-frequency = <38400000>; 739 clock-output-names = "xo_board"; 740 }; 741 742 sleep_clk: sleep-clk { 743 compatible = "fixed-clock"; 744 #clock-cells = <0>; 745 clock-frequency = <32764>; 746 }; 747 }; 748 749 firmware { 750 scm { 751 compatible = "qcom,scm-sdm845", "qcom,scm"; 752 }; 753 }; 754 755 adsp_pas: remoteproc-adsp { 756 compatible = "qcom,sdm845-adsp-pas"; 757 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 763 interrupt-names = "wdog", "fatal", "ready", 764 "handover", "stop-ack"; 765 766 clocks = <&rpmhcc RPMH_CXO_CLK>; 767 clock-names = "xo"; 768 769 memory-region = <&adsp_mem>; 770 771 qcom,smem-states = <&adsp_smp2p_out 0>; 772 qcom,smem-state-names = "stop"; 773 774 status = "disabled"; 775 776 glink-edge { 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 778 label = "lpass"; 779 qcom,remote-pid = <2>; 780 mboxes = <&apss_shared 8>; 781 782 apr { 783 compatible = "qcom,apr-v2"; 784 qcom,glink-channels = "apr_audio_svc"; 785 qcom,apr-domain = <APR_DOMAIN_ADSP>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 qcom,intents = <512 20>; 789 790 apr-service@3 { 791 reg = <APR_SVC_ADSP_CORE>; 792 compatible = "qcom,q6core"; 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 794 }; 795 796 q6afe: apr-service@4 { 797 compatible = "qcom,q6afe"; 798 reg = <APR_SVC_AFE>; 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 800 q6afedai: dais { 801 compatible = "qcom,q6afe-dais"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #sound-dai-cells = <1>; 805 }; 806 }; 807 808 q6asm: apr-service@7 { 809 compatible = "qcom,q6asm"; 810 reg = <APR_SVC_ASM>; 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 812 q6asmdai: dais { 813 compatible = "qcom,q6asm-dais"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #sound-dai-cells = <1>; 817 iommus = <&apps_smmu 0x1821 0x0>; 818 }; 819 }; 820 821 q6adm: apr-service@8 { 822 compatible = "qcom,q6adm"; 823 reg = <APR_SVC_ADM>; 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 825 q6routing: routing { 826 compatible = "qcom,q6adm-routing"; 827 #sound-dai-cells = <0>; 828 }; 829 }; 830 }; 831 832 fastrpc { 833 compatible = "qcom,fastrpc"; 834 qcom,glink-channels = "fastrpcglink-apps-dsp"; 835 label = "adsp"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 compute-cb@3 { 840 compatible = "qcom,fastrpc-compute-cb"; 841 reg = <3>; 842 iommus = <&apps_smmu 0x1823 0x0>; 843 }; 844 845 compute-cb@4 { 846 compatible = "qcom,fastrpc-compute-cb"; 847 reg = <4>; 848 iommus = <&apps_smmu 0x1824 0x0>; 849 }; 850 }; 851 }; 852 }; 853 854 cdsp_pas: remoteproc-cdsp { 855 compatible = "qcom,sdm845-cdsp-pas"; 856 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 862 interrupt-names = "wdog", "fatal", "ready", 863 "handover", "stop-ack"; 864 865 clocks = <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "xo"; 867 868 memory-region = <&cdsp_mem>; 869 870 qcom,smem-states = <&cdsp_smp2p_out 0>; 871 qcom,smem-state-names = "stop"; 872 873 status = "disabled"; 874 875 glink-edge { 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 877 label = "turing"; 878 qcom,remote-pid = <5>; 879 mboxes = <&apss_shared 4>; 880 fastrpc { 881 compatible = "qcom,fastrpc"; 882 qcom,glink-channels = "fastrpcglink-apps-dsp"; 883 label = "cdsp"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 compute-cb@1 { 888 compatible = "qcom,fastrpc-compute-cb"; 889 reg = <1>; 890 iommus = <&apps_smmu 0x1401 0x30>; 891 }; 892 893 compute-cb@2 { 894 compatible = "qcom,fastrpc-compute-cb"; 895 reg = <2>; 896 iommus = <&apps_smmu 0x1402 0x30>; 897 }; 898 899 compute-cb@3 { 900 compatible = "qcom,fastrpc-compute-cb"; 901 reg = <3>; 902 iommus = <&apps_smmu 0x1403 0x30>; 903 }; 904 905 compute-cb@4 { 906 compatible = "qcom,fastrpc-compute-cb"; 907 reg = <4>; 908 iommus = <&apps_smmu 0x1404 0x30>; 909 }; 910 911 compute-cb@5 { 912 compatible = "qcom,fastrpc-compute-cb"; 913 reg = <5>; 914 iommus = <&apps_smmu 0x1405 0x30>; 915 }; 916 917 compute-cb@6 { 918 compatible = "qcom,fastrpc-compute-cb"; 919 reg = <6>; 920 iommus = <&apps_smmu 0x1406 0x30>; 921 }; 922 923 compute-cb@7 { 924 compatible = "qcom,fastrpc-compute-cb"; 925 reg = <7>; 926 iommus = <&apps_smmu 0x1407 0x30>; 927 }; 928 929 compute-cb@8 { 930 compatible = "qcom,fastrpc-compute-cb"; 931 reg = <8>; 932 iommus = <&apps_smmu 0x1408 0x30>; 933 }; 934 }; 935 }; 936 }; 937 938 tcsr_mutex: hwlock { 939 compatible = "qcom,tcsr-mutex"; 940 syscon = <&tcsr_mutex_regs 0 0x1000>; 941 #hwlock-cells = <1>; 942 }; 943 944 smem { 945 compatible = "qcom,smem"; 946 memory-region = <&smem_mem>; 947 hwlocks = <&tcsr_mutex 3>; 948 }; 949 950 smp2p-cdsp { 951 compatible = "qcom,smp2p"; 952 qcom,smem = <94>, <432>; 953 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 955 956 mboxes = <&apss_shared 6>; 957 958 qcom,local-pid = <0>; 959 qcom,remote-pid = <5>; 960 961 cdsp_smp2p_out: master-kernel { 962 qcom,entry-name = "master-kernel"; 963 #qcom,smem-state-cells = <1>; 964 }; 965 966 cdsp_smp2p_in: slave-kernel { 967 qcom,entry-name = "slave-kernel"; 968 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 }; 972 }; 973 974 smp2p-lpass { 975 compatible = "qcom,smp2p"; 976 qcom,smem = <443>, <429>; 977 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 979 980 mboxes = <&apss_shared 10>; 981 982 qcom,local-pid = <0>; 983 qcom,remote-pid = <2>; 984 985 adsp_smp2p_out: master-kernel { 986 qcom,entry-name = "master-kernel"; 987 #qcom,smem-state-cells = <1>; 988 }; 989 990 adsp_smp2p_in: slave-kernel { 991 qcom,entry-name = "slave-kernel"; 992 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 }; 996 }; 997 998 smp2p-mpss { 999 compatible = "qcom,smp2p"; 1000 qcom,smem = <435>, <428>; 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1002 mboxes = <&apss_shared 14>; 1003 qcom,local-pid = <0>; 1004 qcom,remote-pid = <1>; 1005 1006 modem_smp2p_out: master-kernel { 1007 qcom,entry-name = "master-kernel"; 1008 #qcom,smem-state-cells = <1>; 1009 }; 1010 1011 modem_smp2p_in: slave-kernel { 1012 qcom,entry-name = "slave-kernel"; 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 }; 1016 1017 ipa_smp2p_out: ipa-ap-to-modem { 1018 qcom,entry-name = "ipa"; 1019 #qcom,smem-state-cells = <1>; 1020 }; 1021 1022 ipa_smp2p_in: ipa-modem-to-ap { 1023 qcom,entry-name = "ipa"; 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 }; 1027 }; 1028 1029 smp2p-slpi { 1030 compatible = "qcom,smp2p"; 1031 qcom,smem = <481>, <430>; 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1033 mboxes = <&apss_shared 26>; 1034 qcom,local-pid = <0>; 1035 qcom,remote-pid = <3>; 1036 1037 slpi_smp2p_out: master-kernel { 1038 qcom,entry-name = "master-kernel"; 1039 #qcom,smem-state-cells = <1>; 1040 }; 1041 1042 slpi_smp2p_in: slave-kernel { 1043 qcom,entry-name = "slave-kernel"; 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 }; 1048 1049 psci { 1050 compatible = "arm,psci-1.0"; 1051 method = "smc"; 1052 }; 1053 1054 soc: soc@0 { 1055 #address-cells = <2>; 1056 #size-cells = <2>; 1057 ranges = <0 0 0 0 0x10 0>; 1058 dma-ranges = <0 0 0 0 0x10 0>; 1059 compatible = "simple-bus"; 1060 1061 gcc: clock-controller@100000 { 1062 compatible = "qcom,gcc-sdm845"; 1063 reg = <0 0x00100000 0 0x1f0000>; 1064 clocks = <&rpmhcc RPMH_CXO_CLK>, 1065 <&rpmhcc RPMH_CXO_CLK_A>, 1066 <&sleep_clk>, 1067 <&pcie0_lane>, 1068 <&pcie1_lane>; 1069 clock-names = "bi_tcxo", 1070 "bi_tcxo_ao", 1071 "sleep_clk", 1072 "pcie_0_pipe_clk", 1073 "pcie_1_pipe_clk"; 1074 #clock-cells = <1>; 1075 #reset-cells = <1>; 1076 #power-domain-cells = <1>; 1077 }; 1078 1079 qfprom@784000 { 1080 compatible = "qcom,qfprom"; 1081 reg = <0 0x00784000 0 0x8ff>; 1082 #address-cells = <1>; 1083 #size-cells = <1>; 1084 1085 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1086 reg = <0x1eb 0x1>; 1087 bits = <1 4>; 1088 }; 1089 1090 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1091 reg = <0x1eb 0x2>; 1092 bits = <6 4>; 1093 }; 1094 }; 1095 1096 rng: rng@793000 { 1097 compatible = "qcom,prng-ee"; 1098 reg = <0 0x00793000 0 0x1000>; 1099 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1100 clock-names = "core"; 1101 }; 1102 1103 qup_opp_table: qup-opp-table { 1104 compatible = "operating-points-v2"; 1105 1106 opp-50000000 { 1107 opp-hz = /bits/ 64 <50000000>; 1108 required-opps = <&rpmhpd_opp_min_svs>; 1109 }; 1110 1111 opp-75000000 { 1112 opp-hz = /bits/ 64 <75000000>; 1113 required-opps = <&rpmhpd_opp_low_svs>; 1114 }; 1115 1116 opp-100000000 { 1117 opp-hz = /bits/ 64 <100000000>; 1118 required-opps = <&rpmhpd_opp_svs>; 1119 }; 1120 1121 opp-128000000 { 1122 opp-hz = /bits/ 64 <128000000>; 1123 required-opps = <&rpmhpd_opp_nom>; 1124 }; 1125 }; 1126 1127 qupv3_id_0: geniqup@8c0000 { 1128 compatible = "qcom,geni-se-qup"; 1129 reg = <0 0x008c0000 0 0x6000>; 1130 clock-names = "m-ahb", "s-ahb"; 1131 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1132 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1133 iommus = <&apps_smmu 0x3 0x0>; 1134 #address-cells = <2>; 1135 #size-cells = <2>; 1136 ranges; 1137 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1138 interconnect-names = "qup-core"; 1139 status = "disabled"; 1140 1141 i2c0: i2c@880000 { 1142 compatible = "qcom,geni-i2c"; 1143 reg = <0 0x00880000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_i2c0_default>; 1148 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 power-domains = <&rpmhpd SDM845_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1154 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1155 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1156 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1157 status = "disabled"; 1158 }; 1159 1160 spi0: spi@880000 { 1161 compatible = "qcom,geni-spi"; 1162 reg = <0 0x00880000 0 0x4000>; 1163 clock-names = "se"; 1164 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&qup_spi0_default>; 1167 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1171 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 status = "disabled"; 1174 }; 1175 1176 uart0: serial@880000 { 1177 compatible = "qcom,geni-uart"; 1178 reg = <0 0x00880000 0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_uart0_default>; 1183 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1184 power-domains = <&rpmhpd SDM845_CX>; 1185 operating-points-v2 = <&qup_opp_table>; 1186 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1187 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c1: i2c@884000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00884000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c1_default>; 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 power-domains = <&rpmhpd SDM845_CX>; 1203 operating-points-v2 = <&qup_opp_table>; 1204 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1205 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1206 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1207 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1208 status = "disabled"; 1209 }; 1210 1211 spi1: spi@884000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00884000 0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_spi1_default>; 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1222 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1223 interconnect-names = "qup-core", "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 uart1: serial@884000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00884000 0 0x4000>; 1230 clock-names = "se"; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart1_default>; 1234 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SDM845_CX>; 1236 operating-points-v2 = <&qup_opp_table>; 1237 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1238 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c2: i2c@888000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0 0x00888000 0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c2_default>; 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 power-domains = <&rpmhpd SDM845_CX>; 1254 operating-points-v2 = <&qup_opp_table>; 1255 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1256 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1257 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1258 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1259 status = "disabled"; 1260 }; 1261 1262 spi2: spi@888000 { 1263 compatible = "qcom,geni-spi"; 1264 reg = <0 0x00888000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_spi2_default>; 1269 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1273 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 uart2: serial@888000 { 1279 compatible = "qcom,geni-uart"; 1280 reg = <0 0x00888000 0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_uart2_default>; 1285 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1286 power-domains = <&rpmhpd SDM845_CX>; 1287 operating-points-v2 = <&qup_opp_table>; 1288 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1289 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1290 interconnect-names = "qup-core", "qup-config"; 1291 status = "disabled"; 1292 }; 1293 1294 i2c3: i2c@88c000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x0088c000 0 0x4000>; 1297 clock-names = "se"; 1298 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1299 pinctrl-names = "default"; 1300 pinctrl-0 = <&qup_i2c3_default>; 1301 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 power-domains = <&rpmhpd SDM845_CX>; 1305 operating-points-v2 = <&qup_opp_table>; 1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1308 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1309 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1310 status = "disabled"; 1311 }; 1312 1313 spi3: spi@88c000 { 1314 compatible = "qcom,geni-spi"; 1315 reg = <0 0x0088c000 0 0x4000>; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_spi3_default>; 1320 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1324 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1325 interconnect-names = "qup-core", "qup-config"; 1326 status = "disabled"; 1327 }; 1328 1329 uart3: serial@88c000 { 1330 compatible = "qcom,geni-uart"; 1331 reg = <0 0x0088c000 0 0x4000>; 1332 clock-names = "se"; 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1334 pinctrl-names = "default"; 1335 pinctrl-0 = <&qup_uart3_default>; 1336 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1337 power-domains = <&rpmhpd SDM845_CX>; 1338 operating-points-v2 = <&qup_opp_table>; 1339 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1340 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1341 interconnect-names = "qup-core", "qup-config"; 1342 status = "disabled"; 1343 }; 1344 1345 i2c4: i2c@890000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0 0x00890000 0 0x4000>; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_i2c4_default>; 1352 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 power-domains = <&rpmhpd SDM845_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1358 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1359 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1360 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1361 status = "disabled"; 1362 }; 1363 1364 spi4: spi@890000 { 1365 compatible = "qcom,geni-spi"; 1366 reg = <0 0x00890000 0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_spi4_default>; 1371 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1375 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1376 interconnect-names = "qup-core", "qup-config"; 1377 status = "disabled"; 1378 }; 1379 1380 uart4: serial@890000 { 1381 compatible = "qcom,geni-uart"; 1382 reg = <0 0x00890000 0 0x4000>; 1383 clock-names = "se"; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&qup_uart4_default>; 1387 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1388 power-domains = <&rpmhpd SDM845_CX>; 1389 operating-points-v2 = <&qup_opp_table>; 1390 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1391 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1392 interconnect-names = "qup-core", "qup-config"; 1393 status = "disabled"; 1394 }; 1395 1396 i2c5: i2c@894000 { 1397 compatible = "qcom,geni-i2c"; 1398 reg = <0 0x00894000 0 0x4000>; 1399 clock-names = "se"; 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_i2c5_default>; 1403 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 power-domains = <&rpmhpd SDM845_CX>; 1407 operating-points-v2 = <&qup_opp_table>; 1408 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1409 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1410 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1411 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1412 status = "disabled"; 1413 }; 1414 1415 spi5: spi@894000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0 0x00894000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_spi5_default>; 1422 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1426 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1427 interconnect-names = "qup-core", "qup-config"; 1428 status = "disabled"; 1429 }; 1430 1431 uart5: serial@894000 { 1432 compatible = "qcom,geni-uart"; 1433 reg = <0 0x00894000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_uart5_default>; 1438 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1439 power-domains = <&rpmhpd SDM845_CX>; 1440 operating-points-v2 = <&qup_opp_table>; 1441 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1442 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1443 interconnect-names = "qup-core", "qup-config"; 1444 status = "disabled"; 1445 }; 1446 1447 i2c6: i2c@898000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0 0x00898000 0 0x4000>; 1450 clock-names = "se"; 1451 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_i2c6_default>; 1454 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 power-domains = <&rpmhpd SDM845_CX>; 1458 operating-points-v2 = <&qup_opp_table>; 1459 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1460 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1461 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1462 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1463 status = "disabled"; 1464 }; 1465 1466 spi6: spi@898000 { 1467 compatible = "qcom,geni-spi"; 1468 reg = <0 0x00898000 0 0x4000>; 1469 clock-names = "se"; 1470 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_spi6_default>; 1473 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1477 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1478 interconnect-names = "qup-core", "qup-config"; 1479 status = "disabled"; 1480 }; 1481 1482 uart6: serial@898000 { 1483 compatible = "qcom,geni-uart"; 1484 reg = <0 0x00898000 0 0x4000>; 1485 clock-names = "se"; 1486 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1487 pinctrl-names = "default"; 1488 pinctrl-0 = <&qup_uart6_default>; 1489 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1490 power-domains = <&rpmhpd SDM845_CX>; 1491 operating-points-v2 = <&qup_opp_table>; 1492 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1493 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1494 interconnect-names = "qup-core", "qup-config"; 1495 status = "disabled"; 1496 }; 1497 1498 i2c7: i2c@89c000 { 1499 compatible = "qcom,geni-i2c"; 1500 reg = <0 0x0089c000 0 0x4000>; 1501 clock-names = "se"; 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_i2c7_default>; 1505 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 power-domains = <&rpmhpd SDM845_CX>; 1509 operating-points-v2 = <&qup_opp_table>; 1510 status = "disabled"; 1511 }; 1512 1513 spi7: spi@89c000 { 1514 compatible = "qcom,geni-spi"; 1515 reg = <0 0x0089c000 0 0x4000>; 1516 clock-names = "se"; 1517 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1518 pinctrl-names = "default"; 1519 pinctrl-0 = <&qup_spi7_default>; 1520 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1524 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1525 interconnect-names = "qup-core", "qup-config"; 1526 status = "disabled"; 1527 }; 1528 1529 uart7: serial@89c000 { 1530 compatible = "qcom,geni-uart"; 1531 reg = <0 0x0089c000 0 0x4000>; 1532 clock-names = "se"; 1533 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1534 pinctrl-names = "default"; 1535 pinctrl-0 = <&qup_uart7_default>; 1536 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1537 power-domains = <&rpmhpd SDM845_CX>; 1538 operating-points-v2 = <&qup_opp_table>; 1539 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1540 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1541 interconnect-names = "qup-core", "qup-config"; 1542 status = "disabled"; 1543 }; 1544 }; 1545 1546 qupv3_id_1: geniqup@ac0000 { 1547 compatible = "qcom,geni-se-qup"; 1548 reg = <0 0x00ac0000 0 0x6000>; 1549 clock-names = "m-ahb", "s-ahb"; 1550 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1551 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1552 iommus = <&apps_smmu 0x6c3 0x0>; 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges; 1556 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1557 interconnect-names = "qup-core"; 1558 status = "disabled"; 1559 1560 i2c8: i2c@a80000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00a80000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c8_default>; 1567 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 power-domains = <&rpmhpd SDM845_CX>; 1571 operating-points-v2 = <&qup_opp_table>; 1572 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1574 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1575 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1576 status = "disabled"; 1577 }; 1578 1579 spi8: spi@a80000 { 1580 compatible = "qcom,geni-spi"; 1581 reg = <0 0x00a80000 0 0x4000>; 1582 clock-names = "se"; 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1584 pinctrl-names = "default"; 1585 pinctrl-0 = <&qup_spi8_default>; 1586 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1590 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1591 interconnect-names = "qup-core", "qup-config"; 1592 status = "disabled"; 1593 }; 1594 1595 uart8: serial@a80000 { 1596 compatible = "qcom,geni-uart"; 1597 reg = <0 0x00a80000 0 0x4000>; 1598 clock-names = "se"; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_uart8_default>; 1602 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1603 power-domains = <&rpmhpd SDM845_CX>; 1604 operating-points-v2 = <&qup_opp_table>; 1605 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1606 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1607 interconnect-names = "qup-core", "qup-config"; 1608 status = "disabled"; 1609 }; 1610 1611 i2c9: i2c@a84000 { 1612 compatible = "qcom,geni-i2c"; 1613 reg = <0 0x00a84000 0 0x4000>; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_i2c9_default>; 1618 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 power-domains = <&rpmhpd SDM845_CX>; 1622 operating-points-v2 = <&qup_opp_table>; 1623 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1624 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1625 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 status = "disabled"; 1628 }; 1629 1630 spi9: spi@a84000 { 1631 compatible = "qcom,geni-spi"; 1632 reg = <0 0x00a84000 0 0x4000>; 1633 clock-names = "se"; 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&qup_spi9_default>; 1637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1641 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1642 interconnect-names = "qup-core", "qup-config"; 1643 status = "disabled"; 1644 }; 1645 1646 uart9: serial@a84000 { 1647 compatible = "qcom,geni-debug-uart"; 1648 reg = <0 0x00a84000 0 0x4000>; 1649 clock-names = "se"; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1651 pinctrl-names = "default"; 1652 pinctrl-0 = <&qup_uart9_default>; 1653 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1654 power-domains = <&rpmhpd SDM845_CX>; 1655 operating-points-v2 = <&qup_opp_table>; 1656 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1657 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1658 interconnect-names = "qup-core", "qup-config"; 1659 status = "disabled"; 1660 }; 1661 1662 i2c10: i2c@a88000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00a88000 0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c10_default>; 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 power-domains = <&rpmhpd SDM845_CX>; 1673 operating-points-v2 = <&qup_opp_table>; 1674 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1675 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1676 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1677 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1678 status = "disabled"; 1679 }; 1680 1681 spi10: spi@a88000 { 1682 compatible = "qcom,geni-spi"; 1683 reg = <0 0x00a88000 0 0x4000>; 1684 clock-names = "se"; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1686 pinctrl-names = "default"; 1687 pinctrl-0 = <&qup_spi10_default>; 1688 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1692 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1693 interconnect-names = "qup-core", "qup-config"; 1694 status = "disabled"; 1695 }; 1696 1697 uart10: serial@a88000 { 1698 compatible = "qcom,geni-uart"; 1699 reg = <0 0x00a88000 0 0x4000>; 1700 clock-names = "se"; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&qup_uart10_default>; 1704 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1705 power-domains = <&rpmhpd SDM845_CX>; 1706 operating-points-v2 = <&qup_opp_table>; 1707 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1708 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1709 interconnect-names = "qup-core", "qup-config"; 1710 status = "disabled"; 1711 }; 1712 1713 i2c11: i2c@a8c000 { 1714 compatible = "qcom,geni-i2c"; 1715 reg = <0 0x00a8c000 0 0x4000>; 1716 clock-names = "se"; 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_i2c11_default>; 1720 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 power-domains = <&rpmhpd SDM845_CX>; 1724 operating-points-v2 = <&qup_opp_table>; 1725 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1726 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1727 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1728 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1729 status = "disabled"; 1730 }; 1731 1732 spi11: spi@a8c000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0 0x00a8c000 0 0x4000>; 1735 clock-names = "se"; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_spi11_default>; 1739 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1743 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1744 interconnect-names = "qup-core", "qup-config"; 1745 status = "disabled"; 1746 }; 1747 1748 uart11: serial@a8c000 { 1749 compatible = "qcom,geni-uart"; 1750 reg = <0 0x00a8c000 0 0x4000>; 1751 clock-names = "se"; 1752 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&qup_uart11_default>; 1755 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1756 power-domains = <&rpmhpd SDM845_CX>; 1757 operating-points-v2 = <&qup_opp_table>; 1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1759 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1760 interconnect-names = "qup-core", "qup-config"; 1761 status = "disabled"; 1762 }; 1763 1764 i2c12: i2c@a90000 { 1765 compatible = "qcom,geni-i2c"; 1766 reg = <0 0x00a90000 0 0x4000>; 1767 clock-names = "se"; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_i2c12_default>; 1771 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SDM845_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1779 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1780 status = "disabled"; 1781 }; 1782 1783 spi12: spi@a90000 { 1784 compatible = "qcom,geni-spi"; 1785 reg = <0 0x00a90000 0 0x4000>; 1786 clock-names = "se"; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&qup_spi12_default>; 1790 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1795 interconnect-names = "qup-core", "qup-config"; 1796 status = "disabled"; 1797 }; 1798 1799 uart12: serial@a90000 { 1800 compatible = "qcom,geni-uart"; 1801 reg = <0 0x00a90000 0 0x4000>; 1802 clock-names = "se"; 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1804 pinctrl-names = "default"; 1805 pinctrl-0 = <&qup_uart12_default>; 1806 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1807 power-domains = <&rpmhpd SDM845_CX>; 1808 operating-points-v2 = <&qup_opp_table>; 1809 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1810 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1811 interconnect-names = "qup-core", "qup-config"; 1812 status = "disabled"; 1813 }; 1814 1815 i2c13: i2c@a94000 { 1816 compatible = "qcom,geni-i2c"; 1817 reg = <0 0x00a94000 0 0x4000>; 1818 clock-names = "se"; 1819 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1820 pinctrl-names = "default"; 1821 pinctrl-0 = <&qup_i2c13_default>; 1822 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 power-domains = <&rpmhpd SDM845_CX>; 1826 operating-points-v2 = <&qup_opp_table>; 1827 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1828 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1829 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1830 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1831 status = "disabled"; 1832 }; 1833 1834 spi13: spi@a94000 { 1835 compatible = "qcom,geni-spi"; 1836 reg = <0 0x00a94000 0 0x4000>; 1837 clock-names = "se"; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1839 pinctrl-names = "default"; 1840 pinctrl-0 = <&qup_spi13_default>; 1841 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1845 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1846 interconnect-names = "qup-core", "qup-config"; 1847 status = "disabled"; 1848 }; 1849 1850 uart13: serial@a94000 { 1851 compatible = "qcom,geni-uart"; 1852 reg = <0 0x00a94000 0 0x4000>; 1853 clock-names = "se"; 1854 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1855 pinctrl-names = "default"; 1856 pinctrl-0 = <&qup_uart13_default>; 1857 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1858 power-domains = <&rpmhpd SDM845_CX>; 1859 operating-points-v2 = <&qup_opp_table>; 1860 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1861 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1862 interconnect-names = "qup-core", "qup-config"; 1863 status = "disabled"; 1864 }; 1865 1866 i2c14: i2c@a98000 { 1867 compatible = "qcom,geni-i2c"; 1868 reg = <0 0x00a98000 0 0x4000>; 1869 clock-names = "se"; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1871 pinctrl-names = "default"; 1872 pinctrl-0 = <&qup_i2c14_default>; 1873 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 power-domains = <&rpmhpd SDM845_CX>; 1877 operating-points-v2 = <&qup_opp_table>; 1878 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1879 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1880 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1881 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1882 status = "disabled"; 1883 }; 1884 1885 spi14: spi@a98000 { 1886 compatible = "qcom,geni-spi"; 1887 reg = <0 0x00a98000 0 0x4000>; 1888 clock-names = "se"; 1889 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_spi14_default>; 1892 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1896 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1897 interconnect-names = "qup-core", "qup-config"; 1898 status = "disabled"; 1899 }; 1900 1901 uart14: serial@a98000 { 1902 compatible = "qcom,geni-uart"; 1903 reg = <0 0x00a98000 0 0x4000>; 1904 clock-names = "se"; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_uart14_default>; 1908 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1909 power-domains = <&rpmhpd SDM845_CX>; 1910 operating-points-v2 = <&qup_opp_table>; 1911 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1912 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1913 interconnect-names = "qup-core", "qup-config"; 1914 status = "disabled"; 1915 }; 1916 1917 i2c15: i2c@a9c000 { 1918 compatible = "qcom,geni-i2c"; 1919 reg = <0 0x00a9c000 0 0x4000>; 1920 clock-names = "se"; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&qup_i2c15_default>; 1924 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 power-domains = <&rpmhpd SDM845_CX>; 1928 operating-points-v2 = <&qup_opp_table>; 1929 status = "disabled"; 1930 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1931 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1932 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1933 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1934 }; 1935 1936 spi15: spi@a9c000 { 1937 compatible = "qcom,geni-spi"; 1938 reg = <0 0x00a9c000 0 0x4000>; 1939 clock-names = "se"; 1940 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1941 pinctrl-names = "default"; 1942 pinctrl-0 = <&qup_spi15_default>; 1943 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1947 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1948 interconnect-names = "qup-core", "qup-config"; 1949 status = "disabled"; 1950 }; 1951 1952 uart15: serial@a9c000 { 1953 compatible = "qcom,geni-uart"; 1954 reg = <0 0x00a9c000 0 0x4000>; 1955 clock-names = "se"; 1956 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1957 pinctrl-names = "default"; 1958 pinctrl-0 = <&qup_uart15_default>; 1959 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1960 power-domains = <&rpmhpd SDM845_CX>; 1961 operating-points-v2 = <&qup_opp_table>; 1962 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1963 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1964 interconnect-names = "qup-core", "qup-config"; 1965 status = "disabled"; 1966 }; 1967 }; 1968 1969 system-cache-controller@1100000 { 1970 compatible = "qcom,sdm845-llcc"; 1971 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1972 reg-names = "llcc_base", "llcc_broadcast_base"; 1973 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1974 }; 1975 1976 pcie0: pci@1c00000 { 1977 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1978 reg = <0 0x01c00000 0 0x2000>, 1979 <0 0x60000000 0 0xf1d>, 1980 <0 0x60000f20 0 0xa8>, 1981 <0 0x60100000 0 0x100000>; 1982 reg-names = "parf", "dbi", "elbi", "config"; 1983 device_type = "pci"; 1984 linux,pci-domain = <0>; 1985 bus-range = <0x00 0xff>; 1986 num-lanes = <1>; 1987 1988 #address-cells = <3>; 1989 #size-cells = <2>; 1990 1991 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1992 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1993 1994 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1995 interrupt-names = "msi"; 1996 #interrupt-cells = <1>; 1997 interrupt-map-mask = <0 0 0 0x7>; 1998 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1999 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2000 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2001 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2002 2003 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2004 <&gcc GCC_PCIE_0_AUX_CLK>, 2005 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2006 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2007 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2008 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2009 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2010 clock-names = "pipe", 2011 "aux", 2012 "cfg", 2013 "bus_master", 2014 "bus_slave", 2015 "slave_q2a", 2016 "tbu"; 2017 2018 iommus = <&apps_smmu 0x1c10 0xf>; 2019 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2020 <0x100 &apps_smmu 0x1c11 0x1>, 2021 <0x200 &apps_smmu 0x1c12 0x1>, 2022 <0x300 &apps_smmu 0x1c13 0x1>, 2023 <0x400 &apps_smmu 0x1c14 0x1>, 2024 <0x500 &apps_smmu 0x1c15 0x1>, 2025 <0x600 &apps_smmu 0x1c16 0x1>, 2026 <0x700 &apps_smmu 0x1c17 0x1>, 2027 <0x800 &apps_smmu 0x1c18 0x1>, 2028 <0x900 &apps_smmu 0x1c19 0x1>, 2029 <0xa00 &apps_smmu 0x1c1a 0x1>, 2030 <0xb00 &apps_smmu 0x1c1b 0x1>, 2031 <0xc00 &apps_smmu 0x1c1c 0x1>, 2032 <0xd00 &apps_smmu 0x1c1d 0x1>, 2033 <0xe00 &apps_smmu 0x1c1e 0x1>, 2034 <0xf00 &apps_smmu 0x1c1f 0x1>; 2035 2036 resets = <&gcc GCC_PCIE_0_BCR>; 2037 reset-names = "pci"; 2038 2039 power-domains = <&gcc PCIE_0_GDSC>; 2040 2041 phys = <&pcie0_lane>; 2042 phy-names = "pciephy"; 2043 2044 status = "disabled"; 2045 }; 2046 2047 pcie0_phy: phy@1c06000 { 2048 compatible = "qcom,sdm845-qmp-pcie-phy"; 2049 reg = <0 0x01c06000 0 0x18c>; 2050 #address-cells = <2>; 2051 #size-cells = <2>; 2052 ranges; 2053 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2054 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2055 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2056 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2057 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2058 2059 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2060 reset-names = "phy"; 2061 2062 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2063 assigned-clock-rates = <100000000>; 2064 2065 status = "disabled"; 2066 2067 pcie0_lane: lanes@1c06200 { 2068 reg = <0 0x01c06200 0 0x128>, 2069 <0 0x01c06400 0 0x1fc>, 2070 <0 0x01c06800 0 0x218>, 2071 <0 0x01c06600 0 0x70>; 2072 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2073 clock-names = "pipe0"; 2074 2075 #clock-cells = <0>; 2076 #phy-cells = <0>; 2077 clock-output-names = "pcie_0_pipe_clk"; 2078 }; 2079 }; 2080 2081 pcie1: pci@1c08000 { 2082 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 2083 reg = <0 0x01c08000 0 0x2000>, 2084 <0 0x40000000 0 0xf1d>, 2085 <0 0x40000f20 0 0xa8>, 2086 <0 0x40100000 0 0x100000>; 2087 reg-names = "parf", "dbi", "elbi", "config"; 2088 device_type = "pci"; 2089 linux,pci-domain = <1>; 2090 bus-range = <0x00 0xff>; 2091 num-lanes = <1>; 2092 2093 #address-cells = <3>; 2094 #size-cells = <2>; 2095 2096 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2097 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2098 2099 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2100 interrupt-names = "msi"; 2101 #interrupt-cells = <1>; 2102 interrupt-map-mask = <0 0 0 0x7>; 2103 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2104 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2105 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2106 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2107 2108 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2109 <&gcc GCC_PCIE_1_AUX_CLK>, 2110 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2111 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2112 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2113 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2114 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2115 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2116 clock-names = "pipe", 2117 "aux", 2118 "cfg", 2119 "bus_master", 2120 "bus_slave", 2121 "slave_q2a", 2122 "ref", 2123 "tbu"; 2124 2125 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2126 assigned-clock-rates = <19200000>; 2127 2128 iommus = <&apps_smmu 0x1c00 0xf>; 2129 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2130 <0x100 &apps_smmu 0x1c01 0x1>, 2131 <0x200 &apps_smmu 0x1c02 0x1>, 2132 <0x300 &apps_smmu 0x1c03 0x1>, 2133 <0x400 &apps_smmu 0x1c04 0x1>, 2134 <0x500 &apps_smmu 0x1c05 0x1>, 2135 <0x600 &apps_smmu 0x1c06 0x1>, 2136 <0x700 &apps_smmu 0x1c07 0x1>, 2137 <0x800 &apps_smmu 0x1c08 0x1>, 2138 <0x900 &apps_smmu 0x1c09 0x1>, 2139 <0xa00 &apps_smmu 0x1c0a 0x1>, 2140 <0xb00 &apps_smmu 0x1c0b 0x1>, 2141 <0xc00 &apps_smmu 0x1c0c 0x1>, 2142 <0xd00 &apps_smmu 0x1c0d 0x1>, 2143 <0xe00 &apps_smmu 0x1c0e 0x1>, 2144 <0xf00 &apps_smmu 0x1c0f 0x1>; 2145 2146 resets = <&gcc GCC_PCIE_1_BCR>; 2147 reset-names = "pci"; 2148 2149 power-domains = <&gcc PCIE_1_GDSC>; 2150 2151 phys = <&pcie1_lane>; 2152 phy-names = "pciephy"; 2153 2154 status = "disabled"; 2155 }; 2156 2157 pcie1_phy: phy@1c0a000 { 2158 compatible = "qcom,sdm845-qhp-pcie-phy"; 2159 reg = <0 0x01c0a000 0 0x800>; 2160 #address-cells = <2>; 2161 #size-cells = <2>; 2162 ranges; 2163 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2164 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2165 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2166 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2167 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2168 2169 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2170 reset-names = "phy"; 2171 2172 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2173 assigned-clock-rates = <100000000>; 2174 2175 status = "disabled"; 2176 2177 pcie1_lane: lanes@1c06200 { 2178 reg = <0 0x01c0a800 0 0x800>, 2179 <0 0x01c0a800 0 0x800>, 2180 <0 0x01c0b800 0 0x400>; 2181 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2182 clock-names = "pipe0"; 2183 2184 #clock-cells = <0>; 2185 #phy-cells = <0>; 2186 clock-output-names = "pcie_1_pipe_clk"; 2187 }; 2188 }; 2189 2190 mem_noc: interconnect@1380000 { 2191 compatible = "qcom,sdm845-mem-noc"; 2192 reg = <0 0x01380000 0 0x27200>; 2193 #interconnect-cells = <2>; 2194 qcom,bcm-voters = <&apps_bcm_voter>; 2195 }; 2196 2197 dc_noc: interconnect@14e0000 { 2198 compatible = "qcom,sdm845-dc-noc"; 2199 reg = <0 0x014e0000 0 0x400>; 2200 #interconnect-cells = <2>; 2201 qcom,bcm-voters = <&apps_bcm_voter>; 2202 }; 2203 2204 config_noc: interconnect@1500000 { 2205 compatible = "qcom,sdm845-config-noc"; 2206 reg = <0 0x01500000 0 0x5080>; 2207 #interconnect-cells = <2>; 2208 qcom,bcm-voters = <&apps_bcm_voter>; 2209 }; 2210 2211 system_noc: interconnect@1620000 { 2212 compatible = "qcom,sdm845-system-noc"; 2213 reg = <0 0x01620000 0 0x18080>; 2214 #interconnect-cells = <2>; 2215 qcom,bcm-voters = <&apps_bcm_voter>; 2216 }; 2217 2218 aggre1_noc: interconnect@16e0000 { 2219 compatible = "qcom,sdm845-aggre1-noc"; 2220 reg = <0 0x016e0000 0 0x15080>; 2221 #interconnect-cells = <2>; 2222 qcom,bcm-voters = <&apps_bcm_voter>; 2223 }; 2224 2225 aggre2_noc: interconnect@1700000 { 2226 compatible = "qcom,sdm845-aggre2-noc"; 2227 reg = <0 0x01700000 0 0x1f300>; 2228 #interconnect-cells = <2>; 2229 qcom,bcm-voters = <&apps_bcm_voter>; 2230 }; 2231 2232 mmss_noc: interconnect@1740000 { 2233 compatible = "qcom,sdm845-mmss-noc"; 2234 reg = <0 0x01740000 0 0x1c100>; 2235 #interconnect-cells = <2>; 2236 qcom,bcm-voters = <&apps_bcm_voter>; 2237 }; 2238 2239 ufs_mem_hc: ufshc@1d84000 { 2240 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2241 "jedec,ufs-2.0"; 2242 reg = <0 0x01d84000 0 0x2500>, 2243 <0 0x01d90000 0 0x8000>; 2244 reg-names = "std", "ice"; 2245 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2246 phys = <&ufs_mem_phy_lanes>; 2247 phy-names = "ufsphy"; 2248 lanes-per-direction = <2>; 2249 power-domains = <&gcc UFS_PHY_GDSC>; 2250 #reset-cells = <1>; 2251 resets = <&gcc GCC_UFS_PHY_BCR>; 2252 reset-names = "rst"; 2253 2254 iommus = <&apps_smmu 0x100 0xf>; 2255 2256 clock-names = 2257 "core_clk", 2258 "bus_aggr_clk", 2259 "iface_clk", 2260 "core_clk_unipro", 2261 "ref_clk", 2262 "tx_lane0_sync_clk", 2263 "rx_lane0_sync_clk", 2264 "rx_lane1_sync_clk", 2265 "ice_core_clk"; 2266 clocks = 2267 <&gcc GCC_UFS_PHY_AXI_CLK>, 2268 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2269 <&gcc GCC_UFS_PHY_AHB_CLK>, 2270 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2271 <&rpmhcc RPMH_CXO_CLK>, 2272 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2273 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2274 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2275 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2276 freq-table-hz = 2277 <50000000 200000000>, 2278 <0 0>, 2279 <0 0>, 2280 <37500000 150000000>, 2281 <0 0>, 2282 <0 0>, 2283 <0 0>, 2284 <0 0>, 2285 <0 300000000>; 2286 2287 status = "disabled"; 2288 }; 2289 2290 ufs_mem_phy: phy@1d87000 { 2291 compatible = "qcom,sdm845-qmp-ufs-phy"; 2292 reg = <0 0x01d87000 0 0x18c>; 2293 #address-cells = <2>; 2294 #size-cells = <2>; 2295 ranges; 2296 clock-names = "ref", 2297 "ref_aux"; 2298 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2299 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2300 2301 resets = <&ufs_mem_hc 0>; 2302 reset-names = "ufsphy"; 2303 status = "disabled"; 2304 2305 ufs_mem_phy_lanes: lanes@1d87400 { 2306 reg = <0 0x01d87400 0 0x108>, 2307 <0 0x01d87600 0 0x1e0>, 2308 <0 0x01d87c00 0 0x1dc>, 2309 <0 0x01d87800 0 0x108>, 2310 <0 0x01d87a00 0 0x1e0>; 2311 #phy-cells = <0>; 2312 }; 2313 }; 2314 2315 cryptobam: dma@1dc4000 { 2316 compatible = "qcom,bam-v1.7.0"; 2317 reg = <0 0x01dc4000 0 0x24000>; 2318 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2319 clocks = <&rpmhcc 15>; 2320 clock-names = "bam_clk"; 2321 #dma-cells = <1>; 2322 qcom,ee = <0>; 2323 qcom,controlled-remotely = <1>; 2324 iommus = <&apps_smmu 0x704 0x1>, 2325 <&apps_smmu 0x706 0x1>, 2326 <&apps_smmu 0x714 0x1>, 2327 <&apps_smmu 0x716 0x1>; 2328 }; 2329 2330 crypto: crypto@1dfa000 { 2331 compatible = "qcom,crypto-v5.4"; 2332 reg = <0 0x01dfa000 0 0x6000>; 2333 clocks = <&gcc GCC_CE1_AHB_CLK>, 2334 <&gcc GCC_CE1_AHB_CLK>, 2335 <&rpmhcc 15>; 2336 clock-names = "iface", "bus", "core"; 2337 dmas = <&cryptobam 6>, <&cryptobam 7>; 2338 dma-names = "rx", "tx"; 2339 iommus = <&apps_smmu 0x704 0x1>, 2340 <&apps_smmu 0x706 0x1>, 2341 <&apps_smmu 0x714 0x1>, 2342 <&apps_smmu 0x716 0x1>; 2343 }; 2344 2345 ipa: ipa@1e40000 { 2346 compatible = "qcom,sdm845-ipa"; 2347 2348 iommus = <&apps_smmu 0x720 0x0>, 2349 <&apps_smmu 0x722 0x0>; 2350 reg = <0 0x1e40000 0 0x7000>, 2351 <0 0x1e47000 0 0x2000>, 2352 <0 0x1e04000 0 0x2c000>; 2353 reg-names = "ipa-reg", 2354 "ipa-shared", 2355 "gsi"; 2356 2357 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2358 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2359 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2360 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2361 interrupt-names = "ipa", 2362 "gsi", 2363 "ipa-clock-query", 2364 "ipa-setup-ready"; 2365 2366 clocks = <&rpmhcc RPMH_IPA_CLK>; 2367 clock-names = "core"; 2368 2369 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2370 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2371 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2372 interconnect-names = "memory", 2373 "imem", 2374 "config"; 2375 2376 qcom,smem-states = <&ipa_smp2p_out 0>, 2377 <&ipa_smp2p_out 1>; 2378 qcom,smem-state-names = "ipa-clock-enabled-valid", 2379 "ipa-clock-enabled"; 2380 2381 status = "disabled"; 2382 }; 2383 2384 tcsr_mutex_regs: syscon@1f40000 { 2385 compatible = "syscon"; 2386 reg = <0 0x01f40000 0 0x40000>; 2387 }; 2388 2389 tlmm: pinctrl@3400000 { 2390 compatible = "qcom,sdm845-pinctrl"; 2391 reg = <0 0x03400000 0 0xc00000>; 2392 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2393 gpio-controller; 2394 #gpio-cells = <2>; 2395 interrupt-controller; 2396 #interrupt-cells = <2>; 2397 gpio-ranges = <&tlmm 0 0 151>; 2398 wakeup-parent = <&pdc_intc>; 2399 2400 cci0_default: cci0-default { 2401 /* SDA, SCL */ 2402 pins = "gpio17", "gpio18"; 2403 function = "cci_i2c"; 2404 2405 bias-pull-up; 2406 drive-strength = <2>; /* 2 mA */ 2407 }; 2408 2409 cci0_sleep: cci0-sleep { 2410 /* SDA, SCL */ 2411 pins = "gpio17", "gpio18"; 2412 function = "cci_i2c"; 2413 2414 drive-strength = <2>; /* 2 mA */ 2415 bias-pull-down; 2416 }; 2417 2418 cci1_default: cci1-default { 2419 /* SDA, SCL */ 2420 pins = "gpio19", "gpio20"; 2421 function = "cci_i2c"; 2422 2423 bias-pull-up; 2424 drive-strength = <2>; /* 2 mA */ 2425 }; 2426 2427 cci1_sleep: cci1-sleep { 2428 /* SDA, SCL */ 2429 pins = "gpio19", "gpio20"; 2430 function = "cci_i2c"; 2431 2432 drive-strength = <2>; /* 2 mA */ 2433 bias-pull-down; 2434 }; 2435 2436 qspi_clk: qspi-clk { 2437 pinmux { 2438 pins = "gpio95"; 2439 function = "qspi_clk"; 2440 }; 2441 }; 2442 2443 qspi_cs0: qspi-cs0 { 2444 pinmux { 2445 pins = "gpio90"; 2446 function = "qspi_cs"; 2447 }; 2448 }; 2449 2450 qspi_cs1: qspi-cs1 { 2451 pinmux { 2452 pins = "gpio89"; 2453 function = "qspi_cs"; 2454 }; 2455 }; 2456 2457 qspi_data01: qspi-data01 { 2458 pinmux-data { 2459 pins = "gpio91", "gpio92"; 2460 function = "qspi_data"; 2461 }; 2462 }; 2463 2464 qspi_data12: qspi-data12 { 2465 pinmux-data { 2466 pins = "gpio93", "gpio94"; 2467 function = "qspi_data"; 2468 }; 2469 }; 2470 2471 qup_i2c0_default: qup-i2c0-default { 2472 pinmux { 2473 pins = "gpio0", "gpio1"; 2474 function = "qup0"; 2475 }; 2476 }; 2477 2478 qup_i2c1_default: qup-i2c1-default { 2479 pinmux { 2480 pins = "gpio17", "gpio18"; 2481 function = "qup1"; 2482 }; 2483 }; 2484 2485 qup_i2c2_default: qup-i2c2-default { 2486 pinmux { 2487 pins = "gpio27", "gpio28"; 2488 function = "qup2"; 2489 }; 2490 }; 2491 2492 qup_i2c3_default: qup-i2c3-default { 2493 pinmux { 2494 pins = "gpio41", "gpio42"; 2495 function = "qup3"; 2496 }; 2497 }; 2498 2499 qup_i2c4_default: qup-i2c4-default { 2500 pinmux { 2501 pins = "gpio89", "gpio90"; 2502 function = "qup4"; 2503 }; 2504 }; 2505 2506 qup_i2c5_default: qup-i2c5-default { 2507 pinmux { 2508 pins = "gpio85", "gpio86"; 2509 function = "qup5"; 2510 }; 2511 }; 2512 2513 qup_i2c6_default: qup-i2c6-default { 2514 pinmux { 2515 pins = "gpio45", "gpio46"; 2516 function = "qup6"; 2517 }; 2518 }; 2519 2520 qup_i2c7_default: qup-i2c7-default { 2521 pinmux { 2522 pins = "gpio93", "gpio94"; 2523 function = "qup7"; 2524 }; 2525 }; 2526 2527 qup_i2c8_default: qup-i2c8-default { 2528 pinmux { 2529 pins = "gpio65", "gpio66"; 2530 function = "qup8"; 2531 }; 2532 }; 2533 2534 qup_i2c9_default: qup-i2c9-default { 2535 pinmux { 2536 pins = "gpio6", "gpio7"; 2537 function = "qup9"; 2538 }; 2539 }; 2540 2541 qup_i2c10_default: qup-i2c10-default { 2542 pinmux { 2543 pins = "gpio55", "gpio56"; 2544 function = "qup10"; 2545 }; 2546 }; 2547 2548 qup_i2c11_default: qup-i2c11-default { 2549 pinmux { 2550 pins = "gpio31", "gpio32"; 2551 function = "qup11"; 2552 }; 2553 }; 2554 2555 qup_i2c12_default: qup-i2c12-default { 2556 pinmux { 2557 pins = "gpio49", "gpio50"; 2558 function = "qup12"; 2559 }; 2560 }; 2561 2562 qup_i2c13_default: qup-i2c13-default { 2563 pinmux { 2564 pins = "gpio105", "gpio106"; 2565 function = "qup13"; 2566 }; 2567 }; 2568 2569 qup_i2c14_default: qup-i2c14-default { 2570 pinmux { 2571 pins = "gpio33", "gpio34"; 2572 function = "qup14"; 2573 }; 2574 }; 2575 2576 qup_i2c15_default: qup-i2c15-default { 2577 pinmux { 2578 pins = "gpio81", "gpio82"; 2579 function = "qup15"; 2580 }; 2581 }; 2582 2583 qup_spi0_default: qup-spi0-default { 2584 pinmux { 2585 pins = "gpio0", "gpio1", 2586 "gpio2", "gpio3"; 2587 function = "qup0"; 2588 }; 2589 }; 2590 2591 qup_spi1_default: qup-spi1-default { 2592 pinmux { 2593 pins = "gpio17", "gpio18", 2594 "gpio19", "gpio20"; 2595 function = "qup1"; 2596 }; 2597 }; 2598 2599 qup_spi2_default: qup-spi2-default { 2600 pinmux { 2601 pins = "gpio27", "gpio28", 2602 "gpio29", "gpio30"; 2603 function = "qup2"; 2604 }; 2605 }; 2606 2607 qup_spi3_default: qup-spi3-default { 2608 pinmux { 2609 pins = "gpio41", "gpio42", 2610 "gpio43", "gpio44"; 2611 function = "qup3"; 2612 }; 2613 }; 2614 2615 qup_spi4_default: qup-spi4-default { 2616 pinmux { 2617 pins = "gpio89", "gpio90", 2618 "gpio91", "gpio92"; 2619 function = "qup4"; 2620 }; 2621 }; 2622 2623 qup_spi5_default: qup-spi5-default { 2624 pinmux { 2625 pins = "gpio85", "gpio86", 2626 "gpio87", "gpio88"; 2627 function = "qup5"; 2628 }; 2629 }; 2630 2631 qup_spi6_default: qup-spi6-default { 2632 pinmux { 2633 pins = "gpio45", "gpio46", 2634 "gpio47", "gpio48"; 2635 function = "qup6"; 2636 }; 2637 }; 2638 2639 qup_spi7_default: qup-spi7-default { 2640 pinmux { 2641 pins = "gpio93", "gpio94", 2642 "gpio95", "gpio96"; 2643 function = "qup7"; 2644 }; 2645 }; 2646 2647 qup_spi8_default: qup-spi8-default { 2648 pinmux { 2649 pins = "gpio65", "gpio66", 2650 "gpio67", "gpio68"; 2651 function = "qup8"; 2652 }; 2653 }; 2654 2655 qup_spi9_default: qup-spi9-default { 2656 pinmux { 2657 pins = "gpio6", "gpio7", 2658 "gpio4", "gpio5"; 2659 function = "qup9"; 2660 }; 2661 }; 2662 2663 qup_spi10_default: qup-spi10-default { 2664 pinmux { 2665 pins = "gpio55", "gpio56", 2666 "gpio53", "gpio54"; 2667 function = "qup10"; 2668 }; 2669 }; 2670 2671 qup_spi11_default: qup-spi11-default { 2672 pinmux { 2673 pins = "gpio31", "gpio32", 2674 "gpio33", "gpio34"; 2675 function = "qup11"; 2676 }; 2677 }; 2678 2679 qup_spi12_default: qup-spi12-default { 2680 pinmux { 2681 pins = "gpio49", "gpio50", 2682 "gpio51", "gpio52"; 2683 function = "qup12"; 2684 }; 2685 }; 2686 2687 qup_spi13_default: qup-spi13-default { 2688 pinmux { 2689 pins = "gpio105", "gpio106", 2690 "gpio107", "gpio108"; 2691 function = "qup13"; 2692 }; 2693 }; 2694 2695 qup_spi14_default: qup-spi14-default { 2696 pinmux { 2697 pins = "gpio33", "gpio34", 2698 "gpio31", "gpio32"; 2699 function = "qup14"; 2700 }; 2701 }; 2702 2703 qup_spi15_default: qup-spi15-default { 2704 pinmux { 2705 pins = "gpio81", "gpio82", 2706 "gpio83", "gpio84"; 2707 function = "qup15"; 2708 }; 2709 }; 2710 2711 qup_uart0_default: qup-uart0-default { 2712 pinmux { 2713 pins = "gpio2", "gpio3"; 2714 function = "qup0"; 2715 }; 2716 }; 2717 2718 qup_uart1_default: qup-uart1-default { 2719 pinmux { 2720 pins = "gpio19", "gpio20"; 2721 function = "qup1"; 2722 }; 2723 }; 2724 2725 qup_uart2_default: qup-uart2-default { 2726 pinmux { 2727 pins = "gpio29", "gpio30"; 2728 function = "qup2"; 2729 }; 2730 }; 2731 2732 qup_uart3_default: qup-uart3-default { 2733 pinmux { 2734 pins = "gpio43", "gpio44"; 2735 function = "qup3"; 2736 }; 2737 }; 2738 2739 qup_uart4_default: qup-uart4-default { 2740 pinmux { 2741 pins = "gpio91", "gpio92"; 2742 function = "qup4"; 2743 }; 2744 }; 2745 2746 qup_uart5_default: qup-uart5-default { 2747 pinmux { 2748 pins = "gpio87", "gpio88"; 2749 function = "qup5"; 2750 }; 2751 }; 2752 2753 qup_uart6_default: qup-uart6-default { 2754 pinmux { 2755 pins = "gpio47", "gpio48"; 2756 function = "qup6"; 2757 }; 2758 }; 2759 2760 qup_uart7_default: qup-uart7-default { 2761 pinmux { 2762 pins = "gpio95", "gpio96"; 2763 function = "qup7"; 2764 }; 2765 }; 2766 2767 qup_uart8_default: qup-uart8-default { 2768 pinmux { 2769 pins = "gpio67", "gpio68"; 2770 function = "qup8"; 2771 }; 2772 }; 2773 2774 qup_uart9_default: qup-uart9-default { 2775 pinmux { 2776 pins = "gpio4", "gpio5"; 2777 function = "qup9"; 2778 }; 2779 }; 2780 2781 qup_uart10_default: qup-uart10-default { 2782 pinmux { 2783 pins = "gpio53", "gpio54"; 2784 function = "qup10"; 2785 }; 2786 }; 2787 2788 qup_uart11_default: qup-uart11-default { 2789 pinmux { 2790 pins = "gpio33", "gpio34"; 2791 function = "qup11"; 2792 }; 2793 }; 2794 2795 qup_uart12_default: qup-uart12-default { 2796 pinmux { 2797 pins = "gpio51", "gpio52"; 2798 function = "qup12"; 2799 }; 2800 }; 2801 2802 qup_uart13_default: qup-uart13-default { 2803 pinmux { 2804 pins = "gpio107", "gpio108"; 2805 function = "qup13"; 2806 }; 2807 }; 2808 2809 qup_uart14_default: qup-uart14-default { 2810 pinmux { 2811 pins = "gpio31", "gpio32"; 2812 function = "qup14"; 2813 }; 2814 }; 2815 2816 qup_uart15_default: qup-uart15-default { 2817 pinmux { 2818 pins = "gpio83", "gpio84"; 2819 function = "qup15"; 2820 }; 2821 }; 2822 2823 quat_mi2s_sleep: quat_mi2s_sleep { 2824 mux { 2825 pins = "gpio58", "gpio59"; 2826 function = "gpio"; 2827 }; 2828 2829 config { 2830 pins = "gpio58", "gpio59"; 2831 drive-strength = <2>; 2832 bias-pull-down; 2833 input-enable; 2834 }; 2835 }; 2836 2837 quat_mi2s_active: quat_mi2s_active { 2838 mux { 2839 pins = "gpio58", "gpio59"; 2840 function = "qua_mi2s"; 2841 }; 2842 2843 config { 2844 pins = "gpio58", "gpio59"; 2845 drive-strength = <8>; 2846 bias-disable; 2847 output-high; 2848 }; 2849 }; 2850 2851 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2852 mux { 2853 pins = "gpio60"; 2854 function = "gpio"; 2855 }; 2856 2857 config { 2858 pins = "gpio60"; 2859 drive-strength = <2>; 2860 bias-pull-down; 2861 input-enable; 2862 }; 2863 }; 2864 2865 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2866 mux { 2867 pins = "gpio60"; 2868 function = "qua_mi2s"; 2869 }; 2870 2871 config { 2872 pins = "gpio60"; 2873 drive-strength = <8>; 2874 bias-disable; 2875 }; 2876 }; 2877 2878 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2879 mux { 2880 pins = "gpio61"; 2881 function = "gpio"; 2882 }; 2883 2884 config { 2885 pins = "gpio61"; 2886 drive-strength = <2>; 2887 bias-pull-down; 2888 input-enable; 2889 }; 2890 }; 2891 2892 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2893 mux { 2894 pins = "gpio61"; 2895 function = "qua_mi2s"; 2896 }; 2897 2898 config { 2899 pins = "gpio61"; 2900 drive-strength = <8>; 2901 bias-disable; 2902 }; 2903 }; 2904 2905 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2906 mux { 2907 pins = "gpio62"; 2908 function = "gpio"; 2909 }; 2910 2911 config { 2912 pins = "gpio62"; 2913 drive-strength = <2>; 2914 bias-pull-down; 2915 input-enable; 2916 }; 2917 }; 2918 2919 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2920 mux { 2921 pins = "gpio62"; 2922 function = "qua_mi2s"; 2923 }; 2924 2925 config { 2926 pins = "gpio62"; 2927 drive-strength = <8>; 2928 bias-disable; 2929 }; 2930 }; 2931 2932 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2933 mux { 2934 pins = "gpio63"; 2935 function = "gpio"; 2936 }; 2937 2938 config { 2939 pins = "gpio63"; 2940 drive-strength = <2>; 2941 bias-pull-down; 2942 input-enable; 2943 }; 2944 }; 2945 2946 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2947 mux { 2948 pins = "gpio63"; 2949 function = "qua_mi2s"; 2950 }; 2951 2952 config { 2953 pins = "gpio63"; 2954 drive-strength = <8>; 2955 bias-disable; 2956 }; 2957 }; 2958 }; 2959 2960 mss_pil: remoteproc@4080000 { 2961 compatible = "qcom,sdm845-mss-pil"; 2962 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2963 reg-names = "qdsp6", "rmb"; 2964 2965 interrupts-extended = 2966 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2967 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2968 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2969 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2970 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2971 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2972 interrupt-names = "wdog", "fatal", "ready", 2973 "handover", "stop-ack", 2974 "shutdown-ack"; 2975 2976 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2977 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2978 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2979 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2980 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2981 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2982 <&gcc GCC_PRNG_AHB_CLK>, 2983 <&rpmhcc RPMH_CXO_CLK>; 2984 clock-names = "iface", "bus", "mem", "gpll0_mss", 2985 "snoc_axi", "mnoc_axi", "prng", "xo"; 2986 2987 qcom,smem-states = <&modem_smp2p_out 0>; 2988 qcom,smem-state-names = "stop"; 2989 2990 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2991 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2992 reset-names = "mss_restart", "pdc_reset"; 2993 2994 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2995 2996 power-domains = <&aoss_qmp 2>, 2997 <&rpmhpd SDM845_CX>, 2998 <&rpmhpd SDM845_MX>, 2999 <&rpmhpd SDM845_MSS>; 3000 power-domain-names = "load_state", "cx", "mx", "mss"; 3001 3002 mba { 3003 memory-region = <&mba_region>; 3004 }; 3005 3006 mpss { 3007 memory-region = <&mpss_region>; 3008 }; 3009 3010 glink-edge { 3011 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3012 label = "modem"; 3013 qcom,remote-pid = <1>; 3014 mboxes = <&apss_shared 12>; 3015 }; 3016 }; 3017 3018 gpucc: clock-controller@5090000 { 3019 compatible = "qcom,sdm845-gpucc"; 3020 reg = <0 0x05090000 0 0x9000>; 3021 #clock-cells = <1>; 3022 #reset-cells = <1>; 3023 #power-domain-cells = <1>; 3024 clocks = <&rpmhcc RPMH_CXO_CLK>, 3025 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3026 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3027 clock-names = "bi_tcxo", 3028 "gcc_gpu_gpll0_clk_src", 3029 "gcc_gpu_gpll0_div_clk_src"; 3030 }; 3031 3032 stm@6002000 { 3033 compatible = "arm,coresight-stm", "arm,primecell"; 3034 reg = <0 0x06002000 0 0x1000>, 3035 <0 0x16280000 0 0x180000>; 3036 reg-names = "stm-base", "stm-stimulus-base"; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 3041 out-ports { 3042 port { 3043 stm_out: endpoint { 3044 remote-endpoint = 3045 <&funnel0_in7>; 3046 }; 3047 }; 3048 }; 3049 }; 3050 3051 funnel@6041000 { 3052 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3053 reg = <0 0x06041000 0 0x1000>; 3054 3055 clocks = <&aoss_qmp>; 3056 clock-names = "apb_pclk"; 3057 3058 out-ports { 3059 port { 3060 funnel0_out: endpoint { 3061 remote-endpoint = 3062 <&merge_funnel_in0>; 3063 }; 3064 }; 3065 }; 3066 3067 in-ports { 3068 #address-cells = <1>; 3069 #size-cells = <0>; 3070 3071 port@7 { 3072 reg = <7>; 3073 funnel0_in7: endpoint { 3074 remote-endpoint = <&stm_out>; 3075 }; 3076 }; 3077 }; 3078 }; 3079 3080 funnel@6043000 { 3081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3082 reg = <0 0x06043000 0 0x1000>; 3083 3084 clocks = <&aoss_qmp>; 3085 clock-names = "apb_pclk"; 3086 3087 out-ports { 3088 port { 3089 funnel2_out: endpoint { 3090 remote-endpoint = 3091 <&merge_funnel_in2>; 3092 }; 3093 }; 3094 }; 3095 3096 in-ports { 3097 #address-cells = <1>; 3098 #size-cells = <0>; 3099 3100 port@5 { 3101 reg = <5>; 3102 funnel2_in5: endpoint { 3103 remote-endpoint = 3104 <&apss_merge_funnel_out>; 3105 }; 3106 }; 3107 }; 3108 }; 3109 3110 funnel@6045000 { 3111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3112 reg = <0 0x06045000 0 0x1000>; 3113 3114 clocks = <&aoss_qmp>; 3115 clock-names = "apb_pclk"; 3116 3117 out-ports { 3118 port { 3119 merge_funnel_out: endpoint { 3120 remote-endpoint = <&etf_in>; 3121 }; 3122 }; 3123 }; 3124 3125 in-ports { 3126 #address-cells = <1>; 3127 #size-cells = <0>; 3128 3129 port@0 { 3130 reg = <0>; 3131 merge_funnel_in0: endpoint { 3132 remote-endpoint = 3133 <&funnel0_out>; 3134 }; 3135 }; 3136 3137 port@2 { 3138 reg = <2>; 3139 merge_funnel_in2: endpoint { 3140 remote-endpoint = 3141 <&funnel2_out>; 3142 }; 3143 }; 3144 }; 3145 }; 3146 3147 replicator@6046000 { 3148 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3149 reg = <0 0x06046000 0 0x1000>; 3150 3151 clocks = <&aoss_qmp>; 3152 clock-names = "apb_pclk"; 3153 3154 out-ports { 3155 port { 3156 replicator_out: endpoint { 3157 remote-endpoint = <&etr_in>; 3158 }; 3159 }; 3160 }; 3161 3162 in-ports { 3163 port { 3164 replicator_in: endpoint { 3165 remote-endpoint = <&etf_out>; 3166 }; 3167 }; 3168 }; 3169 }; 3170 3171 etf@6047000 { 3172 compatible = "arm,coresight-tmc", "arm,primecell"; 3173 reg = <0 0x06047000 0 0x1000>; 3174 3175 clocks = <&aoss_qmp>; 3176 clock-names = "apb_pclk"; 3177 3178 out-ports { 3179 port { 3180 etf_out: endpoint { 3181 remote-endpoint = 3182 <&replicator_in>; 3183 }; 3184 }; 3185 }; 3186 3187 in-ports { 3188 #address-cells = <1>; 3189 #size-cells = <0>; 3190 3191 port@1 { 3192 reg = <1>; 3193 etf_in: endpoint { 3194 remote-endpoint = 3195 <&merge_funnel_out>; 3196 }; 3197 }; 3198 }; 3199 }; 3200 3201 etr@6048000 { 3202 compatible = "arm,coresight-tmc", "arm,primecell"; 3203 reg = <0 0x06048000 0 0x1000>; 3204 3205 clocks = <&aoss_qmp>; 3206 clock-names = "apb_pclk"; 3207 arm,scatter-gather; 3208 3209 in-ports { 3210 port { 3211 etr_in: endpoint { 3212 remote-endpoint = 3213 <&replicator_out>; 3214 }; 3215 }; 3216 }; 3217 }; 3218 3219 etm@7040000 { 3220 compatible = "arm,coresight-etm4x", "arm,primecell"; 3221 reg = <0 0x07040000 0 0x1000>; 3222 3223 cpu = <&CPU0>; 3224 3225 clocks = <&aoss_qmp>; 3226 clock-names = "apb_pclk"; 3227 arm,coresight-loses-context-with-cpu; 3228 3229 out-ports { 3230 port { 3231 etm0_out: endpoint { 3232 remote-endpoint = 3233 <&apss_funnel_in0>; 3234 }; 3235 }; 3236 }; 3237 }; 3238 3239 etm@7140000 { 3240 compatible = "arm,coresight-etm4x", "arm,primecell"; 3241 reg = <0 0x07140000 0 0x1000>; 3242 3243 cpu = <&CPU1>; 3244 3245 clocks = <&aoss_qmp>; 3246 clock-names = "apb_pclk"; 3247 arm,coresight-loses-context-with-cpu; 3248 3249 out-ports { 3250 port { 3251 etm1_out: endpoint { 3252 remote-endpoint = 3253 <&apss_funnel_in1>; 3254 }; 3255 }; 3256 }; 3257 }; 3258 3259 etm@7240000 { 3260 compatible = "arm,coresight-etm4x", "arm,primecell"; 3261 reg = <0 0x07240000 0 0x1000>; 3262 3263 cpu = <&CPU2>; 3264 3265 clocks = <&aoss_qmp>; 3266 clock-names = "apb_pclk"; 3267 arm,coresight-loses-context-with-cpu; 3268 3269 out-ports { 3270 port { 3271 etm2_out: endpoint { 3272 remote-endpoint = 3273 <&apss_funnel_in2>; 3274 }; 3275 }; 3276 }; 3277 }; 3278 3279 etm@7340000 { 3280 compatible = "arm,coresight-etm4x", "arm,primecell"; 3281 reg = <0 0x07340000 0 0x1000>; 3282 3283 cpu = <&CPU3>; 3284 3285 clocks = <&aoss_qmp>; 3286 clock-names = "apb_pclk"; 3287 arm,coresight-loses-context-with-cpu; 3288 3289 out-ports { 3290 port { 3291 etm3_out: endpoint { 3292 remote-endpoint = 3293 <&apss_funnel_in3>; 3294 }; 3295 }; 3296 }; 3297 }; 3298 3299 etm@7440000 { 3300 compatible = "arm,coresight-etm4x", "arm,primecell"; 3301 reg = <0 0x07440000 0 0x1000>; 3302 3303 cpu = <&CPU4>; 3304 3305 clocks = <&aoss_qmp>; 3306 clock-names = "apb_pclk"; 3307 arm,coresight-loses-context-with-cpu; 3308 3309 out-ports { 3310 port { 3311 etm4_out: endpoint { 3312 remote-endpoint = 3313 <&apss_funnel_in4>; 3314 }; 3315 }; 3316 }; 3317 }; 3318 3319 etm@7540000 { 3320 compatible = "arm,coresight-etm4x", "arm,primecell"; 3321 reg = <0 0x07540000 0 0x1000>; 3322 3323 cpu = <&CPU5>; 3324 3325 clocks = <&aoss_qmp>; 3326 clock-names = "apb_pclk"; 3327 arm,coresight-loses-context-with-cpu; 3328 3329 out-ports { 3330 port { 3331 etm5_out: endpoint { 3332 remote-endpoint = 3333 <&apss_funnel_in5>; 3334 }; 3335 }; 3336 }; 3337 }; 3338 3339 etm@7640000 { 3340 compatible = "arm,coresight-etm4x", "arm,primecell"; 3341 reg = <0 0x07640000 0 0x1000>; 3342 3343 cpu = <&CPU6>; 3344 3345 clocks = <&aoss_qmp>; 3346 clock-names = "apb_pclk"; 3347 arm,coresight-loses-context-with-cpu; 3348 3349 out-ports { 3350 port { 3351 etm6_out: endpoint { 3352 remote-endpoint = 3353 <&apss_funnel_in6>; 3354 }; 3355 }; 3356 }; 3357 }; 3358 3359 etm@7740000 { 3360 compatible = "arm,coresight-etm4x", "arm,primecell"; 3361 reg = <0 0x07740000 0 0x1000>; 3362 3363 cpu = <&CPU7>; 3364 3365 clocks = <&aoss_qmp>; 3366 clock-names = "apb_pclk"; 3367 arm,coresight-loses-context-with-cpu; 3368 3369 out-ports { 3370 port { 3371 etm7_out: endpoint { 3372 remote-endpoint = 3373 <&apss_funnel_in7>; 3374 }; 3375 }; 3376 }; 3377 }; 3378 3379 funnel@7800000 { /* APSS Funnel */ 3380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3381 reg = <0 0x07800000 0 0x1000>; 3382 3383 clocks = <&aoss_qmp>; 3384 clock-names = "apb_pclk"; 3385 3386 out-ports { 3387 port { 3388 apss_funnel_out: endpoint { 3389 remote-endpoint = 3390 <&apss_merge_funnel_in>; 3391 }; 3392 }; 3393 }; 3394 3395 in-ports { 3396 #address-cells = <1>; 3397 #size-cells = <0>; 3398 3399 port@0 { 3400 reg = <0>; 3401 apss_funnel_in0: endpoint { 3402 remote-endpoint = 3403 <&etm0_out>; 3404 }; 3405 }; 3406 3407 port@1 { 3408 reg = <1>; 3409 apss_funnel_in1: endpoint { 3410 remote-endpoint = 3411 <&etm1_out>; 3412 }; 3413 }; 3414 3415 port@2 { 3416 reg = <2>; 3417 apss_funnel_in2: endpoint { 3418 remote-endpoint = 3419 <&etm2_out>; 3420 }; 3421 }; 3422 3423 port@3 { 3424 reg = <3>; 3425 apss_funnel_in3: endpoint { 3426 remote-endpoint = 3427 <&etm3_out>; 3428 }; 3429 }; 3430 3431 port@4 { 3432 reg = <4>; 3433 apss_funnel_in4: endpoint { 3434 remote-endpoint = 3435 <&etm4_out>; 3436 }; 3437 }; 3438 3439 port@5 { 3440 reg = <5>; 3441 apss_funnel_in5: endpoint { 3442 remote-endpoint = 3443 <&etm5_out>; 3444 }; 3445 }; 3446 3447 port@6 { 3448 reg = <6>; 3449 apss_funnel_in6: endpoint { 3450 remote-endpoint = 3451 <&etm6_out>; 3452 }; 3453 }; 3454 3455 port@7 { 3456 reg = <7>; 3457 apss_funnel_in7: endpoint { 3458 remote-endpoint = 3459 <&etm7_out>; 3460 }; 3461 }; 3462 }; 3463 }; 3464 3465 funnel@7810000 { 3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3467 reg = <0 0x07810000 0 0x1000>; 3468 3469 clocks = <&aoss_qmp>; 3470 clock-names = "apb_pclk"; 3471 3472 out-ports { 3473 port { 3474 apss_merge_funnel_out: endpoint { 3475 remote-endpoint = 3476 <&funnel2_in5>; 3477 }; 3478 }; 3479 }; 3480 3481 in-ports { 3482 port { 3483 apss_merge_funnel_in: endpoint { 3484 remote-endpoint = 3485 <&apss_funnel_out>; 3486 }; 3487 }; 3488 }; 3489 }; 3490 3491 sdhc_2: sdhci@8804000 { 3492 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3493 reg = <0 0x08804000 0 0x1000>; 3494 3495 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3497 interrupt-names = "hc_irq", "pwr_irq"; 3498 3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3500 <&gcc GCC_SDCC2_APPS_CLK>; 3501 clock-names = "iface", "core"; 3502 iommus = <&apps_smmu 0xa0 0xf>; 3503 power-domains = <&rpmhpd SDM845_CX>; 3504 operating-points-v2 = <&sdhc2_opp_table>; 3505 3506 status = "disabled"; 3507 3508 sdhc2_opp_table: sdhc2-opp-table { 3509 compatible = "operating-points-v2"; 3510 3511 opp-9600000 { 3512 opp-hz = /bits/ 64 <9600000>; 3513 required-opps = <&rpmhpd_opp_min_svs>; 3514 }; 3515 3516 opp-19200000 { 3517 opp-hz = /bits/ 64 <19200000>; 3518 required-opps = <&rpmhpd_opp_low_svs>; 3519 }; 3520 3521 opp-100000000 { 3522 opp-hz = /bits/ 64 <100000000>; 3523 required-opps = <&rpmhpd_opp_svs>; 3524 }; 3525 3526 opp-201500000 { 3527 opp-hz = /bits/ 64 <201500000>; 3528 required-opps = <&rpmhpd_opp_svs_l1>; 3529 }; 3530 }; 3531 }; 3532 3533 qspi_opp_table: qspi-opp-table { 3534 compatible = "operating-points-v2"; 3535 3536 opp-19200000 { 3537 opp-hz = /bits/ 64 <19200000>; 3538 required-opps = <&rpmhpd_opp_min_svs>; 3539 }; 3540 3541 opp-100000000 { 3542 opp-hz = /bits/ 64 <100000000>; 3543 required-opps = <&rpmhpd_opp_low_svs>; 3544 }; 3545 3546 opp-150000000 { 3547 opp-hz = /bits/ 64 <150000000>; 3548 required-opps = <&rpmhpd_opp_svs>; 3549 }; 3550 3551 opp-300000000 { 3552 opp-hz = /bits/ 64 <300000000>; 3553 required-opps = <&rpmhpd_opp_nom>; 3554 }; 3555 }; 3556 3557 qspi: spi@88df000 { 3558 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3559 reg = <0 0x088df000 0 0x600>; 3560 #address-cells = <1>; 3561 #size-cells = <0>; 3562 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3563 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3564 <&gcc GCC_QSPI_CORE_CLK>; 3565 clock-names = "iface", "core"; 3566 power-domains = <&rpmhpd SDM845_CX>; 3567 operating-points-v2 = <&qspi_opp_table>; 3568 status = "disabled"; 3569 }; 3570 3571 slim: slim@171c0000 { 3572 compatible = "qcom,slim-ngd-v2.1.0"; 3573 reg = <0 0x171c0000 0 0x2c000>; 3574 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3575 3576 qcom,apps-ch-pipes = <0x780000>; 3577 qcom,ea-pc = <0x270>; 3578 status = "okay"; 3579 dmas = <&slimbam 3>, <&slimbam 4>, 3580 <&slimbam 5>, <&slimbam 6>; 3581 dma-names = "rx", "tx", "tx2", "rx2"; 3582 3583 iommus = <&apps_smmu 0x1806 0x0>; 3584 #address-cells = <1>; 3585 #size-cells = <0>; 3586 3587 ngd@1 { 3588 reg = <1>; 3589 #address-cells = <2>; 3590 #size-cells = <0>; 3591 3592 wcd9340_ifd: ifd@0{ 3593 compatible = "slim217,250"; 3594 reg = <0 0>; 3595 }; 3596 3597 wcd9340: codec@1{ 3598 compatible = "slim217,250"; 3599 reg = <1 0>; 3600 slim-ifc-dev = <&wcd9340_ifd>; 3601 3602 #sound-dai-cells = <1>; 3603 3604 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3605 interrupt-controller; 3606 #interrupt-cells = <1>; 3607 3608 #clock-cells = <0>; 3609 clock-frequency = <9600000>; 3610 clock-output-names = "mclk"; 3611 qcom,micbias1-millivolt = <1800>; 3612 qcom,micbias2-millivolt = <1800>; 3613 qcom,micbias3-millivolt = <1800>; 3614 qcom,micbias4-millivolt = <1800>; 3615 3616 #address-cells = <1>; 3617 #size-cells = <1>; 3618 3619 wcdgpio: gpio-controller@42 { 3620 compatible = "qcom,wcd9340-gpio"; 3621 gpio-controller; 3622 #gpio-cells = <2>; 3623 reg = <0x42 0x2>; 3624 }; 3625 3626 swm: swm@c85 { 3627 compatible = "qcom,soundwire-v1.3.0"; 3628 reg = <0xc85 0x40>; 3629 interrupts-extended = <&wcd9340 20>; 3630 3631 qcom,dout-ports = <6>; 3632 qcom,din-ports = <2>; 3633 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3635 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3636 3637 #sound-dai-cells = <1>; 3638 clocks = <&wcd9340>; 3639 clock-names = "iface"; 3640 #address-cells = <2>; 3641 #size-cells = <0>; 3642 3643 3644 }; 3645 }; 3646 }; 3647 }; 3648 3649 sound: sound { 3650 }; 3651 3652 usb_1_hsphy: phy@88e2000 { 3653 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3654 reg = <0 0x088e2000 0 0x400>; 3655 status = "disabled"; 3656 #phy-cells = <0>; 3657 3658 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3659 <&rpmhcc RPMH_CXO_CLK>; 3660 clock-names = "cfg_ahb", "ref"; 3661 3662 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3663 3664 nvmem-cells = <&qusb2p_hstx_trim>; 3665 }; 3666 3667 usb_2_hsphy: phy@88e3000 { 3668 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3669 reg = <0 0x088e3000 0 0x400>; 3670 status = "disabled"; 3671 #phy-cells = <0>; 3672 3673 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3674 <&rpmhcc RPMH_CXO_CLK>; 3675 clock-names = "cfg_ahb", "ref"; 3676 3677 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3678 3679 nvmem-cells = <&qusb2s_hstx_trim>; 3680 }; 3681 3682 usb_1_qmpphy: phy@88e9000 { 3683 compatible = "qcom,sdm845-qmp-usb3-phy"; 3684 reg = <0 0x088e9000 0 0x18c>, 3685 <0 0x088e8000 0 0x10>; 3686 reg-names = "reg-base", "dp_com"; 3687 status = "disabled"; 3688 #address-cells = <2>; 3689 #size-cells = <2>; 3690 ranges; 3691 3692 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3693 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3694 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3695 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3696 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3697 3698 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3699 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3700 reset-names = "phy", "common"; 3701 3702 usb_1_ssphy: lanes@88e9200 { 3703 reg = <0 0x088e9200 0 0x128>, 3704 <0 0x088e9400 0 0x200>, 3705 <0 0x088e9c00 0 0x218>, 3706 <0 0x088e9600 0 0x128>, 3707 <0 0x088e9800 0 0x200>, 3708 <0 0x088e9a00 0 0x100>; 3709 #clock-cells = <0>; 3710 #phy-cells = <0>; 3711 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3712 clock-names = "pipe0"; 3713 clock-output-names = "usb3_phy_pipe_clk_src"; 3714 }; 3715 }; 3716 3717 usb_2_qmpphy: phy@88eb000 { 3718 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3719 reg = <0 0x088eb000 0 0x18c>; 3720 status = "disabled"; 3721 #address-cells = <2>; 3722 #size-cells = <2>; 3723 ranges; 3724 3725 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3726 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3727 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3728 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3729 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3730 3731 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3732 <&gcc GCC_USB3_PHY_SEC_BCR>; 3733 reset-names = "phy", "common"; 3734 3735 usb_2_ssphy: lane@88eb200 { 3736 reg = <0 0x088eb200 0 0x128>, 3737 <0 0x088eb400 0 0x1fc>, 3738 <0 0x088eb800 0 0x218>, 3739 <0 0x088eb600 0 0x70>; 3740 #clock-cells = <0>; 3741 #phy-cells = <0>; 3742 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3743 clock-names = "pipe0"; 3744 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3745 }; 3746 }; 3747 3748 usb_1: usb@a6f8800 { 3749 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3750 reg = <0 0x0a6f8800 0 0x400>; 3751 status = "disabled"; 3752 #address-cells = <2>; 3753 #size-cells = <2>; 3754 ranges; 3755 dma-ranges; 3756 3757 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3758 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3759 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3760 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3761 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3762 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3763 "sleep"; 3764 3765 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3766 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3767 assigned-clock-rates = <19200000>, <150000000>; 3768 3769 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3773 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3774 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3775 3776 power-domains = <&gcc USB30_PRIM_GDSC>; 3777 3778 resets = <&gcc GCC_USB30_PRIM_BCR>; 3779 3780 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 3781 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3782 interconnect-names = "usb-ddr", "apps-usb"; 3783 3784 usb_1_dwc3: dwc3@a600000 { 3785 compatible = "snps,dwc3"; 3786 reg = <0 0x0a600000 0 0xcd00>; 3787 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3788 iommus = <&apps_smmu 0x740 0>; 3789 snps,dis_u2_susphy_quirk; 3790 snps,dis_enblslpm_quirk; 3791 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3792 phy-names = "usb2-phy", "usb3-phy"; 3793 }; 3794 }; 3795 3796 usb_2: usb@a8f8800 { 3797 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3798 reg = <0 0x0a8f8800 0 0x400>; 3799 status = "disabled"; 3800 #address-cells = <2>; 3801 #size-cells = <2>; 3802 ranges; 3803 dma-ranges; 3804 3805 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3806 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3807 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3808 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3809 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3810 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3811 "sleep"; 3812 3813 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3814 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3815 assigned-clock-rates = <19200000>, <150000000>; 3816 3817 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3821 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3822 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3823 3824 power-domains = <&gcc USB30_SEC_GDSC>; 3825 3826 resets = <&gcc GCC_USB30_SEC_BCR>; 3827 3828 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 3829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3830 interconnect-names = "usb-ddr", "apps-usb"; 3831 3832 usb_2_dwc3: dwc3@a800000 { 3833 compatible = "snps,dwc3"; 3834 reg = <0 0x0a800000 0 0xcd00>; 3835 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3836 iommus = <&apps_smmu 0x760 0>; 3837 snps,dis_u2_susphy_quirk; 3838 snps,dis_enblslpm_quirk; 3839 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3840 phy-names = "usb2-phy", "usb3-phy"; 3841 }; 3842 }; 3843 3844 venus: video-codec@aa00000 { 3845 compatible = "qcom,sdm845-venus-v2"; 3846 reg = <0 0x0aa00000 0 0xff000>; 3847 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3848 power-domains = <&videocc VENUS_GDSC>, 3849 <&videocc VCODEC0_GDSC>, 3850 <&videocc VCODEC1_GDSC>, 3851 <&rpmhpd SDM845_CX>; 3852 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 3853 operating-points-v2 = <&venus_opp_table>; 3854 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3855 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3856 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3857 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3858 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3859 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3860 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3861 clock-names = "core", "iface", "bus", 3862 "vcodec0_core", "vcodec0_bus", 3863 "vcodec1_core", "vcodec1_bus"; 3864 iommus = <&apps_smmu 0x10a0 0x8>, 3865 <&apps_smmu 0x10b0 0x0>; 3866 memory-region = <&venus_mem>; 3867 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 3868 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3869 interconnect-names = "video-mem", "cpu-cfg"; 3870 3871 video-core0 { 3872 compatible = "venus-decoder"; 3873 }; 3874 3875 video-core1 { 3876 compatible = "venus-encoder"; 3877 }; 3878 3879 venus_opp_table: venus-opp-table { 3880 compatible = "operating-points-v2"; 3881 3882 opp-100000000 { 3883 opp-hz = /bits/ 64 <100000000>; 3884 required-opps = <&rpmhpd_opp_min_svs>; 3885 }; 3886 3887 opp-200000000 { 3888 opp-hz = /bits/ 64 <200000000>; 3889 required-opps = <&rpmhpd_opp_low_svs>; 3890 }; 3891 3892 opp-320000000 { 3893 opp-hz = /bits/ 64 <320000000>; 3894 required-opps = <&rpmhpd_opp_svs>; 3895 }; 3896 3897 opp-380000000 { 3898 opp-hz = /bits/ 64 <380000000>; 3899 required-opps = <&rpmhpd_opp_svs_l1>; 3900 }; 3901 3902 opp-444000000 { 3903 opp-hz = /bits/ 64 <444000000>; 3904 required-opps = <&rpmhpd_opp_nom>; 3905 }; 3906 3907 opp-533000097 { 3908 opp-hz = /bits/ 64 <533000097>; 3909 required-opps = <&rpmhpd_opp_turbo>; 3910 }; 3911 }; 3912 }; 3913 3914 videocc: clock-controller@ab00000 { 3915 compatible = "qcom,sdm845-videocc"; 3916 reg = <0 0x0ab00000 0 0x10000>; 3917 clocks = <&rpmhcc RPMH_CXO_CLK>; 3918 clock-names = "bi_tcxo"; 3919 #clock-cells = <1>; 3920 #power-domain-cells = <1>; 3921 #reset-cells = <1>; 3922 }; 3923 3924 camss: camss@a00000 { 3925 compatible = "qcom,sdm845-camss"; 3926 3927 reg = <0 0xacb3000 0 0x1000>, 3928 <0 0xacba000 0 0x1000>, 3929 <0 0xacc8000 0 0x1000>, 3930 <0 0xac65000 0 0x1000>, 3931 <0 0xac66000 0 0x1000>, 3932 <0 0xac67000 0 0x1000>, 3933 <0 0xac68000 0 0x1000>, 3934 <0 0xacaf000 0 0x4000>, 3935 <0 0xacb6000 0 0x4000>, 3936 <0 0xacc4000 0 0x4000>; 3937 reg-names = "csid0", 3938 "csid1", 3939 "csid2", 3940 "csiphy0", 3941 "csiphy1", 3942 "csiphy2", 3943 "csiphy3", 3944 "vfe0", 3945 "vfe1", 3946 "vfe_lite"; 3947 3948 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 3958 interrupt-names = "csid0", 3959 "csid1", 3960 "csid2", 3961 "csiphy0", 3962 "csiphy1", 3963 "csiphy2", 3964 "csiphy3", 3965 "vfe0", 3966 "vfe1", 3967 "vfe_lite"; 3968 3969 power-domains = <&clock_camcc IFE_0_GDSC>, 3970 <&clock_camcc IFE_1_GDSC>, 3971 <&clock_camcc TITAN_TOP_GDSC>; 3972 3973 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3974 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3975 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 3976 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 3977 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 3978 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 3979 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 3980 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 3981 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 3982 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 3983 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 3984 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 3985 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 3986 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 3987 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 3988 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 3989 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 3990 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 3991 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 3992 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 3993 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 3994 <&gcc GCC_CAMERA_AHB_CLK>, 3995 <&gcc GCC_CAMERA_AXI_CLK>, 3996 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3997 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 3998 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 3999 <&clock_camcc CAM_CC_IFE_0_CLK>, 4000 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4001 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4002 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4003 <&clock_camcc CAM_CC_IFE_1_CLK>, 4004 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4005 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4006 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4007 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4008 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4009 clock-names = "camnoc_axi", 4010 "cpas_ahb", 4011 "cphy_rx_src", 4012 "csi0", 4013 "csi0_src", 4014 "csi1", 4015 "csi1_src", 4016 "csi2", 4017 "csi2_src", 4018 "csiphy0", 4019 "csiphy0_timer", 4020 "csiphy0_timer_src", 4021 "csiphy1", 4022 "csiphy1_timer", 4023 "csiphy1_timer_src", 4024 "csiphy2", 4025 "csiphy2_timer", 4026 "csiphy2_timer_src", 4027 "csiphy3", 4028 "csiphy3_timer", 4029 "csiphy3_timer_src", 4030 "gcc_camera_ahb", 4031 "gcc_camera_axi", 4032 "slow_ahb_src", 4033 "soc_ahb", 4034 "vfe0_axi", 4035 "vfe0", 4036 "vfe0_cphy_rx", 4037 "vfe0_src", 4038 "vfe1_axi", 4039 "vfe1", 4040 "vfe1_cphy_rx", 4041 "vfe1_src", 4042 "vfe_lite", 4043 "vfe_lite_cphy_rx", 4044 "vfe_lite_src"; 4045 4046 iommus = <&apps_smmu 0x0808 0x0>, 4047 <&apps_smmu 0x0810 0x8>, 4048 <&apps_smmu 0x0c08 0x0>, 4049 <&apps_smmu 0x0c10 0x8>; 4050 4051 status = "disabled"; 4052 4053 ports { 4054 #address-cells = <1>; 4055 #size-cells = <0>; 4056 }; 4057 }; 4058 4059 cci: cci@ac4a000 { 4060 compatible = "qcom,sdm845-cci"; 4061 #address-cells = <1>; 4062 #size-cells = <0>; 4063 4064 reg = <0 0x0ac4a000 0 0x4000>; 4065 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4066 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4067 4068 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4069 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4070 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4071 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4072 <&clock_camcc CAM_CC_CCI_CLK>, 4073 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4074 clock-names = "camnoc_axi", 4075 "soc_ahb", 4076 "slow_ahb_src", 4077 "cpas_ahb", 4078 "cci", 4079 "cci_src"; 4080 4081 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4082 <&clock_camcc CAM_CC_CCI_CLK>; 4083 assigned-clock-rates = <80000000>, <37500000>; 4084 4085 pinctrl-names = "default", "sleep"; 4086 pinctrl-0 = <&cci0_default &cci1_default>; 4087 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4088 4089 status = "disabled"; 4090 4091 cci_i2c0: i2c-bus@0 { 4092 reg = <0>; 4093 clock-frequency = <1000000>; 4094 #address-cells = <1>; 4095 #size-cells = <0>; 4096 }; 4097 4098 cci_i2c1: i2c-bus@1 { 4099 reg = <1>; 4100 clock-frequency = <1000000>; 4101 #address-cells = <1>; 4102 #size-cells = <0>; 4103 }; 4104 }; 4105 4106 clock_camcc: clock-controller@ad00000 { 4107 compatible = "qcom,sdm845-camcc"; 4108 reg = <0 0x0ad00000 0 0x10000>; 4109 #clock-cells = <1>; 4110 #reset-cells = <1>; 4111 #power-domain-cells = <1>; 4112 }; 4113 4114 dsi_opp_table: dsi-opp-table { 4115 compatible = "operating-points-v2"; 4116 4117 opp-19200000 { 4118 opp-hz = /bits/ 64 <19200000>; 4119 required-opps = <&rpmhpd_opp_min_svs>; 4120 }; 4121 4122 opp-180000000 { 4123 opp-hz = /bits/ 64 <180000000>; 4124 required-opps = <&rpmhpd_opp_low_svs>; 4125 }; 4126 4127 opp-275000000 { 4128 opp-hz = /bits/ 64 <275000000>; 4129 required-opps = <&rpmhpd_opp_svs>; 4130 }; 4131 4132 opp-328580000 { 4133 opp-hz = /bits/ 64 <328580000>; 4134 required-opps = <&rpmhpd_opp_svs_l1>; 4135 }; 4136 4137 opp-358000000 { 4138 opp-hz = /bits/ 64 <358000000>; 4139 required-opps = <&rpmhpd_opp_nom>; 4140 }; 4141 }; 4142 4143 mdss: mdss@ae00000 { 4144 compatible = "qcom,sdm845-mdss"; 4145 reg = <0 0x0ae00000 0 0x1000>; 4146 reg-names = "mdss"; 4147 4148 power-domains = <&dispcc MDSS_GDSC>; 4149 4150 clocks = <&gcc GCC_DISP_AHB_CLK>, 4151 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4152 clock-names = "iface", "core"; 4153 4154 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 4155 assigned-clock-rates = <300000000>; 4156 4157 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4158 interrupt-controller; 4159 #interrupt-cells = <1>; 4160 4161 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4162 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4163 interconnect-names = "mdp0-mem", "mdp1-mem"; 4164 4165 iommus = <&apps_smmu 0x880 0x8>, 4166 <&apps_smmu 0xc80 0x8>; 4167 4168 status = "disabled"; 4169 4170 #address-cells = <2>; 4171 #size-cells = <2>; 4172 ranges; 4173 4174 mdss_mdp: mdp@ae01000 { 4175 compatible = "qcom,sdm845-dpu"; 4176 reg = <0 0x0ae01000 0 0x8f000>, 4177 <0 0x0aeb0000 0 0x2008>; 4178 reg-names = "mdp", "vbif"; 4179 4180 clocks = <&gcc GCC_DISP_AXI_CLK>, 4181 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4182 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4183 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4184 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4185 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4186 4187 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 4188 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4189 assigned-clock-rates = <300000000>, 4190 <19200000>; 4191 operating-points-v2 = <&mdp_opp_table>; 4192 power-domains = <&rpmhpd SDM845_CX>; 4193 4194 interrupt-parent = <&mdss>; 4195 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 4196 4197 status = "disabled"; 4198 4199 ports { 4200 #address-cells = <1>; 4201 #size-cells = <0>; 4202 4203 port@0 { 4204 reg = <0>; 4205 dpu_intf1_out: endpoint { 4206 remote-endpoint = <&dsi0_in>; 4207 }; 4208 }; 4209 4210 port@1 { 4211 reg = <1>; 4212 dpu_intf2_out: endpoint { 4213 remote-endpoint = <&dsi1_in>; 4214 }; 4215 }; 4216 }; 4217 4218 mdp_opp_table: mdp-opp-table { 4219 compatible = "operating-points-v2"; 4220 4221 opp-19200000 { 4222 opp-hz = /bits/ 64 <19200000>; 4223 required-opps = <&rpmhpd_opp_min_svs>; 4224 }; 4225 4226 opp-171428571 { 4227 opp-hz = /bits/ 64 <171428571>; 4228 required-opps = <&rpmhpd_opp_low_svs>; 4229 }; 4230 4231 opp-344000000 { 4232 opp-hz = /bits/ 64 <344000000>; 4233 required-opps = <&rpmhpd_opp_svs_l1>; 4234 }; 4235 4236 opp-430000000 { 4237 opp-hz = /bits/ 64 <430000000>; 4238 required-opps = <&rpmhpd_opp_nom>; 4239 }; 4240 }; 4241 }; 4242 4243 dsi0: dsi@ae94000 { 4244 compatible = "qcom,mdss-dsi-ctrl"; 4245 reg = <0 0x0ae94000 0 0x400>; 4246 reg-names = "dsi_ctrl"; 4247 4248 interrupt-parent = <&mdss>; 4249 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 4250 4251 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4252 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4253 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4254 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4255 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4256 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4257 clock-names = "byte", 4258 "byte_intf", 4259 "pixel", 4260 "core", 4261 "iface", 4262 "bus"; 4263 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4264 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4265 4266 operating-points-v2 = <&dsi_opp_table>; 4267 power-domains = <&rpmhpd SDM845_CX>; 4268 4269 phys = <&dsi0_phy>; 4270 phy-names = "dsi"; 4271 4272 status = "disabled"; 4273 4274 ports { 4275 #address-cells = <1>; 4276 #size-cells = <0>; 4277 4278 port@0 { 4279 reg = <0>; 4280 dsi0_in: endpoint { 4281 remote-endpoint = <&dpu_intf1_out>; 4282 }; 4283 }; 4284 4285 port@1 { 4286 reg = <1>; 4287 dsi0_out: endpoint { 4288 }; 4289 }; 4290 }; 4291 }; 4292 4293 dsi0_phy: dsi-phy@ae94400 { 4294 compatible = "qcom,dsi-phy-10nm"; 4295 reg = <0 0x0ae94400 0 0x200>, 4296 <0 0x0ae94600 0 0x280>, 4297 <0 0x0ae94a00 0 0x1e0>; 4298 reg-names = "dsi_phy", 4299 "dsi_phy_lane", 4300 "dsi_pll"; 4301 4302 #clock-cells = <1>; 4303 #phy-cells = <0>; 4304 4305 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4306 <&rpmhcc RPMH_CXO_CLK>; 4307 clock-names = "iface", "ref"; 4308 4309 status = "disabled"; 4310 }; 4311 4312 dsi1: dsi@ae96000 { 4313 compatible = "qcom,mdss-dsi-ctrl"; 4314 reg = <0 0x0ae96000 0 0x400>; 4315 reg-names = "dsi_ctrl"; 4316 4317 interrupt-parent = <&mdss>; 4318 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 4319 4320 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4321 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4322 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4323 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4324 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4325 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4326 clock-names = "byte", 4327 "byte_intf", 4328 "pixel", 4329 "core", 4330 "iface", 4331 "bus"; 4332 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4333 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4334 4335 operating-points-v2 = <&dsi_opp_table>; 4336 power-domains = <&rpmhpd SDM845_CX>; 4337 4338 phys = <&dsi1_phy>; 4339 phy-names = "dsi"; 4340 4341 status = "disabled"; 4342 4343 ports { 4344 #address-cells = <1>; 4345 #size-cells = <0>; 4346 4347 port@0 { 4348 reg = <0>; 4349 dsi1_in: endpoint { 4350 remote-endpoint = <&dpu_intf2_out>; 4351 }; 4352 }; 4353 4354 port@1 { 4355 reg = <1>; 4356 dsi1_out: endpoint { 4357 }; 4358 }; 4359 }; 4360 }; 4361 4362 dsi1_phy: dsi-phy@ae96400 { 4363 compatible = "qcom,dsi-phy-10nm"; 4364 reg = <0 0x0ae96400 0 0x200>, 4365 <0 0x0ae96600 0 0x280>, 4366 <0 0x0ae96a00 0 0x10e>; 4367 reg-names = "dsi_phy", 4368 "dsi_phy_lane", 4369 "dsi_pll"; 4370 4371 #clock-cells = <1>; 4372 #phy-cells = <0>; 4373 4374 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4375 <&rpmhcc RPMH_CXO_CLK>; 4376 clock-names = "iface", "ref"; 4377 4378 status = "disabled"; 4379 }; 4380 }; 4381 4382 gpu: gpu@5000000 { 4383 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4384 #stream-id-cells = <16>; 4385 4386 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4387 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4388 4389 /* 4390 * Look ma, no clocks! The GPU clocks and power are 4391 * controlled entirely by the GMU 4392 */ 4393 4394 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4395 4396 iommus = <&adreno_smmu 0>; 4397 4398 operating-points-v2 = <&gpu_opp_table>; 4399 4400 qcom,gmu = <&gmu>; 4401 4402 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4403 interconnect-names = "gfx-mem"; 4404 4405 gpu_opp_table: opp-table { 4406 compatible = "operating-points-v2"; 4407 4408 opp-710000000 { 4409 opp-hz = /bits/ 64 <710000000>; 4410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4411 opp-peak-kBps = <7216000>; 4412 }; 4413 4414 opp-675000000 { 4415 opp-hz = /bits/ 64 <675000000>; 4416 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4417 opp-peak-kBps = <7216000>; 4418 }; 4419 4420 opp-596000000 { 4421 opp-hz = /bits/ 64 <596000000>; 4422 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4423 opp-peak-kBps = <6220000>; 4424 }; 4425 4426 opp-520000000 { 4427 opp-hz = /bits/ 64 <520000000>; 4428 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4429 opp-peak-kBps = <6220000>; 4430 }; 4431 4432 opp-414000000 { 4433 opp-hz = /bits/ 64 <414000000>; 4434 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4435 opp-peak-kBps = <4068000>; 4436 }; 4437 4438 opp-342000000 { 4439 opp-hz = /bits/ 64 <342000000>; 4440 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4441 opp-peak-kBps = <2724000>; 4442 }; 4443 4444 opp-257000000 { 4445 opp-hz = /bits/ 64 <257000000>; 4446 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4447 opp-peak-kBps = <1648000>; 4448 }; 4449 }; 4450 }; 4451 4452 adreno_smmu: iommu@5040000 { 4453 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4454 reg = <0 0x5040000 0 0x10000>; 4455 #iommu-cells = <1>; 4456 #global-interrupts = <2>; 4457 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4458 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4460 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4461 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4462 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4463 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4464 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4465 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4466 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4467 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4468 <&gcc GCC_GPU_CFG_AHB_CLK>; 4469 clock-names = "bus", "iface"; 4470 4471 power-domains = <&gpucc GPU_CX_GDSC>; 4472 }; 4473 4474 gmu: gmu@506a000 { 4475 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4476 4477 reg = <0 0x506a000 0 0x30000>, 4478 <0 0xb280000 0 0x10000>, 4479 <0 0xb480000 0 0x10000>; 4480 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4481 4482 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4483 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4484 interrupt-names = "hfi", "gmu"; 4485 4486 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4487 <&gpucc GPU_CC_CXO_CLK>, 4488 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4489 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4490 clock-names = "gmu", "cxo", "axi", "memnoc"; 4491 4492 power-domains = <&gpucc GPU_CX_GDSC>, 4493 <&gpucc GPU_GX_GDSC>; 4494 power-domain-names = "cx", "gx"; 4495 4496 iommus = <&adreno_smmu 5>; 4497 4498 operating-points-v2 = <&gmu_opp_table>; 4499 4500 gmu_opp_table: opp-table { 4501 compatible = "operating-points-v2"; 4502 4503 opp-400000000 { 4504 opp-hz = /bits/ 64 <400000000>; 4505 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4506 }; 4507 4508 opp-200000000 { 4509 opp-hz = /bits/ 64 <200000000>; 4510 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4511 }; 4512 }; 4513 }; 4514 4515 dispcc: clock-controller@af00000 { 4516 compatible = "qcom,sdm845-dispcc"; 4517 reg = <0 0x0af00000 0 0x10000>; 4518 clocks = <&rpmhcc RPMH_CXO_CLK>, 4519 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4520 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4521 <&dsi0_phy 0>, 4522 <&dsi0_phy 1>, 4523 <&dsi1_phy 0>, 4524 <&dsi1_phy 1>, 4525 <0>, 4526 <0>; 4527 clock-names = "bi_tcxo", 4528 "gcc_disp_gpll0_clk_src", 4529 "gcc_disp_gpll0_div_clk_src", 4530 "dsi0_phy_pll_out_byteclk", 4531 "dsi0_phy_pll_out_dsiclk", 4532 "dsi1_phy_pll_out_byteclk", 4533 "dsi1_phy_pll_out_dsiclk", 4534 "dp_link_clk_divsel_ten", 4535 "dp_vco_divided_clk_src_mux"; 4536 #clock-cells = <1>; 4537 #reset-cells = <1>; 4538 #power-domain-cells = <1>; 4539 }; 4540 4541 pdc_intc: interrupt-controller@b220000 { 4542 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4543 reg = <0 0x0b220000 0 0x30000>; 4544 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4545 #interrupt-cells = <2>; 4546 interrupt-parent = <&intc>; 4547 interrupt-controller; 4548 }; 4549 4550 pdc_reset: reset-controller@b2e0000 { 4551 compatible = "qcom,sdm845-pdc-global"; 4552 reg = <0 0x0b2e0000 0 0x20000>; 4553 #reset-cells = <1>; 4554 }; 4555 4556 tsens0: thermal-sensor@c263000 { 4557 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4558 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4559 <0 0x0c222000 0 0x1ff>; /* SROT */ 4560 #qcom,sensors = <13>; 4561 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4562 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4563 interrupt-names = "uplow", "critical"; 4564 #thermal-sensor-cells = <1>; 4565 }; 4566 4567 tsens1: thermal-sensor@c265000 { 4568 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4569 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4570 <0 0x0c223000 0 0x1ff>; /* SROT */ 4571 #qcom,sensors = <8>; 4572 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4573 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4574 interrupt-names = "uplow", "critical"; 4575 #thermal-sensor-cells = <1>; 4576 }; 4577 4578 aoss_reset: reset-controller@c2a0000 { 4579 compatible = "qcom,sdm845-aoss-cc"; 4580 reg = <0 0x0c2a0000 0 0x31000>; 4581 #reset-cells = <1>; 4582 }; 4583 4584 aoss_qmp: power-controller@c300000 { 4585 compatible = "qcom,sdm845-aoss-qmp"; 4586 reg = <0 0x0c300000 0 0x100000>; 4587 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4588 mboxes = <&apss_shared 0>; 4589 4590 #clock-cells = <0>; 4591 #power-domain-cells = <1>; 4592 4593 cx_cdev: cx { 4594 #cooling-cells = <2>; 4595 }; 4596 4597 ebi_cdev: ebi { 4598 #cooling-cells = <2>; 4599 }; 4600 }; 4601 4602 spmi_bus: spmi@c440000 { 4603 compatible = "qcom,spmi-pmic-arb"; 4604 reg = <0 0x0c440000 0 0x1100>, 4605 <0 0x0c600000 0 0x2000000>, 4606 <0 0x0e600000 0 0x100000>, 4607 <0 0x0e700000 0 0xa0000>, 4608 <0 0x0c40a000 0 0x26000>; 4609 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4610 interrupt-names = "periph_irq"; 4611 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4612 qcom,ee = <0>; 4613 qcom,channel = <0>; 4614 #address-cells = <2>; 4615 #size-cells = <0>; 4616 interrupt-controller; 4617 #interrupt-cells = <4>; 4618 cell-index = <0>; 4619 }; 4620 4621 imem@146bf000 { 4622 compatible = "simple-mfd"; 4623 reg = <0 0x146bf000 0 0x1000>; 4624 4625 #address-cells = <1>; 4626 #size-cells = <1>; 4627 4628 ranges = <0 0 0x146bf000 0x1000>; 4629 4630 pil-reloc@94c { 4631 compatible = "qcom,pil-reloc-info"; 4632 reg = <0x94c 0xc8>; 4633 }; 4634 }; 4635 4636 apps_smmu: iommu@15000000 { 4637 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4638 reg = <0 0x15000000 0 0x80000>; 4639 #iommu-cells = <2>; 4640 #global-interrupts = <1>; 4641 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4642 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4643 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4644 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4645 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4646 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4647 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4648 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4649 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4650 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4651 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4652 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4653 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4654 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4655 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4656 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4657 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4658 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4659 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4660 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4661 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4663 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4664 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4665 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4666 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4667 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4668 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4669 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4670 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4672 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4673 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4674 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4675 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4685 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4690 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4691 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4692 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4694 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4695 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4696 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4699 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4700 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4704 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4705 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4706 }; 4707 4708 lpasscc: clock-controller@17014000 { 4709 compatible = "qcom,sdm845-lpasscc"; 4710 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 4711 reg-names = "cc", "qdsp6ss"; 4712 #clock-cells = <1>; 4713 status = "disabled"; 4714 }; 4715 4716 gladiator_noc: interconnect@17900000 { 4717 compatible = "qcom,sdm845-gladiator-noc"; 4718 reg = <0 0x17900000 0 0xd080>; 4719 #interconnect-cells = <2>; 4720 qcom,bcm-voters = <&apps_bcm_voter>; 4721 }; 4722 4723 watchdog@17980000 { 4724 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 4725 reg = <0 0x17980000 0 0x1000>; 4726 clocks = <&sleep_clk>; 4727 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4728 }; 4729 4730 apss_shared: mailbox@17990000 { 4731 compatible = "qcom,sdm845-apss-shared"; 4732 reg = <0 0x17990000 0 0x1000>; 4733 #mbox-cells = <1>; 4734 }; 4735 4736 apps_rsc: rsc@179c0000 { 4737 label = "apps_rsc"; 4738 compatible = "qcom,rpmh-rsc"; 4739 reg = <0 0x179c0000 0 0x10000>, 4740 <0 0x179d0000 0 0x10000>, 4741 <0 0x179e0000 0 0x10000>; 4742 reg-names = "drv-0", "drv-1", "drv-2"; 4743 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4744 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4745 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4746 qcom,tcs-offset = <0xd00>; 4747 qcom,drv-id = <2>; 4748 qcom,tcs-config = <ACTIVE_TCS 2>, 4749 <SLEEP_TCS 3>, 4750 <WAKE_TCS 3>, 4751 <CONTROL_TCS 1>; 4752 4753 apps_bcm_voter: bcm-voter { 4754 compatible = "qcom,bcm-voter"; 4755 }; 4756 4757 rpmhcc: clock-controller { 4758 compatible = "qcom,sdm845-rpmh-clk"; 4759 #clock-cells = <1>; 4760 clock-names = "xo"; 4761 clocks = <&xo_board>; 4762 }; 4763 4764 rpmhpd: power-controller { 4765 compatible = "qcom,sdm845-rpmhpd"; 4766 #power-domain-cells = <1>; 4767 operating-points-v2 = <&rpmhpd_opp_table>; 4768 4769 rpmhpd_opp_table: opp-table { 4770 compatible = "operating-points-v2"; 4771 4772 rpmhpd_opp_ret: opp1 { 4773 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4774 }; 4775 4776 rpmhpd_opp_min_svs: opp2 { 4777 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4778 }; 4779 4780 rpmhpd_opp_low_svs: opp3 { 4781 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4782 }; 4783 4784 rpmhpd_opp_svs: opp4 { 4785 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4786 }; 4787 4788 rpmhpd_opp_svs_l1: opp5 { 4789 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4790 }; 4791 4792 rpmhpd_opp_nom: opp6 { 4793 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4794 }; 4795 4796 rpmhpd_opp_nom_l1: opp7 { 4797 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4798 }; 4799 4800 rpmhpd_opp_nom_l2: opp8 { 4801 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4802 }; 4803 4804 rpmhpd_opp_turbo: opp9 { 4805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4806 }; 4807 4808 rpmhpd_opp_turbo_l1: opp10 { 4809 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4810 }; 4811 }; 4812 }; 4813 }; 4814 4815 intc: interrupt-controller@17a00000 { 4816 compatible = "arm,gic-v3"; 4817 #address-cells = <2>; 4818 #size-cells = <2>; 4819 ranges; 4820 #interrupt-cells = <3>; 4821 interrupt-controller; 4822 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4823 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4824 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4825 4826 msi-controller@17a40000 { 4827 compatible = "arm,gic-v3-its"; 4828 msi-controller; 4829 #msi-cells = <1>; 4830 reg = <0 0x17a40000 0 0x20000>; 4831 status = "disabled"; 4832 }; 4833 }; 4834 4835 slimbam: dma-controller@17184000 { 4836 compatible = "qcom,bam-v1.7.0"; 4837 qcom,controlled-remotely; 4838 reg = <0 0x17184000 0 0x2a000>; 4839 num-channels = <31>; 4840 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 4841 #dma-cells = <1>; 4842 qcom,ee = <1>; 4843 qcom,num-ees = <2>; 4844 iommus = <&apps_smmu 0x1806 0x0>; 4845 }; 4846 4847 timer@17c90000 { 4848 #address-cells = <2>; 4849 #size-cells = <2>; 4850 ranges; 4851 compatible = "arm,armv7-timer-mem"; 4852 reg = <0 0x17c90000 0 0x1000>; 4853 4854 frame@17ca0000 { 4855 frame-number = <0>; 4856 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4857 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4858 reg = <0 0x17ca0000 0 0x1000>, 4859 <0 0x17cb0000 0 0x1000>; 4860 }; 4861 4862 frame@17cc0000 { 4863 frame-number = <1>; 4864 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 4865 reg = <0 0x17cc0000 0 0x1000>; 4866 status = "disabled"; 4867 }; 4868 4869 frame@17cd0000 { 4870 frame-number = <2>; 4871 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4872 reg = <0 0x17cd0000 0 0x1000>; 4873 status = "disabled"; 4874 }; 4875 4876 frame@17ce0000 { 4877 frame-number = <3>; 4878 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4879 reg = <0 0x17ce0000 0 0x1000>; 4880 status = "disabled"; 4881 }; 4882 4883 frame@17cf0000 { 4884 frame-number = <4>; 4885 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4886 reg = <0 0x17cf0000 0 0x1000>; 4887 status = "disabled"; 4888 }; 4889 4890 frame@17d00000 { 4891 frame-number = <5>; 4892 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4893 reg = <0 0x17d00000 0 0x1000>; 4894 status = "disabled"; 4895 }; 4896 4897 frame@17d10000 { 4898 frame-number = <6>; 4899 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4900 reg = <0 0x17d10000 0 0x1000>; 4901 status = "disabled"; 4902 }; 4903 }; 4904 4905 osm_l3: interconnect@17d41000 { 4906 compatible = "qcom,sdm845-osm-l3"; 4907 reg = <0 0x17d41000 0 0x1400>; 4908 4909 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4910 clock-names = "xo", "alternate"; 4911 4912 #interconnect-cells = <1>; 4913 }; 4914 4915 cpufreq_hw: cpufreq@17d43000 { 4916 compatible = "qcom,cpufreq-hw"; 4917 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4918 reg-names = "freq-domain0", "freq-domain1"; 4919 4920 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4921 clock-names = "xo", "alternate"; 4922 4923 #freq-domain-cells = <1>; 4924 }; 4925 4926 wifi: wifi@18800000 { 4927 compatible = "qcom,wcn3990-wifi"; 4928 status = "disabled"; 4929 reg = <0 0x18800000 0 0x800000>; 4930 reg-names = "membase"; 4931 memory-region = <&wlan_msa_mem>; 4932 clock-names = "cxo_ref_clk_pin"; 4933 clocks = <&rpmhcc RPMH_RF_CLK2>; 4934 interrupts = 4935 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4936 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4944 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4945 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4947 iommus = <&apps_smmu 0x0040 0x1>; 4948 }; 4949 }; 4950 4951 thermal-zones { 4952 cpu0-thermal { 4953 polling-delay-passive = <250>; 4954 polling-delay = <1000>; 4955 4956 thermal-sensors = <&tsens0 1>; 4957 4958 trips { 4959 cpu0_alert0: trip-point0 { 4960 temperature = <90000>; 4961 hysteresis = <2000>; 4962 type = "passive"; 4963 }; 4964 4965 cpu0_alert1: trip-point1 { 4966 temperature = <95000>; 4967 hysteresis = <2000>; 4968 type = "passive"; 4969 }; 4970 4971 cpu0_crit: cpu_crit { 4972 temperature = <110000>; 4973 hysteresis = <1000>; 4974 type = "critical"; 4975 }; 4976 }; 4977 4978 cooling-maps { 4979 map0 { 4980 trip = <&cpu0_alert0>; 4981 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4982 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4983 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4984 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4985 }; 4986 map1 { 4987 trip = <&cpu0_alert1>; 4988 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4989 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4990 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4992 }; 4993 }; 4994 }; 4995 4996 cpu1-thermal { 4997 polling-delay-passive = <250>; 4998 polling-delay = <1000>; 4999 5000 thermal-sensors = <&tsens0 2>; 5001 5002 trips { 5003 cpu1_alert0: trip-point0 { 5004 temperature = <90000>; 5005 hysteresis = <2000>; 5006 type = "passive"; 5007 }; 5008 5009 cpu1_alert1: trip-point1 { 5010 temperature = <95000>; 5011 hysteresis = <2000>; 5012 type = "passive"; 5013 }; 5014 5015 cpu1_crit: cpu_crit { 5016 temperature = <110000>; 5017 hysteresis = <1000>; 5018 type = "critical"; 5019 }; 5020 }; 5021 5022 cooling-maps { 5023 map0 { 5024 trip = <&cpu1_alert0>; 5025 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5026 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5027 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5028 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5029 }; 5030 map1 { 5031 trip = <&cpu1_alert1>; 5032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5033 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5034 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5036 }; 5037 }; 5038 }; 5039 5040 cpu2-thermal { 5041 polling-delay-passive = <250>; 5042 polling-delay = <1000>; 5043 5044 thermal-sensors = <&tsens0 3>; 5045 5046 trips { 5047 cpu2_alert0: trip-point0 { 5048 temperature = <90000>; 5049 hysteresis = <2000>; 5050 type = "passive"; 5051 }; 5052 5053 cpu2_alert1: trip-point1 { 5054 temperature = <95000>; 5055 hysteresis = <2000>; 5056 type = "passive"; 5057 }; 5058 5059 cpu2_crit: cpu_crit { 5060 temperature = <110000>; 5061 hysteresis = <1000>; 5062 type = "critical"; 5063 }; 5064 }; 5065 5066 cooling-maps { 5067 map0 { 5068 trip = <&cpu2_alert0>; 5069 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5070 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5071 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5073 }; 5074 map1 { 5075 trip = <&cpu2_alert1>; 5076 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5077 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5078 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5080 }; 5081 }; 5082 }; 5083 5084 cpu3-thermal { 5085 polling-delay-passive = <250>; 5086 polling-delay = <1000>; 5087 5088 thermal-sensors = <&tsens0 4>; 5089 5090 trips { 5091 cpu3_alert0: trip-point0 { 5092 temperature = <90000>; 5093 hysteresis = <2000>; 5094 type = "passive"; 5095 }; 5096 5097 cpu3_alert1: trip-point1 { 5098 temperature = <95000>; 5099 hysteresis = <2000>; 5100 type = "passive"; 5101 }; 5102 5103 cpu3_crit: cpu_crit { 5104 temperature = <110000>; 5105 hysteresis = <1000>; 5106 type = "critical"; 5107 }; 5108 }; 5109 5110 cooling-maps { 5111 map0 { 5112 trip = <&cpu3_alert0>; 5113 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5114 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5115 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5116 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5117 }; 5118 map1 { 5119 trip = <&cpu3_alert1>; 5120 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5121 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5122 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5123 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5124 }; 5125 }; 5126 }; 5127 5128 cpu4-thermal { 5129 polling-delay-passive = <250>; 5130 polling-delay = <1000>; 5131 5132 thermal-sensors = <&tsens0 7>; 5133 5134 trips { 5135 cpu4_alert0: trip-point0 { 5136 temperature = <90000>; 5137 hysteresis = <2000>; 5138 type = "passive"; 5139 }; 5140 5141 cpu4_alert1: trip-point1 { 5142 temperature = <95000>; 5143 hysteresis = <2000>; 5144 type = "passive"; 5145 }; 5146 5147 cpu4_crit: cpu_crit { 5148 temperature = <110000>; 5149 hysteresis = <1000>; 5150 type = "critical"; 5151 }; 5152 }; 5153 5154 cooling-maps { 5155 map0 { 5156 trip = <&cpu4_alert0>; 5157 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5158 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5159 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5160 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5161 }; 5162 map1 { 5163 trip = <&cpu4_alert1>; 5164 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5165 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5166 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5167 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5168 }; 5169 }; 5170 }; 5171 5172 cpu5-thermal { 5173 polling-delay-passive = <250>; 5174 polling-delay = <1000>; 5175 5176 thermal-sensors = <&tsens0 8>; 5177 5178 trips { 5179 cpu5_alert0: trip-point0 { 5180 temperature = <90000>; 5181 hysteresis = <2000>; 5182 type = "passive"; 5183 }; 5184 5185 cpu5_alert1: trip-point1 { 5186 temperature = <95000>; 5187 hysteresis = <2000>; 5188 type = "passive"; 5189 }; 5190 5191 cpu5_crit: cpu_crit { 5192 temperature = <110000>; 5193 hysteresis = <1000>; 5194 type = "critical"; 5195 }; 5196 }; 5197 5198 cooling-maps { 5199 map0 { 5200 trip = <&cpu5_alert0>; 5201 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5202 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5203 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5204 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5205 }; 5206 map1 { 5207 trip = <&cpu5_alert1>; 5208 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5209 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5210 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5211 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5212 }; 5213 }; 5214 }; 5215 5216 cpu6-thermal { 5217 polling-delay-passive = <250>; 5218 polling-delay = <1000>; 5219 5220 thermal-sensors = <&tsens0 9>; 5221 5222 trips { 5223 cpu6_alert0: trip-point0 { 5224 temperature = <90000>; 5225 hysteresis = <2000>; 5226 type = "passive"; 5227 }; 5228 5229 cpu6_alert1: trip-point1 { 5230 temperature = <95000>; 5231 hysteresis = <2000>; 5232 type = "passive"; 5233 }; 5234 5235 cpu6_crit: cpu_crit { 5236 temperature = <110000>; 5237 hysteresis = <1000>; 5238 type = "critical"; 5239 }; 5240 }; 5241 5242 cooling-maps { 5243 map0 { 5244 trip = <&cpu6_alert0>; 5245 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5246 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5247 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5248 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5249 }; 5250 map1 { 5251 trip = <&cpu6_alert1>; 5252 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5253 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5254 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5255 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5256 }; 5257 }; 5258 }; 5259 5260 cpu7-thermal { 5261 polling-delay-passive = <250>; 5262 polling-delay = <1000>; 5263 5264 thermal-sensors = <&tsens0 10>; 5265 5266 trips { 5267 cpu7_alert0: trip-point0 { 5268 temperature = <90000>; 5269 hysteresis = <2000>; 5270 type = "passive"; 5271 }; 5272 5273 cpu7_alert1: trip-point1 { 5274 temperature = <95000>; 5275 hysteresis = <2000>; 5276 type = "passive"; 5277 }; 5278 5279 cpu7_crit: cpu_crit { 5280 temperature = <110000>; 5281 hysteresis = <1000>; 5282 type = "critical"; 5283 }; 5284 }; 5285 5286 cooling-maps { 5287 map0 { 5288 trip = <&cpu7_alert0>; 5289 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5290 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5291 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5292 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5293 }; 5294 map1 { 5295 trip = <&cpu7_alert1>; 5296 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5297 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5298 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5299 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5300 }; 5301 }; 5302 }; 5303 5304 aoss0-thermal { 5305 polling-delay-passive = <250>; 5306 polling-delay = <1000>; 5307 5308 thermal-sensors = <&tsens0 0>; 5309 5310 trips { 5311 aoss0_alert0: trip-point0 { 5312 temperature = <90000>; 5313 hysteresis = <2000>; 5314 type = "hot"; 5315 }; 5316 }; 5317 }; 5318 5319 cluster0-thermal { 5320 polling-delay-passive = <250>; 5321 polling-delay = <1000>; 5322 5323 thermal-sensors = <&tsens0 5>; 5324 5325 trips { 5326 cluster0_alert0: trip-point0 { 5327 temperature = <90000>; 5328 hysteresis = <2000>; 5329 type = "hot"; 5330 }; 5331 cluster0_crit: cluster0_crit { 5332 temperature = <110000>; 5333 hysteresis = <2000>; 5334 type = "critical"; 5335 }; 5336 }; 5337 }; 5338 5339 cluster1-thermal { 5340 polling-delay-passive = <250>; 5341 polling-delay = <1000>; 5342 5343 thermal-sensors = <&tsens0 6>; 5344 5345 trips { 5346 cluster1_alert0: trip-point0 { 5347 temperature = <90000>; 5348 hysteresis = <2000>; 5349 type = "hot"; 5350 }; 5351 cluster1_crit: cluster1_crit { 5352 temperature = <110000>; 5353 hysteresis = <2000>; 5354 type = "critical"; 5355 }; 5356 }; 5357 }; 5358 5359 gpu-thermal-top { 5360 polling-delay-passive = <250>; 5361 polling-delay = <1000>; 5362 5363 thermal-sensors = <&tsens0 11>; 5364 5365 trips { 5366 gpu1_alert0: trip-point0 { 5367 temperature = <90000>; 5368 hysteresis = <2000>; 5369 type = "hot"; 5370 }; 5371 }; 5372 }; 5373 5374 gpu-thermal-bottom { 5375 polling-delay-passive = <250>; 5376 polling-delay = <1000>; 5377 5378 thermal-sensors = <&tsens0 12>; 5379 5380 trips { 5381 gpu2_alert0: trip-point0 { 5382 temperature = <90000>; 5383 hysteresis = <2000>; 5384 type = "hot"; 5385 }; 5386 }; 5387 }; 5388 5389 aoss1-thermal { 5390 polling-delay-passive = <250>; 5391 polling-delay = <1000>; 5392 5393 thermal-sensors = <&tsens1 0>; 5394 5395 trips { 5396 aoss1_alert0: trip-point0 { 5397 temperature = <90000>; 5398 hysteresis = <2000>; 5399 type = "hot"; 5400 }; 5401 }; 5402 }; 5403 5404 q6-modem-thermal { 5405 polling-delay-passive = <250>; 5406 polling-delay = <1000>; 5407 5408 thermal-sensors = <&tsens1 1>; 5409 5410 trips { 5411 q6_modem_alert0: trip-point0 { 5412 temperature = <90000>; 5413 hysteresis = <2000>; 5414 type = "hot"; 5415 }; 5416 }; 5417 }; 5418 5419 mem-thermal { 5420 polling-delay-passive = <250>; 5421 polling-delay = <1000>; 5422 5423 thermal-sensors = <&tsens1 2>; 5424 5425 trips { 5426 mem_alert0: trip-point0 { 5427 temperature = <90000>; 5428 hysteresis = <2000>; 5429 type = "hot"; 5430 }; 5431 }; 5432 }; 5433 5434 wlan-thermal { 5435 polling-delay-passive = <250>; 5436 polling-delay = <1000>; 5437 5438 thermal-sensors = <&tsens1 3>; 5439 5440 trips { 5441 wlan_alert0: trip-point0 { 5442 temperature = <90000>; 5443 hysteresis = <2000>; 5444 type = "hot"; 5445 }; 5446 }; 5447 }; 5448 5449 q6-hvx-thermal { 5450 polling-delay-passive = <250>; 5451 polling-delay = <1000>; 5452 5453 thermal-sensors = <&tsens1 4>; 5454 5455 trips { 5456 q6_hvx_alert0: trip-point0 { 5457 temperature = <90000>; 5458 hysteresis = <2000>; 5459 type = "hot"; 5460 }; 5461 }; 5462 }; 5463 5464 camera-thermal { 5465 polling-delay-passive = <250>; 5466 polling-delay = <1000>; 5467 5468 thermal-sensors = <&tsens1 5>; 5469 5470 trips { 5471 camera_alert0: trip-point0 { 5472 temperature = <90000>; 5473 hysteresis = <2000>; 5474 type = "hot"; 5475 }; 5476 }; 5477 }; 5478 5479 video-thermal { 5480 polling-delay-passive = <250>; 5481 polling-delay = <1000>; 5482 5483 thermal-sensors = <&tsens1 6>; 5484 5485 trips { 5486 video_alert0: trip-point0 { 5487 temperature = <90000>; 5488 hysteresis = <2000>; 5489 type = "hot"; 5490 }; 5491 }; 5492 }; 5493 5494 modem-thermal { 5495 polling-delay-passive = <250>; 5496 polling-delay = <1000>; 5497 5498 thermal-sensors = <&tsens1 7>; 5499 5500 trips { 5501 modem_alert0: trip-point0 { 5502 temperature = <90000>; 5503 hysteresis = <2000>; 5504 type = "hot"; 5505 }; 5506 }; 5507 }; 5508 }; 5509 }; 5510
Indexes created Tue Sep 30 17:09:57 GMT 2025