1 /* $NetBSD: ciphy.c,v 1.42 2023/02/22 08:09:09 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.42 2023/02/22 08:09:09 msaitoh Exp $"); 39 40 /* 41 * Driver for the Cicada CS8201 10/100/1000 copper PHY. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include <dev/mii/miidevs.h> 58 59 #include <dev/mii/ciphyreg.h> 60 61 static int ciphymatch(device_t, cfdata_t, void *); 62 static void ciphyattach(device_t, device_t, void *); 63 64 CFATTACH_DECL_NEW(ciphy, sizeof(struct mii_softc), 65 ciphymatch, ciphyattach, mii_phy_detach, mii_phy_activate); 66 67 static int ciphy_service(struct mii_softc *, struct mii_data *, int); 68 static void ciphy_status(struct mii_softc *); 69 static void ciphy_reset(struct mii_softc *); 70 static void ciphy_fixup(struct mii_softc *); 71 72 static const struct mii_phy_funcs ciphy_funcs = { 73 ciphy_service, ciphy_status, mii_phy_reset, 74 }; 75 76 static const struct mii_phydesc ciphys[] = { 77 MII_PHY_DESC(xxCICADA, CIS8201), 78 MII_PHY_DESC(xxCICADA, CIS8201A), 79 MII_PHY_DESC(xxCICADA, CIS8201B), 80 MII_PHY_DESC(xxCICADA, CIS8204), 81 MII_PHY_DESC(xxCICADA, VSC8211), 82 MII_PHY_DESC(xxCICADA, VSC8221), 83 MII_PHY_DESC(xxCICADA, VSC8234), 84 MII_PHY_DESC(xxCICADA, VSC8244), 85 MII_PHY_DESC(xxVITESSE, VSC8601), 86 MII_PHY_DESC(xxVITESSE, VSC8641), 87 MII_PHY_END, 88 }; 89 90 static int 91 ciphymatch(device_t parent, cfdata_t match, 92 void *aux) 93 { 94 struct mii_attach_args *ma = aux; 95 96 if (mii_phy_match(ma, ciphys) != NULL) 97 return 10; 98 99 return 0; 100 } 101 102 static void 103 ciphyattach(device_t parent, device_t self, void *aux) 104 { 105 struct mii_softc *sc = device_private(self); 106 struct mii_attach_args *ma = aux; 107 struct mii_data *mii = ma->mii_data; 108 const struct mii_phydesc *mpd; 109 110 mpd = mii_phy_match(ma, ciphys); 111 aprint_naive(": Media interface\n"); 112 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 113 114 sc->mii_dev = self; 115 sc->mii_inst = mii->mii_instance; 116 sc->mii_phy = ma->mii_phyno; 117 sc->mii_funcs = &ciphy_funcs; 118 sc->mii_pdata = mii; 119 sc->mii_flags = ma->mii_flags; 120 sc->mii_flags |= MIIF_NOISOLATE; 121 122 mii_lock(mii); 123 124 ciphy_reset(sc); 125 126 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 127 sc->mii_capabilities &= ma->mii_capmask; 128 if (sc->mii_capabilities & BMSR_EXTSTAT) 129 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 130 131 mii_unlock(mii); 132 133 mii_phy_add_media(sc); 134 } 135 136 static int 137 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 138 { 139 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 140 uint16_t reg, speed, gig; 141 142 KASSERT(mii_locked(mii)); 143 144 switch (cmd) { 145 case MII_POLLSTAT: 146 /* If we're not polling our PHY instance, just return. */ 147 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 148 return 0; 149 break; 150 151 case MII_MEDIACHG: 152 /* 153 * If the media indicates a different PHY instance, 154 * isolate ourselves. 155 */ 156 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 157 PHY_READ(sc, MII_BMCR, ®); 158 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 159 return 0; 160 } 161 162 /* If the interface is not up, don't do anything. */ 163 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 164 break; 165 166 ciphy_fixup(sc); /* XXX hardware bug work-around */ 167 168 switch (IFM_SUBTYPE(ife->ifm_media)) { 169 case IFM_AUTO: 170 #ifdef foo 171 /* If we're already in auto mode, just return. */ 172 PHY_READ(sc, MII_BMCR, ®); 173 if (reg & BMCR_AUTOEN) 174 return 0; 175 #endif 176 (void) mii_phy_auto(sc); 177 break; 178 case IFM_1000_T: 179 speed = BMCR_S1000; 180 goto setit; 181 case IFM_100_TX: 182 speed = BMCR_S100; 183 goto setit; 184 case IFM_10_T: 185 speed = BMCR_S10; 186 setit: 187 if ((ife->ifm_media & IFM_FDX) != 0) { 188 speed |= BMCR_FDX; 189 gig = GTCR_ADV_1000TFDX; 190 } else 191 gig = GTCR_ADV_1000THDX; 192 193 PHY_WRITE(sc, MII_GTCR, 0); 194 PHY_WRITE(sc, MII_BMCR, speed); 195 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 196 197 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 198 break; 199 200 PHY_WRITE(sc, MII_GTCR, gig); 201 PHY_WRITE(sc, MII_BMCR, 202 speed | BMCR_AUTOEN | BMCR_STARTNEG); 203 204 /* 205 * When setting the link manually, one side must 206 * be the master and the other the slave. However 207 * ifmedia doesn't give us a good way to specify 208 * this, so we fake it by using one of the LINK 209 * flags. If LINK0 is set, we program the PHY to 210 * be a master, otherwise it's a slave. 211 */ 212 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 213 PHY_WRITE(sc, MII_GTCR, 214 gig | GTCR_MAN_MS | GTCR_ADV_MS); 215 } else 216 PHY_WRITE(sc, MII_GTCR, gig | GTCR_MAN_MS); 217 break; 218 case IFM_NONE: 219 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 220 break; 221 case IFM_100_T4: 222 default: 223 return EINVAL; 224 } 225 break; 226 227 case MII_TICK: 228 /* If we're not currently selected, just return. */ 229 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 230 return 0; 231 232 /* Is the interface even up? */ 233 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 234 return 0; 235 236 /* Only used for autonegotiation. */ 237 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 238 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 239 /* 240 * Reset autonegotiation timer to 0 just to make sure 241 * the future autonegotiation start with 0. 242 */ 243 sc->mii_ticks = 0; 244 break; 245 } 246 247 /* 248 * Check to see if we have link. If we do, we don't 249 * need to restart the autonegotiation process. Read 250 * the BMSR twice in case it's latched. 251 */ 252 PHY_READ(sc, MII_BMSR, ®); 253 PHY_READ(sc, MII_BMSR, ®); 254 if (reg & BMSR_LINK) { 255 /* 256 * Reset autonegotiation timer to 0 in case the link 257 * goes down in the next tick. 258 */ 259 sc->mii_ticks = 0; 260 /* See above. */ 261 break; 262 } 263 264 /* 265 * mii_ticks == 0 means it's the first tick after changing the 266 * media or the link became down since the last tick 267 * (see above), so return with 0 to update the status. 268 */ 269 if (sc->mii_ticks++ == 0) 270 break; 271 272 /* Only retry autonegotiation every N seconds. */ 273 if (sc->mii_ticks < sc->mii_anegticks) 274 break; 275 276 mii_phy_auto_restart(sc); 277 return 0; 278 } 279 280 /* Update the media status. */ 281 ciphy_status(sc); 282 283 /* 284 * Callback if something changed. Note that we need to poke 285 * apply fixups for certain PHY revs. 286 */ 287 if (sc->mii_media_active != mii->mii_media_active || 288 sc->mii_media_status != mii->mii_media_status || 289 cmd == MII_MEDIACHG) { 290 ciphy_fixup(sc); 291 } 292 mii_phy_update(sc, cmd); 293 return 0; 294 } 295 296 static void 297 ciphy_status(struct mii_softc *sc) 298 { 299 struct mii_data *mii = sc->mii_pdata; 300 uint16_t bmsr, bmcr, gtsr; 301 302 KASSERT(mii_locked(mii)); 303 304 mii->mii_media_status = IFM_AVALID; 305 mii->mii_media_active = IFM_ETHER; 306 307 PHY_READ(sc, MII_BMSR, &bmsr); 308 PHY_READ(sc, MII_BMSR, &bmsr); 309 310 if (bmsr & BMSR_LINK) 311 mii->mii_media_status |= IFM_ACTIVE; 312 313 PHY_READ(sc, MII_BMCR, &bmcr); 314 315 if (bmcr & BMCR_LOOP) 316 mii->mii_media_active |= IFM_LOOP; 317 318 if (bmcr & BMCR_AUTOEN) { 319 if ((bmsr & BMSR_ACOMP) == 0) { 320 /* Erg, still trying, I guess... */ 321 mii->mii_media_active |= IFM_NONE; 322 return; 323 } 324 } 325 326 PHY_READ(sc, CIPHY_MII_AUXCSR, &bmsr); 327 switch (bmsr & CIPHY_AUXCSR_SPEED) { 328 case CIPHY_SPEED10: 329 mii->mii_media_active |= IFM_10_T; 330 break; 331 case CIPHY_SPEED100: 332 mii->mii_media_active |= IFM_100_TX; 333 break; 334 case CIPHY_SPEED1000: 335 mii->mii_media_active |= IFM_1000_T; 336 break; 337 default: 338 aprint_error_dev(sc->mii_dev, "unknown PHY speed %x\n", 339 bmsr & CIPHY_AUXCSR_SPEED); 340 break; 341 } 342 343 if (bmsr & CIPHY_AUXCSR_FDX) 344 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 345 else 346 mii->mii_media_active |= IFM_HDX; 347 348 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 349 PHY_READ(sc, MII_GTSR, >sr); 350 if ((gtsr & GTSR_MS_RES) != 0) 351 mii->mii_media_active |= IFM_ETH_MASTER; 352 } 353 } 354 355 static void 356 ciphy_reset(struct mii_softc *sc) 357 { 358 359 KASSERT(mii_locked(sc->mii_pdata)); 360 361 mii_phy_reset(sc); 362 DELAY(1000); 363 } 364 365 static inline int 366 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 367 { 368 uint16_t _tmp; 369 int rv; 370 371 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 372 return rv; 373 return PHY_WRITE(sc, y, _tmp | z); 374 } 375 376 static inline int 377 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 378 { 379 uint16_t _tmp; 380 int rv; 381 382 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 383 return rv; 384 return PHY_WRITE(sc, y, _tmp & ~z); 385 } 386 387 static void 388 ciphy_fixup(struct mii_softc *sc) 389 { 390 uint16_t model, status, speed; 391 uint16_t reg; 392 393 PHY_READ(sc, MII_PHYIDR2, ®); 394 model = MII_MODEL(reg); 395 PHY_READ(sc, CIPHY_MII_AUXCSR, &status); 396 speed = status & CIPHY_AUXCSR_SPEED; 397 398 if (device_is_a(device_parent(sc->mii_dev), "nfe")) { 399 /* Need to set for 2.5V RGMII for NVIDIA adapters */ 400 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII); 401 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV); 402 } 403 404 switch (model) { 405 case MII_MODEL_xxCICADA_CIS8201: 406 case MII_MODEL_xxCICADA_CIS8204: 407 /* Turn off "aux mode" (whatever that means) */ 408 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 409 410 /* 411 * Work around speed polling bug in VT3119/VT3216 412 * when using MII in full duplex mode. 413 */ 414 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 415 (status & CIPHY_AUXCSR_FDX)) 416 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 417 else 418 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 419 420 /* Enable link/activity LED blink. */ 421 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 422 423 break; 424 425 case MII_MODEL_xxCICADA_CIS8201A: 426 case MII_MODEL_xxCICADA_CIS8201B: 427 /* 428 * Work around speed polling bug in VT3119/VT3216 429 * when using MII in full duplex mode. 430 */ 431 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 432 (status & CIPHY_AUXCSR_FDX)) 433 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 434 else 435 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 436 437 break; 438 case MII_MODEL_xxCICADA_VSC8211: 439 case MII_MODEL_xxCICADA_VSC8221: 440 case MII_MODEL_xxCICADA_VSC8234: 441 case MII_MODEL_xxCICADA_VSC8244: 442 case MII_MODEL_xxVITESSE_VSC8601: 443 case MII_MODEL_xxVITESSE_VSC8641: 444 break; 445 default: 446 aprint_error_dev(sc->mii_dev, "unknown CICADA PHY model %x\n", 447 model); 448 break; 449 } 450 } 451
Indexes created Sun Oct 25 00:26:45 UTC 2026