| /src/sys/arch/cobalt/stand/boot/ |
| wdc.c | 58 uint8_t st0, st1; local in function:__wdcwait_reset
64 st0 = WDC_READ_REG(chp, wd_status);
77 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
83 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
92 if (st0 & WDCS_BSY)
115 uint8_t st0, st1; local in function:wdcprobe
124 st0 = WDC_READ_REG(chp, wd_status);
129 if (st0 == 0xff || st0 == WDSD_IBM)
|
| /src/sys/arch/mmeye/stand/boot/ |
| wdc.c | 67 uint8_t st0, st1; local in function:__wdcwait_reset
73 st0 = WDC_READ_REG(chp, wd_status);
86 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
92 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
101 if (st0 & WDCS_BSY)
124 uint8_t st0, st1; local in function:wdcprobe
133 st0 = WDC_READ_REG(chp, wd_status);
138 if (st0 == 0xff || st0 == WDSD_IBM)
|
| /src/sys/arch/bebox/stand/boot/ |
| wdc.c | 64 uint8_t st0, st1; local in function:__wdcwait_reset
70 st0 = WDC_READ_REG(chp, wd_status);
83 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
89 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
98 if (st0 & WDCS_BSY)
150 uint8_t st0, st1; local in function:wdcprobe
160 st0 = WDC_READ_REG(chp, wd_status);
165 if (st0 == 0xff || st0 == WDSD_IBM)
172 if (!(st0 & WDCS_DRDY)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_nv50.c | 149 u8 st0, st1, st2, st3; local in function:nv50_fb_intr
167 st0 = (trap[0] & 0x0000000f) >> 0;
172 st0 = (trap[0] & 0x000000ff) >> 0;
179 en = nvkm_enum_find(vm_engine, st0);
194 st0, en ? en->name : "",
|
| /src/bin/csh/ |
| exec.c | 271 Char *lastsh[2], **vp, *st0, **ost; local in function:texec
324 st0 = st[0];
328 ost[0] = st0;
|
| /src/sbin/tunefs/ |
| tunefs.c | 483 struct stat st0, st; local in function:isactive
487 if (fstat(fd, &st0) == -1) {
500 if (st.st_rdev != st0.st_rdev)
|
| /src/sys/dev/ic/ |
| wdc.c | 299 u_int8_t st0 = 0, st1 = 0; local in function:wdc_drvprobe
336 st0 = bus_space_read_1(wdr->cmd_iot,
342 (st0 & WDCS_DRDY)) &&
356 if ((st0 & WDCS_DRDY) == 0 &&
364 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n",
366 chp->ch_channel, st0, st1), DEBUG_PROBE);
526 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; local in function:wdcprobe1
546 st0 = bus_space_read_1(wdr->cmd_iot,
557 if ((st0 & WDCS_BSY) == 0)
561 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n"
1104 u_int8_t st0 = 0, st1 = 0; local in function:__wdcwait_reset
[all...] |
| mvsata.c | 3353 uint8_t st0; local in function:mvsata_softreset
3365 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS);
3367 if ((st0 & WDCS_BSY) == 0) {
|
| /src/sys/dev/isa/ |
| fd.c | 991 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
995 printf(" (st0 %s", bits);
1051 #define st0 fdc->sc_status[0] macro
1227 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 ||
1253 if (fdcresult(fdc) != 7 || (st0 & 0xf8) != 0) {
1315 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
1334 #undef st0
|
| /src/sys/arch/arc/jazz/ |
| fd.c | 710 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
714 printf(" (st0 %s", bits);
782 #define st0 fdc->sc_status[0] macro
926 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 ||
953 if (i != 7 || (st0 & 0xf8) != 0) {
1015 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
1037 #undef st0
|
| /src/sys/arch/atari/dev/ |
| hdfd.c | 874 printf(" (st0 %s", bits);
903 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
950 #define st0 fdc->sc_status[0] macro
1128 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 ||
1223 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
1245 #undef st0
|
| /src/sys/arch/acorn32/mainbus/ |
| fd.c | 843 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
847 printf(" (st0 %s", bits);
915 #define st0 fdc->sc_status[0] macro
1110 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 ||
1136 if (fdcresult(fdc) != 7 || (st0 & 0xf8) != 0) {
1204 if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
1226 #undef st0
|
| /src/sys/arch/sparc64/dev/ |
| fdc.c | 1411 printf(" (st0 %s", bits);
1451 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
1613 #define st0 fdc->sc_status[0] macro
1754 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 ||
1859 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 ||
1913 ((st0 & 0xf8) != 0 &&
1914 ((st0 & 0xf8) != 0x20 || (fdc->sc_cfg & CFG_EIS) == 0))) {
2023 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
2057 #undef st0
|
| /src/sys/arch/sparc/dev/ |
| fd.c | 1233 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
1237 printf(" (st0 %s", bits);
1430 #define st0 fdc->sc_status[0] macro
1571 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 ||
1674 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 ||
1728 ((st0 & 0xf8) != 0 &&
1729 ((st0 & 0xf8) != 0x20 || (fdc->sc_cfg & CFG_EIS) == 0))) {
1836 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
1870 #undef st0
|
| /src/sys/arch/x68k/dev/ |
| fd.c | 1026 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
1030 printf(" (st0 %s", bits);
1098 #define st0 fdc->sc_status[0] macro
1118 (st0 & 0xf8) != 0x20) {
1408 if ((st0 & 0xf8) == 0xc0) {
1413 (st0 & 0xf8) != 0x20 ||
1435 if ((tmp = fdcresult(fdc)) != 7 || (st0 & 0xf8) != 0) {
1467 if ((tmp = fdcresult(fdc)) != 7 || (st0 & 0xf8) != 0) {
1468 printf("fdcintr: resnum=%d, st0=%x\n", tmp, st0);
[all...] |
| /src/sys/arch/sun3/dev/ |
| fd.c | 989 printf(" (st0 %s cyl %d)\n", bits, fdc->sc_status[1]);
993 printf(" (st0 %s", bits);
1152 #define st0 fdc->sc_status[0] macro
1373 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 ||
1405 if (fdc->sc_nstat != 7 || (st0 & 0xf8) != 0 || st1 != 0) {
1514 if (fdc->sc_nstat != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
1537 #undef st0
|
