1 /* $NetBSD: if_ste.c,v 1.66 2024/06/29 12:11:12 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.66 2024/06/29 12:11:12 riastradh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/queue.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #include <sys/bus.h> 60 #include <sys/intr.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/mii_bitbang.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/pci/if_stereg.h> 71 72 /* 73 * Transmit descriptor list size. 74 */ 75 #define STE_NTXDESC 256 76 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 77 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 78 79 /* 80 * Receive descriptor list size. 81 */ 82 #define STE_NRXDESC 128 83 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 84 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 85 86 /* 87 * Control structures are DMA'd to the ST-201 chip. We allocate them in 88 * a single clump that maps to a single DMA segment to make several things 89 * easier. 90 */ 91 struct ste_control_data { 92 /* 93 * The transmit descriptors. 94 */ 95 struct ste_tfd scd_txdescs[STE_NTXDESC]; 96 97 /* 98 * The receive descriptors. 99 */ 100 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 101 }; 102 103 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 104 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 105 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 106 107 /* 108 * Software state for transmit and receive jobs. 109 */ 110 struct ste_descsoft { 111 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 112 bus_dmamap_t ds_dmamap; /* our DMA map */ 113 }; 114 115 /* 116 * Software state per device. 117 */ 118 struct ste_softc { 119 device_t sc_dev; /* generic device information */ 120 bus_space_tag_t sc_st; /* bus space tag */ 121 bus_space_handle_t sc_sh; /* bus space handle */ 122 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 123 struct ethercom sc_ethercom; /* ethernet common data */ 124 125 void *sc_ih; /* interrupt cookie */ 126 127 struct mii_data sc_mii; /* MII/media information */ 128 129 callout_t sc_tick_ch; /* tick callout */ 130 131 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 132 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 133 134 /* 135 * Software state for transmit and receive descriptors. 136 */ 137 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 138 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 139 140 /* 141 * Control data structures. 142 */ 143 struct ste_control_data *sc_control_data; 144 #define sc_txdescs sc_control_data->scd_txdescs 145 #define sc_rxdescs sc_control_data->scd_rxdescs 146 147 int sc_txpending; /* number of Tx requests pending */ 148 int sc_txdirty; /* first dirty Tx descriptor */ 149 int sc_txlast; /* last used Tx descriptor */ 150 151 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 152 153 int sc_txthresh; /* Tx threshold */ 154 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 155 uint16_t sc_IntEnable; /* prototype IntEnable register */ 156 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 157 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 158 159 bool sc_enable_phy0; /* access to phy #0 allowed */ 160 }; 161 162 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 163 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 164 165 #define STE_CDTXSYNC(sc, x, ops) \ 166 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 167 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 168 169 #define STE_CDRXSYNC(sc, x, ops) \ 170 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 171 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 172 173 #define STE_INIT_RXDESC(sc, x) \ 174 do { \ 175 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 176 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 177 struct mbuf *__m = __ds->ds_mbuf; \ 178 \ 179 /* \ 180 * Note: We scoot the packet forward 2 bytes in the buffer \ 181 * so that the payload after the Ethernet header is aligned \ 182 * to a 4-byte boundary. \ 183 */ \ 184 __m->m_data = __m->m_ext.ext_buf + 2; \ 185 __rfd->rfd_frag.frag_addr = \ 186 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 187 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 188 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 189 __rfd->rfd_status = 0; \ 190 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 191 } while (/*CONSTCOND*/0) 192 193 #define STE_TIMEOUT 1000 194 195 static void ste_start(struct ifnet *); 196 static void ste_watchdog(struct ifnet *); 197 static int ste_ioctl(struct ifnet *, u_long, void *); 198 static int ste_init(struct ifnet *); 199 static void ste_stop(struct ifnet *, int); 200 201 static bool ste_shutdown(device_t, int); 202 203 static void ste_reset(struct ste_softc *, uint32_t); 204 static void ste_setthresh(struct ste_softc *); 205 static void ste_txrestart(struct ste_softc *, uint8_t); 206 static void ste_rxdrain(struct ste_softc *); 207 static int ste_add_rxbuf(struct ste_softc *, int); 208 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 209 static void ste_tick(void *); 210 211 static void ste_stats_update(struct ste_softc *); 212 213 static void ste_set_filter(struct ste_softc *); 214 215 static int ste_intr(void *); 216 static void ste_txintr(struct ste_softc *); 217 static void ste_rxintr(struct ste_softc *); 218 219 static int ste_mii_readreg(device_t, int, int, uint16_t *); 220 static int ste_mii_writereg(device_t, int, int, uint16_t); 221 static void ste_mii_statchg(struct ifnet *); 222 223 static int ste_match(device_t, cfdata_t, void *); 224 static void ste_attach(device_t, device_t, void *); 225 226 int ste_copy_small = 0; 227 228 CFATTACH_DECL_NEW(ste, sizeof(struct ste_softc), 229 ste_match, ste_attach, NULL, NULL); 230 231 static uint32_t ste_mii_bitbang_read(device_t); 232 static void ste_mii_bitbang_write(device_t, uint32_t); 233 234 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 235 ste_mii_bitbang_read, 236 ste_mii_bitbang_write, 237 { 238 PC_MgmtData, /* MII_BIT_MDO */ 239 PC_MgmtData, /* MII_BIT_MDI */ 240 PC_MgmtClk, /* MII_BIT_MDC */ 241 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 242 0, /* MII_BIT_DIR_PHY_HOST */ 243 } 244 }; 245 246 /* 247 * Devices supported by this driver. 248 */ 249 struct ste_product { 250 pci_vendor_id_t ste_vendor; 251 pci_product_id_t ste_product; 252 const char *ste_name; 253 const struct ste_product *ste_subs; 254 }; 255 256 static const struct ste_product ste_dlink_products[] = { 257 { PCI_VENDOR_DLINK, 0x1002, 258 "D-Link DFE-550TX 10/100 Ethernet", 259 NULL }, 260 261 { PCI_VENDOR_DLINK, 0x1003, 262 "D-Link DFE-550FX Ethernet", 263 NULL }, 264 265 { PCI_VENDOR_DLINK, 0x1012, 266 "D-Link DFE-580TX 4-port 10/100 Ethernet", 267 NULL }, 268 269 { PCI_VENDOR_DLINK, 0x1040, 270 "D-Link DFE-530TXS 10/100 Ethernet", 271 NULL }, 272 273 { 0, 0, 274 NULL, 275 NULL }, 276 }; 277 278 static const struct ste_product ste_products[] = { 279 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 280 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter", 281 NULL }, 282 283 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 284 "Sundance ST-201 10/100 Ethernet", 285 NULL }, 286 287 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 288 "D-Link DL-1002 10/100 Ethernet", 289 ste_dlink_products }, 290 291 { 0, 0, 292 NULL, 293 NULL }, 294 }; 295 296 static const struct ste_product * 297 ste_lookup_table(pcireg_t pci_id, const struct ste_product * const products) 298 { 299 const struct ste_product *sp; 300 301 for (sp = products; sp->ste_name != NULL; sp++) { 302 if (PCI_VENDOR(pci_id) == sp->ste_vendor && 303 PCI_PRODUCT(pci_id) == sp->ste_product) 304 return (sp); 305 } 306 return (NULL); 307 } 308 309 static const struct ste_product * 310 ste_lookup(const struct pci_attach_args *pa) 311 { 312 const struct ste_product *sp; 313 314 sp = ste_lookup_table(pa->pa_id, ste_products); 315 if (sp && sp->ste_subs) { 316 const pcireg_t subsys = 317 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 318 const struct ste_product *ssp = 319 ste_lookup_table(subsys, sp->ste_subs); 320 if (ssp) 321 sp = ssp; 322 } 323 return (sp); 324 } 325 326 static int 327 ste_match(device_t parent, cfdata_t cf, void *aux) 328 { 329 struct pci_attach_args *pa = aux; 330 331 if (ste_lookup(pa) != NULL) 332 return (1); 333 334 return (0); 335 } 336 337 static void 338 ste_attach(device_t parent, device_t self, void *aux) 339 { 340 struct ste_softc *sc = device_private(self); 341 struct pci_attach_args *pa = aux; 342 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 343 struct mii_data * const mii = &sc->sc_mii; 344 pci_chipset_tag_t pc = pa->pa_pc; 345 pci_intr_handle_t ih; 346 const char *intrstr = NULL; 347 bus_space_tag_t iot, memt; 348 bus_space_handle_t ioh, memh; 349 bus_dma_segment_t seg; 350 int ioh_valid, memh_valid; 351 int i, rseg, error; 352 const struct ste_product *sp; 353 uint8_t enaddr[ETHER_ADDR_LEN]; 354 uint16_t myea[ETHER_ADDR_LEN / 2]; 355 char intrbuf[PCI_INTRSTR_LEN]; 356 357 sc->sc_dev = self; 358 359 callout_init(&sc->sc_tick_ch, 0); 360 callout_setfunc(&sc->sc_tick_ch, ste_tick, sc); 361 362 sp = ste_lookup(pa); 363 if (sp == NULL) { 364 printf("\n"); 365 panic("ste_attach: impossible"); 366 } 367 368 printf(": %s\n", sp->ste_name); 369 370 /* 371 * Map the device. 372 */ 373 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 374 PCI_MAPREG_TYPE_IO, 0, 375 &iot, &ioh, NULL, NULL) == 0); 376 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 377 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 378 &memt, &memh, NULL, NULL) == 0); 379 380 if (memh_valid) { 381 sc->sc_st = memt; 382 sc->sc_sh = memh; 383 } else if (ioh_valid) { 384 sc->sc_st = iot; 385 sc->sc_sh = ioh; 386 } else { 387 aprint_error_dev(self, "unable to map device registers\n"); 388 return; 389 } 390 391 sc->sc_dmat = pa->pa_dmat; 392 393 /* Enable bus mastering. */ 394 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 395 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 396 PCI_COMMAND_MASTER_ENABLE); 397 398 /* power up chip */ 399 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 400 NULL)) && error != EOPNOTSUPP) { 401 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 402 return; 403 } 404 405 /* 406 * Map and establish our interrupt. 407 */ 408 if (pci_intr_map(pa, &ih)) { 409 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 410 return; 411 } 412 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 413 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ste_intr, sc, 414 device_xname(self)); 415 if (sc->sc_ih == NULL) { 416 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 417 if (intrstr != NULL) 418 aprint_error(" at %s", intrstr); 419 aprint_error("\n"); 420 return; 421 } 422 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 423 424 /* 425 * Allocate the control data structures, and create and load the 426 * DMA map for it. 427 */ 428 if ((error = bus_dmamem_alloc(sc->sc_dmat, 429 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 430 0)) != 0) { 431 aprint_error_dev(sc->sc_dev, 432 "unable to allocate control data, error = %d\n", error); 433 goto fail_0; 434 } 435 436 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 437 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 438 BUS_DMA_COHERENT)) != 0) { 439 aprint_error_dev(sc->sc_dev, 440 "unable to map control data, error = %d\n", error); 441 goto fail_1; 442 } 443 444 if ((error = bus_dmamap_create(sc->sc_dmat, 445 sizeof(struct ste_control_data), 1, 446 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 447 aprint_error_dev(sc->sc_dev, 448 "unable to create control data DMA map, error = %d\n", 449 error); 450 goto fail_2; 451 } 452 453 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 454 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 455 0)) != 0) { 456 aprint_error_dev(sc->sc_dev, 457 "unable to load control data DMA map, error = %d\n", 458 error); 459 goto fail_3; 460 } 461 462 /* 463 * Create the transmit buffer DMA maps. 464 */ 465 for (i = 0; i < STE_NTXDESC; i++) { 466 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 467 STE_NTXFRAGS, MCLBYTES, 0, 0, 468 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 469 aprint_error_dev(sc->sc_dev, 470 "unable to create tx DMA map %d, error = %d\n", i, 471 error); 472 goto fail_4; 473 } 474 } 475 476 /* 477 * Create the receive buffer DMA maps. 478 */ 479 for (i = 0; i < STE_NRXDESC; i++) { 480 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 481 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 482 aprint_error_dev(sc->sc_dev, 483 "unable to create rx DMA map %d, error = %d\n", i, 484 error); 485 goto fail_5; 486 } 487 sc->sc_rxsoft[i].ds_mbuf = NULL; 488 } 489 490 /* 491 * Reset the chip to a known state. 492 */ 493 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 494 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 495 496 /* 497 * Read the Ethernet address from the EEPROM. 498 */ 499 for (i = 0; i < 3; i++) { 500 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 501 myea[i] = le16toh(myea[i]); 502 } 503 memcpy(enaddr, myea, sizeof(enaddr)); 504 505 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 506 ether_sprintf(enaddr)); 507 508 /* 509 * Initialize our media structures and probe the MII. 510 */ 511 mii->mii_ifp = ifp; 512 mii->mii_readreg = ste_mii_readreg; 513 mii->mii_writereg = ste_mii_writereg; 514 mii->mii_statchg = ste_mii_statchg; 515 sc->sc_ethercom.ec_mii = mii; 516 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 517 ether_mediastatus); 518 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 519 MII_OFFSET_ANY, 0); 520 if (LIST_FIRST(&mii->mii_phys) == NULL) { 521 /* 522 * It seems that some variants of this chip "ghost" the 523 * single PHY at #0 and #1. We will try probing the MII 524 * first while ignoring #0 access. If we find the PHY, 525 * great! If not, un-ignore #0 and try probing *just* 526 * #0 to see if we can find it. 527 */ 528 sc->sc_enable_phy0 = true; 529 mii_attach(sc->sc_dev, mii, 0xffffffff, 0, 530 MII_OFFSET_ANY, 0); 531 } 532 if (LIST_FIRST(&mii->mii_phys) == NULL) { 533 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 534 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 535 } else 536 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 537 538 ifp = &sc->sc_ethercom.ec_if; 539 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 540 ifp->if_softc = sc; 541 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 542 ifp->if_ioctl = ste_ioctl; 543 ifp->if_start = ste_start; 544 ifp->if_watchdog = ste_watchdog; 545 ifp->if_init = ste_init; 546 ifp->if_stop = ste_stop; 547 IFQ_SET_READY(&ifp->if_snd); 548 549 /* 550 * Default the transmit threshold to 128 bytes. 551 */ 552 sc->sc_txthresh = 128; 553 554 /* 555 * Disable MWI if the PCI layer tells us to. 556 */ 557 sc->sc_DMACtrl = 0; 558 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 559 sc->sc_DMACtrl |= DC_MWIDisable; 560 561 /* 562 * We can support 802.1Q VLAN-sized frames. 563 */ 564 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 565 566 /* 567 * Attach the interface. 568 */ 569 if_attach(ifp); 570 if_deferred_start_init(ifp, NULL); 571 ether_ifattach(ifp, enaddr); 572 573 /* 574 * Make sure the interface is shutdown during reboot. 575 */ 576 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 577 pmf_class_network_register(self, ifp); 578 else 579 aprint_error_dev(self, "couldn't establish power handler\n"); 580 581 return; 582 583 /* 584 * Free any resources we've allocated during the failed attach 585 * attempt. Do this in reverse order and fall through. 586 */ 587 fail_5: 588 for (i = 0; i < STE_NRXDESC; i++) { 589 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 590 bus_dmamap_destroy(sc->sc_dmat, 591 sc->sc_rxsoft[i].ds_dmamap); 592 } 593 fail_4: 594 for (i = 0; i < STE_NTXDESC; i++) { 595 if (sc->sc_txsoft[i].ds_dmamap != NULL) 596 bus_dmamap_destroy(sc->sc_dmat, 597 sc->sc_txsoft[i].ds_dmamap); 598 } 599 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 600 fail_3: 601 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 602 fail_2: 603 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 604 sizeof(struct ste_control_data)); 605 fail_1: 606 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 607 fail_0: 608 return; 609 } 610 611 /* 612 * ste_shutdown: 613 * 614 * Make sure the interface is stopped at reboot time. 615 */ 616 static bool 617 ste_shutdown(device_t self, int howto) 618 { 619 struct ste_softc *sc; 620 621 sc = device_private(self); 622 ste_stop(&sc->sc_ethercom.ec_if, 1); 623 624 return true; 625 } 626 627 static void 628 ste_dmahalt_wait(struct ste_softc *sc) 629 { 630 int i; 631 632 for (i = 0; i < STE_TIMEOUT; i++) { 633 delay(2); 634 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 635 DC_DMAHaltBusy) == 0) 636 break; 637 } 638 639 if (i == STE_TIMEOUT) 640 printf("%s: DMA halt timed out\n", device_xname(sc->sc_dev)); 641 } 642 643 /* 644 * ste_start: [ifnet interface function] 645 * 646 * Start packet transmission on the interface. 647 */ 648 static void 649 ste_start(struct ifnet *ifp) 650 { 651 struct ste_softc *sc = ifp->if_softc; 652 struct mbuf *m0, *m; 653 struct ste_descsoft *ds; 654 struct ste_tfd *tfd; 655 bus_dmamap_t dmamap; 656 int error, olasttx, nexttx, opending, seg, totlen; 657 658 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 659 return; 660 661 /* 662 * Remember the previous number of pending transmissions 663 * and the current last descriptor in the list. 664 */ 665 opending = sc->sc_txpending; 666 olasttx = sc->sc_txlast; 667 668 /* 669 * Loop through the send queue, setting up transmit descriptors 670 * until we drain the queue, or use up all available transmit 671 * descriptors. 672 */ 673 while (sc->sc_txpending < STE_NTXDESC) { 674 /* 675 * Grab a packet off the queue. 676 */ 677 IFQ_POLL(&ifp->if_snd, m0); 678 if (m0 == NULL) 679 break; 680 m = NULL; 681 682 /* 683 * Get the last and next available transmit descriptor. 684 */ 685 nexttx = STE_NEXTTX(sc->sc_txlast); 686 tfd = &sc->sc_txdescs[nexttx]; 687 ds = &sc->sc_txsoft[nexttx]; 688 689 dmamap = ds->ds_dmamap; 690 691 /* 692 * Load the DMA map. If this fails, the packet either 693 * didn't fit in the allotted number of segments, or we 694 * were short on resources. In this case, we'll copy 695 * and try again. 696 */ 697 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 698 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 699 MGETHDR(m, M_DONTWAIT, MT_DATA); 700 if (m == NULL) { 701 printf("%s: unable to allocate Tx mbuf\n", 702 device_xname(sc->sc_dev)); 703 break; 704 } 705 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 706 if (m0->m_pkthdr.len > MHLEN) { 707 MCLGET(m, M_DONTWAIT); 708 if ((m->m_flags & M_EXT) == 0) { 709 printf("%s: unable to allocate Tx " 710 "cluster\n", 711 device_xname(sc->sc_dev)); 712 m_freem(m); 713 break; 714 } 715 } 716 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 717 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 718 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 719 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 720 if (error) { 721 printf("%s: unable to load Tx buffer, " 722 "error = %d\n", device_xname(sc->sc_dev), 723 error); 724 m_freem(m); 725 break; 726 } 727 } 728 729 IFQ_DEQUEUE(&ifp->if_snd, m0); 730 if (m != NULL) { 731 m_freem(m0); 732 m0 = m; 733 } 734 735 /* 736 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 737 */ 738 739 /* Sync the DMA map. */ 740 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 741 BUS_DMASYNC_PREWRITE); 742 743 /* Initialize the fragment list. */ 744 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 745 tfd->tfd_frags[seg].frag_addr = 746 htole32(dmamap->dm_segs[seg].ds_addr); 747 tfd->tfd_frags[seg].frag_len = 748 htole32(dmamap->dm_segs[seg].ds_len); 749 totlen += dmamap->dm_segs[seg].ds_len; 750 } 751 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 752 753 /* Initialize the descriptor. */ 754 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 755 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 756 757 /* Sync the descriptor. */ 758 STE_CDTXSYNC(sc, nexttx, 759 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 760 761 /* 762 * Store a pointer to the packet so we can free it later, 763 * and remember what txdirty will be once the packet is 764 * done. 765 */ 766 ds->ds_mbuf = m0; 767 768 /* Advance the tx pointer. */ 769 sc->sc_txpending++; 770 sc->sc_txlast = nexttx; 771 772 /* 773 * Pass the packet to any BPF listeners. 774 */ 775 bpf_mtap(ifp, m0, BPF_D_OUT); 776 } 777 778 if (sc->sc_txpending != opending) { 779 /* 780 * We enqueued packets. If the transmitter was idle, 781 * reset the txdirty pointer. 782 */ 783 if (opending == 0) 784 sc->sc_txdirty = STE_NEXTTX(olasttx); 785 786 /* 787 * Cause a descriptor interrupt to happen on the 788 * last packet we enqueued, and also cause the 789 * DMA engine to wait after is has finished processing 790 * it. 791 */ 792 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 793 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 794 htole32(TFD_TxDMAIndicate); 795 STE_CDTXSYNC(sc, sc->sc_txlast, 796 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 797 798 /* 799 * Link up the new chain of descriptors to the 800 * last. 801 */ 802 sc->sc_txdescs[olasttx].tfd_next = 803 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 804 STE_CDTXSYNC(sc, olasttx, 805 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 806 807 /* 808 * Kick the transmit DMA logic. Note that since we're 809 * using auto-polling, reading the Tx desc pointer will 810 * give it the nudge it needs to get going. 811 */ 812 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 813 STE_TxDMAListPtr) == 0) { 814 bus_space_write_4(sc->sc_st, sc->sc_sh, 815 STE_DMACtrl, DC_TxDMAHalt); 816 ste_dmahalt_wait(sc); 817 bus_space_write_4(sc->sc_st, sc->sc_sh, 818 STE_TxDMAListPtr, 819 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 820 bus_space_write_4(sc->sc_st, sc->sc_sh, 821 STE_DMACtrl, DC_TxDMAResume); 822 } 823 824 /* Set a watchdog timer in case the chip flakes out. */ 825 ifp->if_timer = 5; 826 } 827 } 828 829 /* 830 * ste_watchdog: [ifnet interface function] 831 * 832 * Watchdog timer handler. 833 */ 834 static void 835 ste_watchdog(struct ifnet *ifp) 836 { 837 struct ste_softc *sc = ifp->if_softc; 838 839 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 840 if_statinc(ifp, if_oerrors); 841 842 ste_txintr(sc); 843 ste_rxintr(sc); 844 (void) ste_init(ifp); 845 846 /* Try to get more packets going. */ 847 ste_start(ifp); 848 } 849 850 /* 851 * ste_ioctl: [ifnet interface function] 852 * 853 * Handle control requests from the operator. 854 */ 855 static int 856 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 857 { 858 struct ste_softc *sc = ifp->if_softc; 859 int s, error; 860 861 s = splnet(); 862 863 error = ether_ioctl(ifp, cmd, data); 864 if (error == ENETRESET) { 865 /* 866 * Multicast list has changed; set the hardware filter 867 * accordingly. 868 */ 869 if (ifp->if_flags & IFF_RUNNING) 870 ste_set_filter(sc); 871 error = 0; 872 } 873 874 /* Try to get more packets going. */ 875 ste_start(ifp); 876 877 splx(s); 878 return (error); 879 } 880 881 /* 882 * ste_intr: 883 * 884 * Interrupt service routine. 885 */ 886 static int 887 ste_intr(void *arg) 888 { 889 struct ste_softc *sc = arg; 890 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 891 uint16_t isr; 892 uint8_t txstat; 893 int wantinit; 894 895 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 896 IS_InterruptStatus) == 0) 897 return (0); 898 899 for (wantinit = 0; wantinit == 0;) { 900 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 901 if ((isr & sc->sc_IntEnable) == 0) 902 break; 903 904 /* Receive interrupts. */ 905 if (isr & IE_RxDMAComplete) 906 ste_rxintr(sc); 907 908 /* Transmit interrupts. */ 909 if (isr & (IE_TxDMAComplete | IE_TxComplete)) 910 ste_txintr(sc); 911 912 /* Statistics overflow. */ 913 if (isr & IE_UpdateStats) 914 ste_stats_update(sc); 915 916 /* Transmission errors. */ 917 if (isr & IE_TxComplete) { 918 for (;;) { 919 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 920 STE_TxStatus); 921 if ((txstat & TS_TxComplete) == 0) 922 break; 923 if (txstat & TS_TxUnderrun) { 924 sc->sc_txthresh += 32; 925 if (sc->sc_txthresh > 0x1ffc) 926 sc->sc_txthresh = 0x1ffc; 927 printf("%s: transmit underrun, new " 928 "threshold: %d bytes\n", 929 device_xname(sc->sc_dev), 930 sc->sc_txthresh); 931 ste_reset(sc, AC_TxReset | AC_DMA | 932 AC_FIFO | AC_Network); 933 ste_setthresh(sc); 934 bus_space_write_1(sc->sc_st, sc->sc_sh, 935 STE_TxDMAPollPeriod, 127); 936 ste_txrestart(sc, 937 bus_space_read_1(sc->sc_st, 938 sc->sc_sh, STE_TxFrameId)); 939 } 940 if (txstat & TS_TxReleaseError) { 941 printf("%s: Tx FIFO release error\n", 942 device_xname(sc->sc_dev)); 943 wantinit = 1; 944 } 945 if (txstat & TS_MaxCollisions) { 946 printf("%s: excessive collisions\n", 947 device_xname(sc->sc_dev)); 948 wantinit = 1; 949 } 950 if (txstat & TS_TxStatusOverflow) { 951 printf("%s: status overflow\n", 952 device_xname(sc->sc_dev)); 953 wantinit = 1; 954 } 955 bus_space_write_2(sc->sc_st, sc->sc_sh, 956 STE_TxStatus, 0); 957 } 958 } 959 960 /* Host interface errors. */ 961 if (isr & IE_HostError) { 962 printf("%s: Host interface error\n", 963 device_xname(sc->sc_dev)); 964 wantinit = 1; 965 } 966 } 967 968 if (wantinit) 969 ste_init(ifp); 970 971 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 972 sc->sc_IntEnable); 973 974 /* Try to get more packets going. */ 975 if_schedule_deferred_start(ifp); 976 977 return (1); 978 } 979 980 /* 981 * ste_txintr: 982 * 983 * Helper; handle transmit interrupts. 984 */ 985 static void 986 ste_txintr(struct ste_softc *sc) 987 { 988 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 989 struct ste_descsoft *ds; 990 uint32_t control; 991 int i; 992 993 /* 994 * Go through our Tx list and free mbufs for those 995 * frames which have been transmitted. 996 */ 997 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 998 i = STE_NEXTTX(i), sc->sc_txpending--) { 999 ds = &sc->sc_txsoft[i]; 1000 1001 STE_CDTXSYNC(sc, i, 1002 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1003 1004 control = le32toh(sc->sc_txdescs[i].tfd_control); 1005 if ((control & TFD_TxDMAComplete) == 0) 1006 break; 1007 1008 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1009 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1010 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1011 m_freem(ds->ds_mbuf); 1012 ds->ds_mbuf = NULL; 1013 } 1014 1015 /* Update the dirty transmit buffer pointer. */ 1016 sc->sc_txdirty = i; 1017 1018 /* 1019 * If there are no more pending transmissions, cancel the watchdog 1020 * timer. 1021 */ 1022 if (sc->sc_txpending == 0) 1023 ifp->if_timer = 0; 1024 } 1025 1026 /* 1027 * ste_rxintr: 1028 * 1029 * Helper; handle receive interrupts. 1030 */ 1031 static void 1032 ste_rxintr(struct ste_softc *sc) 1033 { 1034 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1035 struct ste_descsoft *ds; 1036 struct mbuf *m; 1037 uint32_t status; 1038 int i, len; 1039 1040 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 1041 ds = &sc->sc_rxsoft[i]; 1042 1043 STE_CDRXSYNC(sc, i, 1044 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1045 1046 status = le32toh(sc->sc_rxdescs[i].rfd_status); 1047 1048 if ((status & RFD_RxDMAComplete) == 0) 1049 break; 1050 1051 /* 1052 * If the packet had an error, simply recycle the 1053 * buffer. Note, we count the error later in the 1054 * periodic stats update. 1055 */ 1056 if (status & RFD_RxFrameError) { 1057 STE_INIT_RXDESC(sc, i); 1058 continue; 1059 } 1060 1061 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1062 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1063 1064 /* 1065 * No errors; receive the packet. Note, we have 1066 * configured the chip to not include the CRC at 1067 * the end of the packet. 1068 */ 1069 len = RFD_RxDMAFrameLen(status); 1070 1071 /* 1072 * If the packet is small enough to fit in a 1073 * single header mbuf, allocate one and copy 1074 * the data into it. This greatly reduces 1075 * memory consumption when we receive lots 1076 * of small packets. 1077 * 1078 * Otherwise, we add a new buffer to the receive 1079 * chain. If this fails, we drop the packet and 1080 * recycle the old buffer. 1081 */ 1082 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1083 MGETHDR(m, M_DONTWAIT, MT_DATA); 1084 if (m == NULL) 1085 goto dropit; 1086 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1087 m->m_data += 2; 1088 memcpy(mtod(m, void *), 1089 mtod(ds->ds_mbuf, void *), len); 1090 STE_INIT_RXDESC(sc, i); 1091 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1092 ds->ds_dmamap->dm_mapsize, 1093 BUS_DMASYNC_PREREAD); 1094 } else { 1095 m = ds->ds_mbuf; 1096 if (ste_add_rxbuf(sc, i) != 0) { 1097 dropit: 1098 if_statinc(ifp, if_ierrors); 1099 STE_INIT_RXDESC(sc, i); 1100 bus_dmamap_sync(sc->sc_dmat, 1101 ds->ds_dmamap, 0, 1102 ds->ds_dmamap->dm_mapsize, 1103 BUS_DMASYNC_PREREAD); 1104 continue; 1105 } 1106 } 1107 1108 m_set_rcvif(m, ifp); 1109 m->m_pkthdr.len = m->m_len = len; 1110 1111 /* Pass it on. */ 1112 if_percpuq_enqueue(ifp->if_percpuq, m); 1113 } 1114 1115 /* Update the receive pointer. */ 1116 sc->sc_rxptr = i; 1117 } 1118 1119 /* 1120 * ste_tick: 1121 * 1122 * One second timer, used to tick the MII. 1123 */ 1124 static void 1125 ste_tick(void *arg) 1126 { 1127 struct ste_softc *sc = arg; 1128 int s; 1129 1130 s = splnet(); 1131 mii_tick(&sc->sc_mii); 1132 ste_stats_update(sc); 1133 splx(s); 1134 1135 callout_schedule(&sc->sc_tick_ch, hz); 1136 } 1137 1138 /* 1139 * ste_stats_update: 1140 * 1141 * Read the ST-201 statistics counters. 1142 */ 1143 static void 1144 ste_stats_update(struct ste_softc *sc) 1145 { 1146 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1147 bus_space_tag_t st = sc->sc_st; 1148 bus_space_handle_t sh = sc->sc_sh; 1149 1150 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1151 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1152 1153 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1154 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1155 1156 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1157 1158 if_statadd_ref(ifp, nsr, if_opackets, 1159 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK)); 1160 1161 (void) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1162 1163 if_statadd_ref(ifp, nsr, if_collisions, 1164 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1165 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1166 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames)); 1167 1168 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1169 1170 if_statadd_ref(ifp, nsr, if_ierrors, 1171 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors)); 1172 1173 if_statadd_ref(ifp, nsr, if_oerrors, 1174 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1175 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1176 bus_space_read_1(st, sh, STE_CarrierSenseErrors)); 1177 1178 IF_STAT_PUTREF(ifp); 1179 1180 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1181 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1182 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1183 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1184 } 1185 1186 /* 1187 * ste_reset: 1188 * 1189 * Perform a soft reset on the ST-201. 1190 */ 1191 static void 1192 ste_reset(struct ste_softc *sc, uint32_t rstbits) 1193 { 1194 uint32_t ac; 1195 int i; 1196 1197 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1198 1199 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1200 1201 delay(50000); 1202 1203 for (i = 0; i < STE_TIMEOUT; i++) { 1204 delay(1000); 1205 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1206 AC_ResetBusy) == 0) 1207 break; 1208 } 1209 1210 if (i == STE_TIMEOUT) 1211 printf("%s: reset failed to complete\n", 1212 device_xname(sc->sc_dev)); 1213 1214 delay(1000); 1215 } 1216 1217 /* 1218 * ste_setthresh: 1219 * 1220 * set the various transmit threshold registers 1221 */ 1222 static void 1223 ste_setthresh(struct ste_softc *sc) 1224 { 1225 /* set the TX threhold */ 1226 bus_space_write_2(sc->sc_st, sc->sc_sh, 1227 STE_TxStartThresh, sc->sc_txthresh); 1228 /* Urgent threshold: set to sc_txthresh / 2 */ 1229 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1230 sc->sc_txthresh >> 6); 1231 /* Burst threshold: use default value (256 bytes) */ 1232 } 1233 1234 /* 1235 * restart TX at the given frame ID in the transmitter ring 1236 */ 1237 static void 1238 ste_txrestart(struct ste_softc *sc, uint8_t id) 1239 { 1240 uint32_t control; 1241 1242 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1243 control = le32toh(sc->sc_txdescs[id].tfd_control); 1244 control &= ~TFD_TxDMAComplete; 1245 sc->sc_txdescs[id].tfd_control = htole32(control); 1246 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1247 1248 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1249 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1250 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1251 ste_dmahalt_wait(sc); 1252 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1253 STE_CDTXADDR(sc, id)); 1254 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1255 } 1256 1257 /* 1258 * ste_init: [ ifnet interface function ] 1259 * 1260 * Initialize the interface. Must be called at splnet(). 1261 */ 1262 static int 1263 ste_init(struct ifnet *ifp) 1264 { 1265 struct ste_softc *sc = ifp->if_softc; 1266 bus_space_tag_t st = sc->sc_st; 1267 bus_space_handle_t sh = sc->sc_sh; 1268 struct ste_descsoft *ds; 1269 int i, error = 0; 1270 1271 /* 1272 * Cancel any pending I/O. 1273 */ 1274 ste_stop(ifp, 0); 1275 1276 /* 1277 * Reset the chip to a known state. 1278 */ 1279 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1280 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1281 1282 /* 1283 * Initialize the transmit descriptor ring. 1284 */ 1285 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1286 sc->sc_txpending = 0; 1287 sc->sc_txdirty = 0; 1288 sc->sc_txlast = STE_NTXDESC - 1; 1289 1290 /* 1291 * Initialize the receive descriptor and receive job 1292 * descriptor rings. 1293 */ 1294 for (i = 0; i < STE_NRXDESC; i++) { 1295 ds = &sc->sc_rxsoft[i]; 1296 if (ds->ds_mbuf == NULL) { 1297 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1298 printf("%s: unable to allocate or map rx " 1299 "buffer %d, error = %d\n", 1300 device_xname(sc->sc_dev), i, error); 1301 /* 1302 * XXX Should attempt to run with fewer receive 1303 * XXX buffers instead of just failing. 1304 */ 1305 ste_rxdrain(sc); 1306 goto out; 1307 } 1308 } else 1309 STE_INIT_RXDESC(sc, i); 1310 } 1311 sc->sc_rxptr = 0; 1312 1313 /* Set the station address. */ 1314 for (i = 0; i < ETHER_ADDR_LEN; i++) 1315 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1316 CLLADDR(ifp->if_sadl)[i]); 1317 1318 /* Set up the receive filter. */ 1319 ste_set_filter(sc); 1320 1321 /* 1322 * Give the receive ring to the chip. 1323 */ 1324 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1325 STE_CDRXADDR(sc, sc->sc_rxptr)); 1326 1327 /* 1328 * We defer giving the transmit ring to the chip until we 1329 * transmit the first packet. 1330 */ 1331 1332 /* 1333 * Initialize the Tx auto-poll period. It's OK to make this number 1334 * large (127 is the max) -- we explicitly kick the transmit engine 1335 * when there's actually a packet. We are using auto-polling only 1336 * to make the interface to the transmit engine not suck. 1337 */ 1338 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1339 1340 /* ..and the Rx auto-poll period. */ 1341 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1342 1343 /* Initialize the Tx start threshold. */ 1344 ste_setthresh(sc); 1345 1346 /* Set the FIFO release threshold to 512 bytes. */ 1347 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1348 1349 /* Set maximum packet size for VLAN. */ 1350 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1351 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1352 else 1353 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1354 1355 /* 1356 * Initialize the interrupt mask. 1357 */ 1358 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1359 IE_TxDMAComplete | IE_RxDMAComplete; 1360 1361 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1362 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1363 1364 /* 1365 * Start the receive DMA engine. 1366 */ 1367 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1368 1369 /* 1370 * Initialize MacCtrl0 -- do it before setting the media, 1371 * as setting the media will actually program the register. 1372 */ 1373 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1374 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1375 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1376 1377 /* 1378 * Set the current media. 1379 */ 1380 if ((error = ether_mediachange(ifp)) != 0) 1381 goto out; 1382 1383 /* 1384 * Start the MAC. 1385 */ 1386 bus_space_write_2(st, sh, STE_MacCtrl1, 1387 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1388 1389 /* 1390 * Start the one second MII clock. 1391 */ 1392 callout_schedule(&sc->sc_tick_ch, hz); 1393 1394 /* 1395 * ...all done! 1396 */ 1397 ifp->if_flags |= IFF_RUNNING; 1398 1399 out: 1400 if (error) 1401 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1402 return (error); 1403 } 1404 1405 /* 1406 * ste_drain: 1407 * 1408 * Drain the receive queue. 1409 */ 1410 static void 1411 ste_rxdrain(struct ste_softc *sc) 1412 { 1413 struct ste_descsoft *ds; 1414 int i; 1415 1416 for (i = 0; i < STE_NRXDESC; i++) { 1417 ds = &sc->sc_rxsoft[i]; 1418 if (ds->ds_mbuf != NULL) { 1419 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1420 m_freem(ds->ds_mbuf); 1421 ds->ds_mbuf = NULL; 1422 } 1423 } 1424 } 1425 1426 /* 1427 * ste_stop: [ ifnet interface function ] 1428 * 1429 * Stop transmission on the interface. 1430 */ 1431 static void 1432 ste_stop(struct ifnet *ifp, int disable) 1433 { 1434 struct ste_softc *sc = ifp->if_softc; 1435 struct ste_descsoft *ds; 1436 int i; 1437 1438 /* 1439 * Stop the one second clock. 1440 */ 1441 callout_stop(&sc->sc_tick_ch); 1442 1443 /* Down the MII. */ 1444 mii_down(&sc->sc_mii); 1445 1446 /* 1447 * Disable interrupts. 1448 */ 1449 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1450 1451 /* 1452 * Stop receiver, transmitter, and stats update. 1453 */ 1454 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1455 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1456 1457 /* 1458 * Stop the transmit and receive DMA. 1459 */ 1460 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1461 DC_RxDMAHalt | DC_TxDMAHalt); 1462 ste_dmahalt_wait(sc); 1463 1464 /* 1465 * Release any queued transmit buffers. 1466 */ 1467 for (i = 0; i < STE_NTXDESC; i++) { 1468 ds = &sc->sc_txsoft[i]; 1469 if (ds->ds_mbuf != NULL) { 1470 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1471 m_freem(ds->ds_mbuf); 1472 ds->ds_mbuf = NULL; 1473 } 1474 } 1475 1476 /* 1477 * Mark the interface down and cancel the watchdog timer. 1478 */ 1479 ifp->if_flags &= ~IFF_RUNNING; 1480 ifp->if_timer = 0; 1481 1482 if (disable) 1483 ste_rxdrain(sc); 1484 } 1485 1486 static int 1487 ste_eeprom_wait(struct ste_softc *sc) 1488 { 1489 int i; 1490 1491 for (i = 0; i < STE_TIMEOUT; i++) { 1492 delay(1000); 1493 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1494 EC_EepromBusy) == 0) 1495 return (0); 1496 } 1497 return (1); 1498 } 1499 1500 /* 1501 * ste_read_eeprom: 1502 * 1503 * Read data from the serial EEPROM. 1504 */ 1505 static void 1506 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1507 { 1508 1509 if (ste_eeprom_wait(sc)) 1510 printf("%s: EEPROM failed to come ready\n", 1511 device_xname(sc->sc_dev)); 1512 1513 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1514 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1515 if (ste_eeprom_wait(sc)) 1516 printf("%s: EEPROM read timed out\n", 1517 device_xname(sc->sc_dev)); 1518 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1519 } 1520 1521 /* 1522 * ste_add_rxbuf: 1523 * 1524 * Add a receive buffer to the indicated descriptor. 1525 */ 1526 static int 1527 ste_add_rxbuf(struct ste_softc *sc, int idx) 1528 { 1529 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1530 struct mbuf *m; 1531 int error; 1532 1533 MGETHDR(m, M_DONTWAIT, MT_DATA); 1534 if (m == NULL) 1535 return (ENOBUFS); 1536 1537 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1538 MCLGET(m, M_DONTWAIT); 1539 if ((m->m_flags & M_EXT) == 0) { 1540 m_freem(m); 1541 return (ENOBUFS); 1542 } 1543 1544 if (ds->ds_mbuf != NULL) 1545 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1546 1547 ds->ds_mbuf = m; 1548 1549 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1550 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1551 BUS_DMA_READ | BUS_DMA_NOWAIT); 1552 if (error) { 1553 printf("%s: can't load rx DMA map %d, error = %d\n", 1554 device_xname(sc->sc_dev), idx, error); 1555 panic("ste_add_rxbuf"); /* XXX */ 1556 } 1557 1558 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1559 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1560 1561 STE_INIT_RXDESC(sc, idx); 1562 1563 return (0); 1564 } 1565 1566 /* 1567 * ste_set_filter: 1568 * 1569 * Set up the receive filter. 1570 */ 1571 static void 1572 ste_set_filter(struct ste_softc *sc) 1573 { 1574 struct ethercom *ec = &sc->sc_ethercom; 1575 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1576 struct ether_multi *enm; 1577 struct ether_multistep step; 1578 uint32_t crc; 1579 uint16_t mchash[4]; 1580 1581 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1582 if (ifp->if_flags & IFF_BROADCAST) 1583 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1584 1585 if (ifp->if_flags & IFF_PROMISC) { 1586 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1587 goto allmulti; 1588 } 1589 1590 /* 1591 * Set up the multicast address filter by passing all multicast 1592 * addresses through a CRC generator, and then using the low-order 1593 * 6 bits as an index into the 64 bit multicast hash table. The 1594 * high order bits select the register, while the rest of the bits 1595 * select the bit within the register. 1596 */ 1597 1598 memset(mchash, 0, sizeof(mchash)); 1599 1600 ETHER_LOCK(ec); 1601 ETHER_FIRST_MULTI(step, ec, enm); 1602 if (enm == NULL) { 1603 ETHER_UNLOCK(ec); 1604 goto done; 1605 } 1606 1607 while (enm != NULL) { 1608 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1609 /* 1610 * We must listen to a range of multicast addresses. 1611 * For now, just accept all multicasts, rather than 1612 * trying to set only those filter bits needed to match 1613 * the range. (At this time, the only use of address 1614 * ranges is for IP multicast routing, for which the 1615 * range is big enough to require all bits set.) 1616 */ 1617 ETHER_UNLOCK(ec); 1618 goto allmulti; 1619 } 1620 1621 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1622 1623 /* Just want the 6 least significant bits. */ 1624 crc &= 0x3f; 1625 1626 /* Set the corresponding bit in the hash table. */ 1627 mchash[crc >> 4] |= 1 << (crc & 0xf); 1628 1629 ETHER_NEXT_MULTI(step, enm); 1630 } 1631 ETHER_UNLOCK(ec); 1632 1633 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1634 1635 ifp->if_flags &= ~IFF_ALLMULTI; 1636 goto done; 1637 1638 allmulti: 1639 ifp->if_flags |= IFF_ALLMULTI; 1640 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1641 1642 done: 1643 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1644 /* 1645 * Program the multicast hash table. 1646 */ 1647 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1648 mchash[0]); 1649 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1650 mchash[1]); 1651 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1652 mchash[2]); 1653 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1654 mchash[3]); 1655 } 1656 1657 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1658 sc->sc_ReceiveMode); 1659 } 1660 1661 /* 1662 * ste_mii_readreg: [mii interface function] 1663 * 1664 * Read a PHY register on the MII of the ST-201. 1665 */ 1666 static int 1667 ste_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1668 { 1669 struct ste_softc *sc = device_private(self); 1670 1671 if (phy == 0 && !sc->sc_enable_phy0) 1672 return EIO; 1673 1674 return mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg, val); 1675 } 1676 1677 /* 1678 * ste_mii_writereg: [mii interface function] 1679 * 1680 * Write a PHY register on the MII of the ST-201. 1681 */ 1682 static int 1683 ste_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1684 { 1685 struct ste_softc *sc = device_private(self); 1686 1687 if (phy == 0 && !sc->sc_enable_phy0) 1688 return EIO; 1689 1690 return mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1691 } 1692 1693 /* 1694 * ste_mii_statchg: [mii interface function] 1695 * 1696 * Callback from MII layer when media changes. 1697 */ 1698 static void 1699 ste_mii_statchg(struct ifnet *ifp) 1700 { 1701 struct ste_softc *sc = ifp->if_softc; 1702 1703 if (sc->sc_mii.mii_media_active & IFM_FDX) 1704 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1705 else 1706 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1707 1708 /* XXX 802.1x flow-control? */ 1709 1710 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1711 } 1712 1713 /* 1714 * ste_mii_bitbang_read: [mii bit-bang interface function] 1715 * 1716 * Read the MII serial port for the MII bit-bang module. 1717 */ 1718 static uint32_t 1719 ste_mii_bitbang_read(device_t self) 1720 { 1721 struct ste_softc *sc = device_private(self); 1722 1723 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1724 } 1725 1726 /* 1727 * ste_mii_bitbang_write: [mii big-bang interface function] 1728 * 1729 * Write the MII serial port for the MII bit-bang module. 1730 */ 1731 static void 1732 ste_mii_bitbang_write(device_t self, uint32_t val) 1733 { 1734 struct ste_softc *sc = device_private(self); 1735 1736 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1737 } 1738
Indexes created Tue Sep 30 17:09:57 GMT 2025