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Searched defs:store_rd (Results 1 - 2 of 2) sorted by relevancy

/src/external/gpl3/gdb.old/dist/sim/riscv/
sim-main.c	70 store_rd (SIM_CPU cpu, int rd, unsigned_word val) 192 store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]); 198 store_rd (cpu, rd, 204 store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm); 210 store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm)); 215 store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2]); 220 store_rd (cpu, rd, riscv_cpu->regs[rs1] & i_imm); 225 store_rd (cpu, rd, riscv_cpu->regs[rs1] \| riscv_cpu->regs[rs2]); 230 store_rd (cpu, rd, riscv_cpu->regs[rs1] \| i_imm); 235 store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ riscv_cpu->regs[rs2]) 68 store_rd (SIM_CPU cpu, int rd, unsigned_word val) function [all...]
/src/external/gpl3/gdb/dist/sim/riscv/
sim-main.c	70 store_rd (SIM_CPU cpu, int rd, unsigned_word val) 192 store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]); 198 store_rd (cpu, rd, 204 store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm); 210 store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm)); 215 store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2]); 220 store_rd (cpu, rd, riscv_cpu->regs[rs1] & i_imm); 225 store_rd (cpu, rd, riscv_cpu->regs[rs1] \| riscv_cpu->regs[rs2]); 230 store_rd (cpu, rd, riscv_cpu->regs[rs1] \| i_imm); 235 store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ riscv_cpu->regs[rs2]) 68 store_rd (SIM_CPU cpu, int rd, unsigned_word val) function [all...]

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