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      1 // SPDX-License-Identifier: GPL-2.0
      2 /*
      3  * Samsung's Exynos4210 SoC device tree source
      4  *
      5  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
      6  *		http://www.samsung.com
      7  * Copyright (c) 2010-2011 Linaro Ltd.
      8  *		www.linaro.org
      9  *
     10  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
     11  * based board files can include this file and provide values for board specific
     12  * bindings.
     13  *
     14  * Note: This file does not include device nodes for all the controllers in
     15  * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
     16  * nodes can be added to this file.
     17  */
     18 
     19 #include "exynos4.dtsi"
     20 #include "exynos4-cpu-thermal.dtsi"
     21 
     22 / {
     23 	compatible = "samsung,exynos4210", "samsung,exynos4";
     24 
     25 	aliases {
     26 		pinctrl0 = &pinctrl_0;
     27 		pinctrl1 = &pinctrl_1;
     28 		pinctrl2 = &pinctrl_2;
     29 	};
     30 
     31 	cpus {
     32 		#address-cells = <1>;
     33 		#size-cells = <0>;
     34 
     35 		cpu-map {
     36 			cluster0 {
     37 				core0 {
     38 					cpu = <&cpu0>;
     39 				};
     40 				core1 {
     41 					cpu = <&cpu1>;
     42 				};
     43 			};
     44 		};
     45 
     46 		cpu0: cpu@900 {
     47 			device_type = "cpu";
     48 			compatible = "arm,cortex-a9";
     49 			reg = <0x900>;
     50 			clocks = <&clock CLK_ARM_CLK>;
     51 			clock-names = "cpu";
     52 			clock-latency = <160000>;
     53 
     54 			operating-points = <
     55 				1200000 1250000
     56 				1000000 1150000
     57 				800000	1075000
     58 				500000	975000
     59 				400000	975000
     60 				200000	950000
     61 			>;
     62 			#cooling-cells = <2>; /* min followed by max */
     63 		};
     64 
     65 		cpu1: cpu@901 {
     66 			device_type = "cpu";
     67 			compatible = "arm,cortex-a9";
     68 			reg = <0x901>;
     69 			clocks = <&clock CLK_ARM_CLK>;
     70 			clock-names = "cpu";
     71 			clock-latency = <160000>;
     72 
     73 			operating-points = <
     74 				1200000 1250000
     75 				1000000 1150000
     76 				800000	1075000
     77 				500000	975000
     78 				400000	975000
     79 				200000	950000
     80 			>;
     81 			#cooling-cells = <2>; /* min followed by max */
     82 		};
     83 	};
     84 
     85 	soc: soc {
     86 		sysram: sram@2020000 {
     87 			compatible = "mmio-sram";
     88 			reg = <0x02020000 0x20000>;
     89 			#address-cells = <1>;
     90 			#size-cells = <1>;
     91 			ranges = <0 0x02020000 0x20000>;
     92 
     93 			smp-sram@0 {
     94 				compatible = "samsung,exynos4210-sysram";
     95 				reg = <0x0 0x1000>;
     96 			};
     97 
     98 			smp-sram@1f000 {
     99 				compatible = "samsung,exynos4210-sysram-ns";
    100 				reg = <0x1f000 0x1000>;
    101 			};
    102 		};
    103 
    104 		pd_lcd1: power-domain@10023ca0 {
    105 			compatible = "samsung,exynos4210-pd";
    106 			reg = <0x10023CA0 0x20>;
    107 			#power-domain-cells = <0>;
    108 			label = "LCD1";
    109 		};
    110 
    111 		l2c: cache-controller@10502000 {
    112 			compatible = "arm,pl310-cache";
    113 			reg = <0x10502000 0x1000>;
    114 			cache-unified;
    115 			cache-level = <2>;
    116 			prefetch-data = <1>;
    117 			prefetch-instr = <1>;
    118 			arm,tag-latency = <2 2 1>;
    119 			arm,data-latency = <2 2 1>;
    120 		};
    121 
    122 		mct: timer@10050000 {
    123 			compatible = "samsung,exynos4210-mct";
    124 			reg = <0x10050000 0x800>;
    125 			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
    126 			clock-names = "fin_pll", "mct";
    127 			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
    128 					      <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
    129 					      <&combiner 12 6>,
    130 					      <&combiner 12 7>,
    131 					      <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
    132 					      <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
    133 		};
    134 
    135 		watchdog: watchdog@10060000 {
    136 			compatible = "samsung,s3c6410-wdt";
    137 			reg = <0x10060000 0x100>;
    138 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
    139 			clocks = <&clock CLK_WDT>;
    140 			clock-names = "watchdog";
    141 		};
    142 
    143 		clock: clock-controller@10030000 {
    144 			compatible = "samsung,exynos4210-clock";
    145 			reg = <0x10030000 0x20000>;
    146 			#clock-cells = <1>;
    147 		};
    148 
    149 		pinctrl_0: pinctrl@11400000 {
    150 			compatible = "samsung,exynos4210-pinctrl";
    151 			reg = <0x11400000 0x1000>;
    152 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
    153 		};
    154 
    155 		pinctrl_1: pinctrl@11000000 {
    156 			compatible = "samsung,exynos4210-pinctrl";
    157 			reg = <0x11000000 0x1000>;
    158 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
    159 
    160 			wakup_eint: wakeup-interrupt-controller {
    161 				compatible = "samsung,exynos4210-wakeup-eint";
    162 				interrupt-parent = <&gic>;
    163 				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    164 			};
    165 		};
    166 
    167 		pinctrl_2: pinctrl@3860000 {
    168 			compatible = "samsung,exynos4210-pinctrl";
    169 			reg = <0x03860000 0x1000>;
    170 		};
    171 
    172 		g2d: g2d@12800000 {
    173 			compatible = "samsung,s5pv210-g2d";
    174 			reg = <0x12800000 0x1000>;
    175 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
    176 			clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
    177 			clock-names = "sclk_fimg2d", "fimg2d";
    178 			power-domains = <&pd_lcd0>;
    179 			iommus = <&sysmmu_g2d>;
    180 		};
    181 
    182 		ppmu_acp: ppmu@10ae0000 {
    183 			compatible = "samsung,exynos-ppmu";
    184 			reg = <0x10ae0000 0x2000>;
    185 			status = "disabled";
    186 		};
    187 
    188 		ppmu_lcd1: ppmu@12240000 {
    189 			compatible = "samsung,exynos-ppmu";
    190 			reg = <0x12240000 0x2000>;
    191 			clocks = <&clock CLK_PPMULCD1>;
    192 			clock-names = "ppmu";
    193 			status = "disabled";
    194 		};
    195 
    196 		sysmmu_g2d: sysmmu@12a20000 {
    197 			compatible = "samsung,exynos-sysmmu";
    198 			reg = <0x12A20000 0x1000>;
    199 			interrupt-parent = <&combiner>;
    200 			interrupts = <4 7>;
    201 			clock-names = "sysmmu", "master";
    202 			clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
    203 			power-domains = <&pd_lcd0>;
    204 			#iommu-cells = <0>;
    205 		};
    206 
    207 		sysmmu_fimd1: sysmmu@12220000 {
    208 			compatible = "samsung,exynos-sysmmu";
    209 			interrupt-parent = <&combiner>;
    210 			reg = <0x12220000 0x1000>;
    211 			interrupts = <5 3>;
    212 			clock-names = "sysmmu", "master";
    213 			clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
    214 			power-domains = <&pd_lcd1>;
    215 			#iommu-cells = <0>;
    216 		};
    217 
    218 		bus_dmc: bus-dmc {
    219 			compatible = "samsung,exynos-bus";
    220 			clocks = <&clock CLK_DIV_DMC>;
    221 			clock-names = "bus";
    222 			operating-points-v2 = <&bus_dmc_opp_table>;
    223 			status = "disabled";
    224 		};
    225 
    226 		bus_acp: bus-acp {
    227 			compatible = "samsung,exynos-bus";
    228 			clocks = <&clock CLK_DIV_ACP>;
    229 			clock-names = "bus";
    230 			operating-points-v2 = <&bus_acp_opp_table>;
    231 			status = "disabled";
    232 		};
    233 
    234 		bus_peri: bus-peri {
    235 			compatible = "samsung,exynos-bus";
    236 			clocks = <&clock CLK_ACLK100>;
    237 			clock-names = "bus";
    238 			operating-points-v2 = <&bus_peri_opp_table>;
    239 			status = "disabled";
    240 		};
    241 
    242 		bus_fsys: bus-fsys {
    243 			compatible = "samsung,exynos-bus";
    244 			clocks = <&clock CLK_ACLK133>;
    245 			clock-names = "bus";
    246 			operating-points-v2 = <&bus_fsys_opp_table>;
    247 			status = "disabled";
    248 		};
    249 
    250 		bus_display: bus-display {
    251 			compatible = "samsung,exynos-bus";
    252 			clocks = <&clock CLK_ACLK160>;
    253 			clock-names = "bus";
    254 			operating-points-v2 = <&bus_display_opp_table>;
    255 			status = "disabled";
    256 		};
    257 
    258 		bus_lcd0: bus-lcd0 {
    259 			compatible = "samsung,exynos-bus";
    260 			clocks = <&clock CLK_ACLK200>;
    261 			clock-names = "bus";
    262 			operating-points-v2 = <&bus_leftbus_opp_table>;
    263 			status = "disabled";
    264 		};
    265 
    266 		bus_leftbus: bus-leftbus {
    267 			compatible = "samsung,exynos-bus";
    268 			clocks = <&clock CLK_DIV_GDL>;
    269 			clock-names = "bus";
    270 			operating-points-v2 = <&bus_leftbus_opp_table>;
    271 			status = "disabled";
    272 		};
    273 
    274 		bus_rightbus: bus-rightbus {
    275 			compatible = "samsung,exynos-bus";
    276 			clocks = <&clock CLK_DIV_GDR>;
    277 			clock-names = "bus";
    278 			operating-points-v2 = <&bus_leftbus_opp_table>;
    279 			status = "disabled";
    280 		};
    281 
    282 		bus_mfc: bus-mfc {
    283 			compatible = "samsung,exynos-bus";
    284 			clocks = <&clock CLK_SCLK_MFC>;
    285 			clock-names = "bus";
    286 			operating-points-v2 = <&bus_leftbus_opp_table>;
    287 			status = "disabled";
    288 		};
    289 
    290 		bus_dmc_opp_table: opp-table1 {
    291 			compatible = "operating-points-v2";
    292 			opp-shared;
    293 
    294 			opp-134000000 {
    295 				opp-hz = /bits/ 64 <134000000>;
    296 				opp-microvolt = <1025000>;
    297 			};
    298 			opp-267000000 {
    299 				opp-hz = /bits/ 64 <267000000>;
    300 				opp-microvolt = <1050000>;
    301 			};
    302 			opp-400000000 {
    303 				opp-hz = /bits/ 64 <400000000>;
    304 				opp-microvolt = <1150000>;
    305 				opp-suspend;
    306 			};
    307 		};
    308 
    309 		bus_acp_opp_table: opp-table2 {
    310 			compatible = "operating-points-v2";
    311 			opp-shared;
    312 
    313 			opp-134000000 {
    314 				opp-hz = /bits/ 64 <134000000>;
    315 			};
    316 			opp-160000000 {
    317 				opp-hz = /bits/ 64 <160000000>;
    318 			};
    319 			opp-200000000 {
    320 				opp-hz = /bits/ 64 <200000000>;
    321 			};
    322 		};
    323 
    324 		bus_peri_opp_table: opp-table3 {
    325 			compatible = "operating-points-v2";
    326 			opp-shared;
    327 
    328 			opp-5000000 {
    329 				opp-hz = /bits/ 64 <5000000>;
    330 			};
    331 			opp-100000000 {
    332 				opp-hz = /bits/ 64 <100000000>;
    333 			};
    334 		};
    335 
    336 		bus_fsys_opp_table: opp-table4 {
    337 			compatible = "operating-points-v2";
    338 			opp-shared;
    339 
    340 			opp-10000000 {
    341 				opp-hz = /bits/ 64 <10000000>;
    342 			};
    343 			opp-134000000 {
    344 				opp-hz = /bits/ 64 <134000000>;
    345 			};
    346 		};
    347 
    348 		bus_display_opp_table: opp-table5 {
    349 			compatible = "operating-points-v2";
    350 			opp-shared;
    351 
    352 			opp-100000000 {
    353 				opp-hz = /bits/ 64 <100000000>;
    354 			};
    355 			opp-134000000 {
    356 				opp-hz = /bits/ 64 <134000000>;
    357 			};
    358 			opp-160000000 {
    359 				opp-hz = /bits/ 64 <160000000>;
    360 			};
    361 		};
    362 
    363 		bus_leftbus_opp_table: opp-table6 {
    364 			compatible = "operating-points-v2";
    365 			opp-shared;
    366 
    367 			opp-100000000 {
    368 				opp-hz = /bits/ 64 <100000000>;
    369 			};
    370 			opp-160000000 {
    371 				opp-hz = /bits/ 64 <160000000>;
    372 			};
    373 			opp-200000000 {
    374 				opp-hz = /bits/ 64 <200000000>;
    375 				opp-suspend;
    376 			};
    377 		};
    378 	};
    379 };
    380 
    381 &cpu_alert0 {
    382 	temperature = <85000>; /* millicelsius */
    383 };
    384 
    385 &cpu_alert1 {
    386 	temperature = <100000>; /* millicelsius */
    387 };
    388 
    389 &cpu_alert2 {
    390 	temperature = <110000>; /* millicelsius */
    391 };
    392 
    393 &cpu_thermal {
    394 	polling-delay-passive = <0>;
    395 	polling-delay = <0>;
    396 	thermal-sensors = <&tmu 0>;
    397 };
    398 
    399 &gic {
    400 	cpu-offset = <0x8000>;
    401 };
    402 
    403 &camera {
    404 	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
    405 		 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
    406 	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
    407 };
    408 
    409 &combiner {
    410 	samsung,combiner-nr = <16>;
    411 	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
    412 		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
    413 		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
    414 		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
    415 		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
    416 		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
    417 		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
    418 		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
    419 		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
    420 		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
    421 		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
    422 		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
    423 		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
    424 		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
    425 		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
    426 		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    427 };
    428 
    429 &fimc_0 {
    430 	samsung,pix-limits = <4224 8192 1920 4224>;
    431 	samsung,mainscaler-ext;
    432 	samsung,cam-if;
    433 };
    434 
    435 &fimc_1 {
    436 	samsung,pix-limits = <4224 8192 1920 4224>;
    437 	samsung,mainscaler-ext;
    438 	samsung,cam-if;
    439 };
    440 
    441 &fimc_2 {
    442 	samsung,pix-limits = <4224 8192 1920 4224>;
    443 	samsung,mainscaler-ext;
    444 	samsung,lcd-wb;
    445 };
    446 
    447 &fimc_3 {
    448 	samsung,pix-limits = <1920 8192 1366 1920>;
    449 	samsung,rotators = <0>;
    450 	samsung,mainscaler-ext;
    451 	samsung,lcd-wb;
    452 };
    453 
    454 &gpu {
    455 	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
    456 		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
    457 		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
    458 		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
    459 		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
    460 		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
    461 		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
    462 		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
    463 		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
    464 		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
    465 	interrupt-names = "gp",
    466 			  "gpmmu",
    467 			  "pp0",
    468 			  "ppmmu0",
    469 			  "pp1",
    470 			  "ppmmu1",
    471 			  "pp2",
    472 			  "ppmmu2",
    473 			  "pp3",
    474 			  "ppmmu3";
    475 	operating-points-v2 = <&gpu_opp_table>;
    476 
    477 	gpu_opp_table: opp-table {
    478 		compatible = "operating-points-v2";
    479 
    480 		opp-160000000 {
    481 			opp-hz = /bits/ 64 <160000000>;
    482 			opp-microvolt = <950000>;
    483 		};
    484 		opp-267000000 {
    485 			opp-hz = /bits/ 64 <267000000>;
    486 			opp-microvolt = <1050000>;
    487 		};
    488 	};
    489 };
    490 
    491 &mdma1 {
    492 	power-domains = <&pd_lcd0>;
    493 };
    494 
    495 &mixer {
    496 	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
    497 		      "sclk_mixer";
    498 	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
    499 		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
    500 		 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
    501 };
    502 
    503 &pmu {
    504 	interrupts = <2 2>, <3 2>;
    505 	interrupt-affinity = <&cpu0>, <&cpu1>;
    506 	status = "okay";
    507 };
    508 
    509 &pmu_system_controller {
    510 	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
    511 			"clkout4", "clkout8", "clkout9";
    512 	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
    513 		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
    514 		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
    515 	#clock-cells = <1>;
    516 };
    517 
    518 &rotator {
    519 	power-domains = <&pd_lcd0>;
    520 };
    521 
    522 &sysmmu_rotator {
    523 	power-domains = <&pd_lcd0>;
    524 };
    525 
    526 &tmu {
    527 	compatible = "samsung,exynos4210-tmu";
    528 	clocks = <&clock CLK_TMU_APBIF>;
    529 	clock-names = "tmu_apbif";
    530 	samsung,tmu_gain = <15>;
    531 	samsung,tmu_reference_voltage = <7>;
    532 };
    533 
    534 #include "exynos4210-pinctrl.dtsi"
    535