1 /* $NetBSD: exynos_platform.c,v 1.41 2025/09/06 21:02:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_arm_debug.h" 30 #include "opt_console.h" 31 #include "opt_exynos.h" 32 #include "opt_multiprocessor.h" 33 #include "opt_console.h" 34 35 #include "ukbd.h" 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.41 2025/09/06 21:02:41 thorpej Exp $"); 39 40 #define EXYNOS_CORE_VBASE KERNEL_IO_VBASE 41 42 /* 43 * Booting a CA7 core on Exynos5422 is currently broken, disable starting CA7 secondaries. 44 */ 45 #define EXYNOS5422_DISABLE_CA7_CLUSTER 46 47 #include <sys/param.h> 48 #include <sys/bus.h> 49 #include <sys/cpu.h> 50 #include <sys/device.h> 51 #include <sys/termios.h> 52 53 #include <dev/fdt/fdtvar.h> 54 #include <dev/fdt/fdt_platform.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <machine/bootconfig.h> 59 #include <arm/cpufunc.h> 60 61 #include <arm/samsung/exynos_reg.h> 62 #include <arm/samsung/exynos_var.h> 63 #include <arm/samsung/mct_var.h> 64 #include <arm/samsung/sscom_reg.h> 65 66 #include <evbarm/fdt/platform.h> 67 #include <evbarm/fdt/machdep.h> 68 69 #include <arm/fdt/arm_fdtvar.h> 70 71 #include <libfdt.h> 72 73 void exynos_platform_early_putchar(char); 74 75 #define EXYNOS5800_PMU_BASE 0x10040000 76 #define EXYNOS5800_PMU_SIZE 0x20000 77 #define EXYNOS5800_PMU_SWRESET 0x0400 78 #define EXYNOS5800_PMU_KFC_ETM_RESET(n) __BIT(20 + (n)) 79 #define EXYNOS5800_PMU_KFC_CORE_RESET(n) __BIT(8 + (n)) 80 #define EXYNOS5800_PMU_SPARE2 0x0908 81 #define EXYNOS5800_PMU_SPARE3 0x090c 82 #define EXYNOS5800_PMU_SWRESET_KFC_SEL 0x3 83 #define EXYNOS5800_PMU_CORE_CONFIG(n) (0x2000 + 0x80 * (n)) 84 #define EXYNOS5800_PMU_CORE_STATUS(n) (0x2004 + 0x80 * (n)) 85 #define EXYNOS5800_PMU_CORE_POWER_EN 0x3 86 #define EXYNOS5800_PMU_COMMON_CONFIG(n) (0x2500 + 0x80 * (n)) 87 #define EXYNOS5800_PMU_COMMON_POWER_EN 0x3 88 #define EXYNOS5800_PMU_COMMON_OPTION(n) (0x2508 + 0x80 * (n)) 89 #define EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE __BIT(30) 90 #define EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE __BIT(29) 91 #define EXYNOS5800_PMU_AUTO_CORE_DOWN __BIT(9) 92 93 #define EXYNOS5800_SYSRAM_BASE 0x02073000 94 #define EXYNOS5800_SYSRAM_SIZE 0x1000 95 #define EXYNOS5800_SYSRAM_HOTPLUG 0x001c 96 97 static int 98 exynos5800_mpstart(void) 99 { 100 int ret = 0; 101 #if defined(MULTIPROCESSOR) 102 bus_space_tag_t bst = &armv7_generic_bs_tag; 103 bus_space_handle_t pmu_bsh, sysram_bsh; 104 uint64_t mpidr, bp_mpidr; 105 uint32_t val, started = 0; 106 u_int cpuindex, n; 107 int child; 108 109 bus_space_map(bst, EXYNOS5800_PMU_BASE, EXYNOS5800_PMU_SIZE, 0, &pmu_bsh); 110 bus_space_map(bst, EXYNOS5800_SYSRAM_BASE, EXYNOS5800_SYSRAM_SIZE, 0, &sysram_bsh); 111 112 const int cpus = OF_finddevice("/cpus"); 113 if (cpus == -1) { 114 aprint_error("%s: no /cpus node found\n", __func__); 115 return ret; 116 } 117 118 /* MPIDR affinity levels of boot processor. */ 119 bp_mpidr = cpu_mpidr_aff_read(); 120 121 /* Setup KFC reset */ 122 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE3, EXYNOS5800_PMU_SWRESET_KFC_SEL); 123 124 const uint32_t option = EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE | 125 EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE | 126 EXYNOS5800_PMU_AUTO_CORE_DOWN; 127 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0)); 128 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0), val | option); 129 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1)); 130 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1), val | option); 131 132 bus_space_write_4(bst, sysram_bsh, EXYNOS5800_SYSRAM_HOTPLUG, KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 133 dsb(sy); 134 135 /* Power on clusters */ 136 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(0), 137 EXYNOS5800_PMU_COMMON_POWER_EN); 138 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(1), 139 EXYNOS5800_PMU_COMMON_POWER_EN); 140 141 /* Boot APs */ 142 cpuindex = 1; 143 for (child = OF_child(cpus); child; child = OF_peer(child)) { 144 if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0) 145 continue; 146 147 if (mpidr == bp_mpidr) 148 continue; /* BP already started */ 149 150 const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1); 151 const u_int aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0); 152 const u_int cpu = cluster * 4 + aff0; 153 154 #if defined(EXYNOS5422_DISABLE_CA7_CLUSTER) 155 if (cluster == 1) 156 continue; 157 #endif 158 159 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu)); 160 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_CONFIG(cpu), 161 EXYNOS5800_PMU_CORE_POWER_EN); 162 163 for (n = 0x100000; n > 0; n--) { 164 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu)); 165 if ((val & EXYNOS5800_PMU_CORE_POWER_EN) == EXYNOS5800_PMU_CORE_POWER_EN) { 166 started |= __BIT(cpuindex); 167 break; 168 } 169 } 170 if (n == 0) 171 aprint_error("cpu%d: WARNING: AP failed to power on\n", cpuindex); 172 173 if (cluster == 1 && __SHIFTOUT(bp_mpidr, MPIDR_AFF1) == 1) { 174 while (bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE2) == 0) 175 ; 176 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SWRESET, 177 EXYNOS5800_PMU_KFC_CORE_RESET(aff0) | 178 EXYNOS5800_PMU_KFC_ETM_RESET(aff0)); 179 } 180 181 /* Wait for AP to start */ 182 for (n = 0x100000; n > 0; n--) { 183 if (cpu_hatched_p(cpuindex)) 184 break; 185 } 186 if (n == 0) { 187 ret++; 188 aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex); 189 } 190 191 cpuindex++; 192 } 193 194 bus_space_unmap(bst, sysram_bsh, EXYNOS5800_SYSRAM_SIZE); 195 bus_space_unmap(bst, pmu_bsh, EXYNOS5800_PMU_SIZE); 196 #endif 197 return ret; 198 } 199 200 static struct device_compatible_entry mp_compat_data[] = { 201 { .compat = "samsung,exynos5800", .data = exynos5800_mpstart }, 202 DEVICE_COMPAT_EOL 203 }; 204 205 static int 206 exynos_platform_mpstart(void) 207 { 208 209 int (*mp_start)(void) = NULL; 210 211 const struct device_compatible_entry *cd = 212 of_compatible_lookup(OF_finddevice("/"), mp_compat_data); 213 if (cd) 214 mp_start = cd->data; 215 216 if (mp_start) 217 return mp_start(); 218 219 return 0; 220 } 221 222 static void 223 exynos_platform_init_attach_args(struct fdt_attach_args *faa) 224 { 225 extern struct bus_space armv7_generic_bs_tag; 226 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 227 228 faa->faa_bst = &armv7_generic_bs_tag; 229 faa->faa_dmat = &arm_generic_dma_tag; 230 } 231 232 void __noasan 233 exynos_platform_early_putchar(char c) 234 { 235 #ifdef CONSADDR 236 #define CONSADDR_VA (CONSADDR - EXYNOS_CORE_PBASE + EXYNOS_CORE_VBASE) 237 238 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 239 (volatile uint32_t *)CONSADDR_VA : 240 (volatile uint32_t *)CONSADDR; 241 242 while ((uartaddr[SSCOM_UFSTAT / 4] & UFSTAT_TXFULL) != 0) 243 ; 244 245 uartaddr[SSCOM_UTXH / 4] = c; 246 #endif 247 } 248 249 static void 250 exynos_platform_device_register(device_t self, void *aux) 251 { 252 exynos_device_register(self, aux); 253 } 254 255 static void 256 exynos5_platform_reset(void) 257 { 258 bus_space_tag_t bst = &armv7_generic_bs_tag; 259 bus_space_handle_t bsh; 260 261 bus_space_map(bst, EXYNOS5800_PMU_BASE + EXYNOS5800_PMU_SWRESET, 4, 0, &bsh); 262 bus_space_write_4(bst, bsh, 0, 1); 263 } 264 265 static u_int 266 exynos_platform_uart_freq(void) 267 { 268 return EXYNOS_UART_FREQ; 269 } 270 271 272 #if defined(SOC_EXYNOS4) 273 static const struct pmap_devmap * 274 exynos4_platform_devmap(void) 275 { 276 static const struct pmap_devmap devmap[] = { 277 DEVMAP_ENTRY(EXYNOS_CORE_VBASE, 278 EXYNOS_CORE_PBASE, 279 EXYNOS4_CORE_SIZE), 280 DEVMAP_ENTRY(EXYNOS4_AUDIOCORE_VBASE, 281 EXYNOS4_AUDIOCORE_PBASE, 282 EXYNOS4_AUDIOCORE_SIZE), 283 DEVMAP_ENTRY_END 284 }; 285 286 return devmap; 287 } 288 289 static void 290 exynos4_platform_bootstrap(void) 291 { 292 293 exynos_bootstrap(4); 294 295 #if defined(MULTIPROCESSOR) 296 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU); 297 #endif 298 } 299 300 static const struct fdt_platform exynos4_platform = { 301 .fp_devmap = exynos4_platform_devmap, 302 // .fp_mpstart = exynos4_mpstart, 303 .fp_bootstrap = exynos4_platform_bootstrap, 304 .fp_init_attach_args = exynos_platform_init_attach_args, 305 .fp_device_register = exynos_platform_device_register, 306 .fp_reset = exynos5_platform_reset, 307 .fp_delay = mct_delay, 308 .fp_uart_freq = exynos_platform_uart_freq, 309 }; 310 311 FDT_PLATFORM(exynos4, "samsung,exynos4", &exynos4_platform); 312 #endif 313 314 315 #if defined(SOC_EXYNOS5) 316 static const struct pmap_devmap * 317 exynos5_platform_devmap(void) 318 { 319 static const struct pmap_devmap devmap[] = { 320 DEVMAP_ENTRY(EXYNOS_CORE_VBASE, 321 EXYNOS_CORE_PBASE, 322 EXYNOS5_CORE_SIZE), 323 DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE, 324 EXYNOS5_AUDIOCORE_PBASE, 325 EXYNOS5_AUDIOCORE_SIZE), 326 DEVMAP_ENTRY(EXYNOS5_SYSRAM_VBASE, 327 EXYNOS5_SYSRAM_PBASE, 328 EXYNOS5_SYSRAM_SIZE), 329 DEVMAP_ENTRY_END 330 }; 331 332 return devmap; 333 } 334 335 static void 336 exynos5_platform_bootstrap(void) 337 { 338 339 exynos_bootstrap(5); 340 341 #if defined(MULTIPROCESSOR) && defined(EXYNOS5422_DISABLE_CA7_CLUSTER) 342 const struct device_compatible_entry *cd = 343 of_compatible_lookup(OF_finddevice("/"), mp_compat_data); 344 if (cd && cd->data == exynos5800_mpstart) { 345 void *fdt_data = __UNCONST(fdtbus_get_data()); 346 int cpu_off, cpus_off, len; 347 348 cpus_off = fdt_path_offset(fdt_data, "/cpus"); 349 if (cpus_off < 0) 350 return; 351 352 fdt_for_each_subnode(cpu_off, fdt_data, cpus_off) { 353 const void *prop = fdt_getprop(fdt_data, cpu_off, "reg", &len); 354 if (len != 4) 355 continue; 356 const uint32_t mpidr = be32dec(prop); 357 if (mpidr != cpu_mpidr_aff_read() && __SHIFTOUT(mpidr, MPIDR_AFF1) == 1) 358 fdt_setprop_string(fdt_data, cpu_off, "status", "fail"); 359 } 360 } 361 #endif 362 363 arm_fdt_cpu_bootstrap(); 364 } 365 366 static const struct fdt_platform exynos5_platform = { 367 .fp_devmap = exynos5_platform_devmap, 368 .fp_bootstrap = exynos5_platform_bootstrap, 369 .fp_mpstart = exynos_platform_mpstart, 370 .fp_init_attach_args = exynos_platform_init_attach_args, 371 .fp_device_register = exynos_platform_device_register, 372 .fp_reset = exynos5_platform_reset, 373 .fp_delay = mct_delay, 374 .fp_uart_freq = exynos_platform_uart_freq, 375 }; 376 377 FDT_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform); 378 #endif 379
Indexes created Sun Sep 21 19:09:51 GMT 2025