1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <dt-bindings/clock/rk3399-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3399-power.h> 12 #include <dt-bindings/thermal/thermal.h> 13 14 / { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 pcie0: pcie@f8000000 { 201 compatible = "rockchip,rk3399-pcie"; 202 reg = <0x0 0xf8000000 0x0 0x2000000>, 203 <0x0 0xfd000000 0x0 0x1000000>; 204 reg-names = "axi-base", "apb-base"; 205 device_type = "pci"; 206 #address-cells = <3>; 207 #size-cells = <2>; 208 #interrupt-cells = <1>; 209 aspm-no-l0s; 210 bus-range = <0x0 0x1f>; 211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 213 clock-names = "aclk", "aclk-perf", 214 "hclk", "pm"; 215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 218 interrupt-names = "sys", "legacy", "client"; 219 interrupt-map-mask = <0 0 0 7>; 220 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 221 <0 0 0 2 &pcie0_intc 1>, 222 <0 0 0 3 &pcie0_intc 2>, 223 <0 0 0 4 &pcie0_intc 3>; 224 max-link-speed = <1>; 225 msi-map = <0x0 &its 0x0 0x1000>; 226 phys = <&pcie_phy 0>, <&pcie_phy 1>, 227 <&pcie_phy 2>, <&pcie_phy 3>; 228 phy-names = "pcie-phy-0", "pcie-phy-1", 229 "pcie-phy-2", "pcie-phy-3"; 230 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 235 <&cru SRST_A_PCIE>; 236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 237 "pm", "pclk", "aclk"; 238 status = "disabled"; 239 240 pcie0_intc: interrupt-controller { 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <1>; 244 }; 245 }; 246 247 gmac: ethernet@fe300000 { 248 compatible = "rockchip,rk3399-gmac"; 249 reg = <0x0 0xfe300000 0x0 0x10000>; 250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 251 interrupt-names = "macirq"; 252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 255 <&cru PCLK_GMAC>; 256 clock-names = "stmmaceth", "mac_clk_rx", 257 "mac_clk_tx", "clk_mac_ref", 258 "clk_mac_refout", "aclk_mac", 259 "pclk_mac"; 260 power-domains = <&power RK3399_PD_GMAC>; 261 resets = <&cru SRST_A_GMAC>; 262 reset-names = "stmmaceth"; 263 rockchip,grf = <&grf>; 264 snps,txpbl = <0x4>; 265 status = "disabled"; 266 }; 267 268 sdio0: mmc@fe310000 { 269 compatible = "rockchip,rk3399-dw-mshc", 270 "rockchip,rk3288-dw-mshc"; 271 reg = <0x0 0xfe310000 0x0 0x4000>; 272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 273 max-frequency = <150000000>; 274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 277 fifo-depth = <0x100>; 278 power-domains = <&power RK3399_PD_SDIOAUDIO>; 279 resets = <&cru SRST_SDIO0>; 280 reset-names = "reset"; 281 status = "disabled"; 282 }; 283 284 sdmmc: mmc@fe320000 { 285 compatible = "rockchip,rk3399-dw-mshc", 286 "rockchip,rk3288-dw-mshc"; 287 reg = <0x0 0xfe320000 0x0 0x4000>; 288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 289 max-frequency = <150000000>; 290 assigned-clocks = <&cru HCLK_SD>; 291 assigned-clock-rates = <200000000>; 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 295 fifo-depth = <0x100>; 296 power-domains = <&power RK3399_PD_SD>; 297 resets = <&cru SRST_SDMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 sdhci: mmc@fe330000 { 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 304 reg = <0x0 0xfe330000 0x0 0x10000>; 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 306 arasan,soc-ctl-syscon = <&grf>; 307 assigned-clocks = <&cru SCLK_EMMC>; 308 assigned-clock-rates = <200000000>; 309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 310 clock-names = "clk_xin", "clk_ahb"; 311 clock-output-names = "emmc_cardclock"; 312 #clock-cells = <0>; 313 phys = <&emmc_phy>; 314 phy-names = "phy_arasan"; 315 power-domains = <&power RK3399_PD_EMMC>; 316 disable-cqe-dcmd; 317 status = "disabled"; 318 }; 319 320 usb_host0_ehci: usb@fe380000 { 321 compatible = "generic-ehci"; 322 reg = <0x0 0xfe380000 0x0 0x20000>; 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 325 <&u2phy0>; 326 phys = <&u2phy0_host>; 327 phy-names = "usb"; 328 status = "disabled"; 329 }; 330 331 usb_host0_ohci: usb@fe3a0000 { 332 compatible = "generic-ohci"; 333 reg = <0x0 0xfe3a0000 0x0 0x20000>; 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 336 <&u2phy0>; 337 phys = <&u2phy0_host>; 338 phy-names = "usb"; 339 status = "disabled"; 340 }; 341 342 usb_host1_ehci: usb@fe3c0000 { 343 compatible = "generic-ehci"; 344 reg = <0x0 0xfe3c0000 0x0 0x20000>; 345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 347 <&u2phy1>; 348 phys = <&u2phy1_host>; 349 phy-names = "usb"; 350 status = "disabled"; 351 }; 352 353 usb_host1_ohci: usb@fe3e0000 { 354 compatible = "generic-ohci"; 355 reg = <0x0 0xfe3e0000 0x0 0x20000>; 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 358 <&u2phy1>; 359 phys = <&u2phy1_host>; 360 phy-names = "usb"; 361 status = "disabled"; 362 }; 363 364 usbdrd3_0: usb@fe800000 { 365 compatible = "rockchip,rk3399-dwc3"; 366 #address-cells = <2>; 367 #size-cells = <2>; 368 ranges; 369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 372 clock-names = "ref_clk", "suspend_clk", 373 "bus_clk", "aclk_usb3_rksoc_axi_perf", 374 "aclk_usb3", "grf_clk"; 375 resets = <&cru SRST_A_USB3_OTG0>; 376 reset-names = "usb3-otg"; 377 status = "disabled"; 378 379 usbdrd_dwc3_0: usb@fe800000 { 380 compatible = "snps,dwc3"; 381 reg = <0x0 0xfe800000 0x0 0x100000>; 382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 384 <&cru SCLK_USB3OTG0_SUSPEND>; 385 clock-names = "ref", "bus_early", "suspend"; 386 dr_mode = "otg"; 387 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 388 phy-names = "usb2-phy", "usb3-phy"; 389 phy_type = "utmi_wide"; 390 snps,dis_enblslpm_quirk; 391 snps,dis-u2-freeclk-exists-quirk; 392 snps,dis_u2_susphy_quirk; 393 snps,dis-del-phy-power-chg-quirk; 394 snps,dis-tx-ipgap-linecheck-quirk; 395 power-domains = <&power RK3399_PD_USB3>; 396 status = "disabled"; 397 }; 398 }; 399 400 usbdrd3_1: usb@fe900000 { 401 compatible = "rockchip,rk3399-dwc3"; 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges; 405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 408 clock-names = "ref_clk", "suspend_clk", 409 "bus_clk", "aclk_usb3_rksoc_axi_perf", 410 "aclk_usb3", "grf_clk"; 411 resets = <&cru SRST_A_USB3_OTG1>; 412 reset-names = "usb3-otg"; 413 status = "disabled"; 414 415 usbdrd_dwc3_1: usb@fe900000 { 416 compatible = "snps,dwc3"; 417 reg = <0x0 0xfe900000 0x0 0x100000>; 418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 420 <&cru SCLK_USB3OTG1_SUSPEND>; 421 clock-names = "ref", "bus_early", "suspend"; 422 dr_mode = "otg"; 423 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 424 phy-names = "usb2-phy", "usb3-phy"; 425 phy_type = "utmi_wide"; 426 snps,dis_enblslpm_quirk; 427 snps,dis-u2-freeclk-exists-quirk; 428 snps,dis_u2_susphy_quirk; 429 snps,dis-del-phy-power-chg-quirk; 430 snps,dis-tx-ipgap-linecheck-quirk; 431 power-domains = <&power RK3399_PD_USB3>; 432 status = "disabled"; 433 }; 434 }; 435 436 cdn_dp: dp@fec00000 { 437 compatible = "rockchip,rk3399-cdn-dp"; 438 reg = <0x0 0xfec00000 0x0 0x100000>; 439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 441 assigned-clock-rates = <100000000>, <200000000>; 442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 444 clock-names = "core-clk", "pclk", "spdif", "grf"; 445 phys = <&tcphy0_dp>, <&tcphy1_dp>; 446 power-domains = <&power RK3399_PD_HDCP>; 447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 449 reset-names = "spdif", "dptx", "apb", "core"; 450 rockchip,grf = <&grf>; 451 #sound-dai-cells = <1>; 452 status = "disabled"; 453 454 ports { 455 dp_in: port { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 459 dp_in_vopb: endpoint@0 { 460 reg = <0>; 461 remote-endpoint = <&vopb_out_dp>; 462 }; 463 464 dp_in_vopl: endpoint@1 { 465 reg = <1>; 466 remote-endpoint = <&vopl_out_dp>; 467 }; 468 }; 469 }; 470 }; 471 472 gic: interrupt-controller@fee00000 { 473 compatible = "arm,gic-v3"; 474 #interrupt-cells = <4>; 475 #address-cells = <2>; 476 #size-cells = <2>; 477 ranges; 478 interrupt-controller; 479 480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 481 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 482 <0x0 0xfff00000 0 0x10000>, /* GICC */ 483 <0x0 0xfff10000 0 0x10000>, /* GICH */ 484 <0x0 0xfff20000 0 0x10000>; /* GICV */ 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 486 its: interrupt-controller@fee20000 { 487 compatible = "arm,gic-v3-its"; 488 msi-controller; 489 #msi-cells = <1>; 490 reg = <0x0 0xfee20000 0x0 0x20000>; 491 }; 492 493 ppi-partitions { 494 ppi_cluster0: interrupt-partition-0 { 495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 496 }; 497 498 ppi_cluster1: interrupt-partition-1 { 499 affinity = <&cpu_b0 &cpu_b1>; 500 }; 501 }; 502 }; 503 504 saradc: saradc@ff100000 { 505 compatible = "rockchip,rk3399-saradc"; 506 reg = <0x0 0xff100000 0x0 0x100>; 507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 508 #io-channel-cells = <1>; 509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 510 clock-names = "saradc", "apb_pclk"; 511 resets = <&cru SRST_P_SARADC>; 512 reset-names = "saradc-apb"; 513 status = "disabled"; 514 }; 515 516 i2c1: i2c@ff110000 { 517 compatible = "rockchip,rk3399-i2c"; 518 reg = <0x0 0xff110000 0x0 0x1000>; 519 assigned-clocks = <&cru SCLK_I2C1>; 520 assigned-clock-rates = <200000000>; 521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 522 clock-names = "i2c", "pclk"; 523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&i2c1_xfer>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 531 i2c2: i2c@ff120000 { 532 compatible = "rockchip,rk3399-i2c"; 533 reg = <0x0 0xff120000 0x0 0x1000>; 534 assigned-clocks = <&cru SCLK_I2C2>; 535 assigned-clock-rates = <200000000>; 536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c2_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c3: i2c@ff130000 { 547 compatible = "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff130000 0x0 0x1000>; 549 assigned-clocks = <&cru SCLK_I2C3>; 550 assigned-clock-rates = <200000000>; 551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 552 clock-names = "i2c", "pclk"; 553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c3_xfer>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 i2c5: i2c@ff140000 { 562 compatible = "rockchip,rk3399-i2c"; 563 reg = <0x0 0xff140000 0x0 0x1000>; 564 assigned-clocks = <&cru SCLK_I2C5>; 565 assigned-clock-rates = <200000000>; 566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 567 clock-names = "i2c", "pclk"; 568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c5_xfer>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c6: i2c@ff150000 { 577 compatible = "rockchip,rk3399-i2c"; 578 reg = <0x0 0xff150000 0x0 0x1000>; 579 assigned-clocks = <&cru SCLK_I2C6>; 580 assigned-clock-rates = <200000000>; 581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 582 clock-names = "i2c", "pclk"; 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c6_xfer>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 i2c7: i2c@ff160000 { 592 compatible = "rockchip,rk3399-i2c"; 593 reg = <0x0 0xff160000 0x0 0x1000>; 594 assigned-clocks = <&cru SCLK_I2C7>; 595 assigned-clock-rates = <200000000>; 596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 597 clock-names = "i2c", "pclk"; 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&i2c7_xfer>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 uart0: serial@ff180000 { 607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 608 reg = <0x0 0xff180000 0x0 0x100>; 609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 610 clock-names = "baudclk", "apb_pclk"; 611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 612 reg-shift = <2>; 613 reg-io-width = <4>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&uart0_xfer>; 616 status = "disabled"; 617 }; 618 619 uart1: serial@ff190000 { 620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 621 reg = <0x0 0xff190000 0x0 0x100>; 622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 623 clock-names = "baudclk", "apb_pclk"; 624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 625 reg-shift = <2>; 626 reg-io-width = <4>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&uart1_xfer>; 629 status = "disabled"; 630 }; 631 632 uart2: serial@ff1a0000 { 633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 634 reg = <0x0 0xff1a0000 0x0 0x100>; 635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 636 clock-names = "baudclk", "apb_pclk"; 637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 638 reg-shift = <2>; 639 reg-io-width = <4>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&uart2c_xfer>; 642 status = "disabled"; 643 }; 644 645 uart3: serial@ff1b0000 { 646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 647 reg = <0x0 0xff1b0000 0x0 0x100>; 648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 649 clock-names = "baudclk", "apb_pclk"; 650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 651 reg-shift = <2>; 652 reg-io-width = <4>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&uart3_xfer>; 655 status = "disabled"; 656 }; 657 658 spi0: spi@ff1c0000 { 659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 660 reg = <0x0 0xff1c0000 0x0 0x1000>; 661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 662 clock-names = "spiclk", "apb_pclk"; 663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 664 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 665 dma-names = "tx", "rx"; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 673 spi1: spi@ff1d0000 { 674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 675 reg = <0x0 0xff1d0000 0x0 0x1000>; 676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 677 clock-names = "spiclk", "apb_pclk"; 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 679 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 680 dma-names = "tx", "rx"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 spi2: spi@ff1e0000 { 689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 690 reg = <0x0 0xff1e0000 0x0 0x1000>; 691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 692 clock-names = "spiclk", "apb_pclk"; 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 694 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 695 dma-names = "tx", "rx"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 spi4: spi@ff1f0000 { 704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 705 reg = <0x0 0xff1f0000 0x0 0x1000>; 706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 707 clock-names = "spiclk", "apb_pclk"; 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 709 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 710 dma-names = "tx", "rx"; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 status = "disabled"; 716 }; 717 718 spi5: spi@ff200000 { 719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 720 reg = <0x0 0xff200000 0x0 0x1000>; 721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 722 clock-names = "spiclk", "apb_pclk"; 723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 724 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 725 dma-names = "tx", "rx"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 728 power-domains = <&power RK3399_PD_SDIOAUDIO>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 thermal_zones: thermal-zones { 735 cpu_thermal: cpu-thermal { 736 polling-delay-passive = <100>; 737 polling-delay = <1000>; 738 739 thermal-sensors = <&tsadc 0>; 740 741 trips { 742 cpu_alert0: cpu_alert0 { 743 temperature = <70000>; 744 hysteresis = <2000>; 745 type = "passive"; 746 }; 747 cpu_alert1: cpu_alert1 { 748 temperature = <75000>; 749 hysteresis = <2000>; 750 type = "passive"; 751 }; 752 cpu_crit: cpu_crit { 753 temperature = <95000>; 754 hysteresis = <2000>; 755 type = "critical"; 756 }; 757 }; 758 759 cooling-maps { 760 map0 { 761 trip = <&cpu_alert0>; 762 cooling-device = 763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 765 }; 766 map1 { 767 trip = <&cpu_alert1>; 768 cooling-device = 769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 775 }; 776 }; 777 }; 778 779 gpu_thermal: gpu-thermal { 780 polling-delay-passive = <100>; 781 polling-delay = <1000>; 782 783 thermal-sensors = <&tsadc 1>; 784 785 trips { 786 gpu_alert0: gpu_alert0 { 787 temperature = <75000>; 788 hysteresis = <2000>; 789 type = "passive"; 790 }; 791 gpu_crit: gpu_crit { 792 temperature = <95000>; 793 hysteresis = <2000>; 794 type = "critical"; 795 }; 796 }; 797 798 cooling-maps { 799 map0 { 800 trip = <&gpu_alert0>; 801 cooling-device = 802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 803 }; 804 }; 805 }; 806 }; 807 808 tsadc: tsadc@ff260000 { 809 compatible = "rockchip,rk3399-tsadc"; 810 reg = <0x0 0xff260000 0x0 0x100>; 811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 812 assigned-clocks = <&cru SCLK_TSADC>; 813 assigned-clock-rates = <750000>; 814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 815 clock-names = "tsadc", "apb_pclk"; 816 resets = <&cru SRST_TSADC>; 817 reset-names = "tsadc-apb"; 818 rockchip,grf = <&grf>; 819 rockchip,hw-tshut-temp = <95000>; 820 pinctrl-names = "init", "default", "sleep"; 821 pinctrl-0 = <&otp_pin>; 822 pinctrl-1 = <&otp_out>; 823 pinctrl-2 = <&otp_pin>; 824 #thermal-sensor-cells = <1>; 825 status = "disabled"; 826 }; 827 828 qos_emmc: qos@ffa58000 { 829 compatible = "rockchip,rk3399-qos", "syscon"; 830 reg = <0x0 0xffa58000 0x0 0x20>; 831 }; 832 833 qos_gmac: qos@ffa5c000 { 834 compatible = "rockchip,rk3399-qos", "syscon"; 835 reg = <0x0 0xffa5c000 0x0 0x20>; 836 }; 837 838 qos_pcie: qos@ffa60080 { 839 compatible = "rockchip,rk3399-qos", "syscon"; 840 reg = <0x0 0xffa60080 0x0 0x20>; 841 }; 842 843 qos_usb_host0: qos@ffa60100 { 844 compatible = "rockchip,rk3399-qos", "syscon"; 845 reg = <0x0 0xffa60100 0x0 0x20>; 846 }; 847 848 qos_usb_host1: qos@ffa60180 { 849 compatible = "rockchip,rk3399-qos", "syscon"; 850 reg = <0x0 0xffa60180 0x0 0x20>; 851 }; 852 853 qos_usb_otg0: qos@ffa70000 { 854 compatible = "rockchip,rk3399-qos", "syscon"; 855 reg = <0x0 0xffa70000 0x0 0x20>; 856 }; 857 858 qos_usb_otg1: qos@ffa70080 { 859 compatible = "rockchip,rk3399-qos", "syscon"; 860 reg = <0x0 0xffa70080 0x0 0x20>; 861 }; 862 863 qos_sd: qos@ffa74000 { 864 compatible = "rockchip,rk3399-qos", "syscon"; 865 reg = <0x0 0xffa74000 0x0 0x20>; 866 }; 867 868 qos_sdioaudio: qos@ffa76000 { 869 compatible = "rockchip,rk3399-qos", "syscon"; 870 reg = <0x0 0xffa76000 0x0 0x20>; 871 }; 872 873 qos_hdcp: qos@ffa90000 { 874 compatible = "rockchip,rk3399-qos", "syscon"; 875 reg = <0x0 0xffa90000 0x0 0x20>; 876 }; 877 878 qos_iep: qos@ffa98000 { 879 compatible = "rockchip,rk3399-qos", "syscon"; 880 reg = <0x0 0xffa98000 0x0 0x20>; 881 }; 882 883 qos_isp0_m0: qos@ffaa0000 { 884 compatible = "rockchip,rk3399-qos", "syscon"; 885 reg = <0x0 0xffaa0000 0x0 0x20>; 886 }; 887 888 qos_isp0_m1: qos@ffaa0080 { 889 compatible = "rockchip,rk3399-qos", "syscon"; 890 reg = <0x0 0xffaa0080 0x0 0x20>; 891 }; 892 893 qos_isp1_m0: qos@ffaa8000 { 894 compatible = "rockchip,rk3399-qos", "syscon"; 895 reg = <0x0 0xffaa8000 0x0 0x20>; 896 }; 897 898 qos_isp1_m1: qos@ffaa8080 { 899 compatible = "rockchip,rk3399-qos", "syscon"; 900 reg = <0x0 0xffaa8080 0x0 0x20>; 901 }; 902 903 qos_rga_r: qos@ffab0000 { 904 compatible = "rockchip,rk3399-qos", "syscon"; 905 reg = <0x0 0xffab0000 0x0 0x20>; 906 }; 907 908 qos_rga_w: qos@ffab0080 { 909 compatible = "rockchip,rk3399-qos", "syscon"; 910 reg = <0x0 0xffab0080 0x0 0x20>; 911 }; 912 913 qos_video_m0: qos@ffab8000 { 914 compatible = "rockchip,rk3399-qos", "syscon"; 915 reg = <0x0 0xffab8000 0x0 0x20>; 916 }; 917 918 qos_video_m1_r: qos@ffac0000 { 919 compatible = "rockchip,rk3399-qos", "syscon"; 920 reg = <0x0 0xffac0000 0x0 0x20>; 921 }; 922 923 qos_video_m1_w: qos@ffac0080 { 924 compatible = "rockchip,rk3399-qos", "syscon"; 925 reg = <0x0 0xffac0080 0x0 0x20>; 926 }; 927 928 qos_vop_big_r: qos@ffac8000 { 929 compatible = "rockchip,rk3399-qos", "syscon"; 930 reg = <0x0 0xffac8000 0x0 0x20>; 931 }; 932 933 qos_vop_big_w: qos@ffac8080 { 934 compatible = "rockchip,rk3399-qos", "syscon"; 935 reg = <0x0 0xffac8080 0x0 0x20>; 936 }; 937 938 qos_vop_little: qos@ffad0000 { 939 compatible = "rockchip,rk3399-qos", "syscon"; 940 reg = <0x0 0xffad0000 0x0 0x20>; 941 }; 942 943 qos_perihp: qos@ffad8080 { 944 compatible = "rockchip,rk3399-qos", "syscon"; 945 reg = <0x0 0xffad8080 0x0 0x20>; 946 }; 947 948 qos_gpu: qos@ffae0000 { 949 compatible = "rockchip,rk3399-qos", "syscon"; 950 reg = <0x0 0xffae0000 0x0 0x20>; 951 }; 952 953 pmu: power-management@ff310000 { 954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 955 reg = <0x0 0xff310000 0x0 0x1000>; 956 957 /* 958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 960 * Some of the power domains are grouped together for every 961 * voltage domain. 962 * The detail contents as below. 963 */ 964 power: power-controller { 965 compatible = "rockchip,rk3399-power-controller"; 966 #power-domain-cells = <1>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 /* These power domains are grouped by VD_CENTER */ 971 power-domain@RK3399_PD_IEP { 972 reg = <RK3399_PD_IEP>; 973 clocks = <&cru ACLK_IEP>, 974 <&cru HCLK_IEP>; 975 pm_qos = <&qos_iep>; 976 #power-domain-cells = <0>; 977 }; 978 power-domain@RK3399_PD_RGA { 979 reg = <RK3399_PD_RGA>; 980 clocks = <&cru ACLK_RGA>, 981 <&cru HCLK_RGA>; 982 pm_qos = <&qos_rga_r>, 983 <&qos_rga_w>; 984 #power-domain-cells = <0>; 985 }; 986 power-domain@RK3399_PD_VCODEC { 987 reg = <RK3399_PD_VCODEC>; 988 clocks = <&cru ACLK_VCODEC>, 989 <&cru HCLK_VCODEC>; 990 pm_qos = <&qos_video_m0>; 991 #power-domain-cells = <0>; 992 }; 993 power-domain@RK3399_PD_VDU { 994 reg = <RK3399_PD_VDU>; 995 clocks = <&cru ACLK_VDU>, 996 <&cru HCLK_VDU>; 997 pm_qos = <&qos_video_m1_r>, 998 <&qos_video_m1_w>; 999 #power-domain-cells = <0>; 1000 }; 1001 1002 /* These power domains are grouped by VD_GPU */ 1003 power-domain@RK3399_PD_GPU { 1004 reg = <RK3399_PD_GPU>; 1005 clocks = <&cru ACLK_GPU>; 1006 pm_qos = <&qos_gpu>; 1007 #power-domain-cells = <0>; 1008 }; 1009 1010 /* These power domains are grouped by VD_LOGIC */ 1011 power-domain@RK3399_PD_EDP { 1012 reg = <RK3399_PD_EDP>; 1013 clocks = <&cru PCLK_EDP_CTRL>; 1014 #power-domain-cells = <0>; 1015 }; 1016 power-domain@RK3399_PD_EMMC { 1017 reg = <RK3399_PD_EMMC>; 1018 clocks = <&cru ACLK_EMMC>; 1019 pm_qos = <&qos_emmc>; 1020 #power-domain-cells = <0>; 1021 }; 1022 power-domain@RK3399_PD_GMAC { 1023 reg = <RK3399_PD_GMAC>; 1024 clocks = <&cru ACLK_GMAC>, 1025 <&cru PCLK_GMAC>; 1026 pm_qos = <&qos_gmac>; 1027 #power-domain-cells = <0>; 1028 }; 1029 power-domain@RK3399_PD_SD { 1030 reg = <RK3399_PD_SD>; 1031 clocks = <&cru HCLK_SDMMC>, 1032 <&cru SCLK_SDMMC>; 1033 pm_qos = <&qos_sd>; 1034 #power-domain-cells = <0>; 1035 }; 1036 power-domain@RK3399_PD_SDIOAUDIO { 1037 reg = <RK3399_PD_SDIOAUDIO>; 1038 clocks = <&cru HCLK_SDIO>; 1039 pm_qos = <&qos_sdioaudio>; 1040 #power-domain-cells = <0>; 1041 }; 1042 power-domain@RK3399_PD_TCPD0 { 1043 reg = <RK3399_PD_TCPD0>; 1044 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1045 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1046 #power-domain-cells = <0>; 1047 }; 1048 power-domain@RK3399_PD_TCPD1 { 1049 reg = <RK3399_PD_TCPD1>; 1050 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1051 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1052 #power-domain-cells = <0>; 1053 }; 1054 power-domain@RK3399_PD_USB3 { 1055 reg = <RK3399_PD_USB3>; 1056 clocks = <&cru ACLK_USB3>; 1057 pm_qos = <&qos_usb_otg0>, 1058 <&qos_usb_otg1>; 1059 #power-domain-cells = <0>; 1060 }; 1061 power-domain@RK3399_PD_VIO { 1062 reg = <RK3399_PD_VIO>; 1063 #power-domain-cells = <1>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 power-domain@RK3399_PD_HDCP { 1068 reg = <RK3399_PD_HDCP>; 1069 clocks = <&cru ACLK_HDCP>, 1070 <&cru HCLK_HDCP>, 1071 <&cru PCLK_HDCP>; 1072 pm_qos = <&qos_hdcp>; 1073 #power-domain-cells = <0>; 1074 }; 1075 power-domain@RK3399_PD_ISP0 { 1076 reg = <RK3399_PD_ISP0>; 1077 clocks = <&cru ACLK_ISP0>, 1078 <&cru HCLK_ISP0>; 1079 pm_qos = <&qos_isp0_m0>, 1080 <&qos_isp0_m1>; 1081 #power-domain-cells = <0>; 1082 }; 1083 power-domain@RK3399_PD_ISP1 { 1084 reg = <RK3399_PD_ISP1>; 1085 clocks = <&cru ACLK_ISP1>, 1086 <&cru HCLK_ISP1>; 1087 pm_qos = <&qos_isp1_m0>, 1088 <&qos_isp1_m1>; 1089 #power-domain-cells = <0>; 1090 }; 1091 power-domain@RK3399_PD_VO { 1092 reg = <RK3399_PD_VO>; 1093 #power-domain-cells = <1>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 power-domain@RK3399_PD_VOPB { 1098 reg = <RK3399_PD_VOPB>; 1099 clocks = <&cru ACLK_VOP0>, 1100 <&cru HCLK_VOP0>; 1101 pm_qos = <&qos_vop_big_r>, 1102 <&qos_vop_big_w>; 1103 #power-domain-cells = <0>; 1104 }; 1105 power-domain@RK3399_PD_VOPL { 1106 reg = <RK3399_PD_VOPL>; 1107 clocks = <&cru ACLK_VOP1>, 1108 <&cru HCLK_VOP1>; 1109 pm_qos = <&qos_vop_little>; 1110 #power-domain-cells = <0>; 1111 }; 1112 }; 1113 }; 1114 }; 1115 }; 1116 1117 pmugrf: syscon@ff320000 { 1118 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1119 reg = <0x0 0xff320000 0x0 0x1000>; 1120 1121 pmu_io_domains: io-domains { 1122 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 spi3: spi@ff350000 { 1128 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1129 reg = <0x0 0xff350000 0x0 0x1000>; 1130 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1131 clock-names = "spiclk", "apb_pclk"; 1132 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 uart4: serial@ff370000 { 1141 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1142 reg = <0x0 0xff370000 0x0 0x100>; 1143 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1144 clock-names = "baudclk", "apb_pclk"; 1145 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1146 reg-shift = <2>; 1147 reg-io-width = <4>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&uart4_xfer>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c0: i2c@ff3c0000 { 1154 compatible = "rockchip,rk3399-i2c"; 1155 reg = <0x0 0xff3c0000 0x0 0x1000>; 1156 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1157 assigned-clock-rates = <200000000>; 1158 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1159 clock-names = "i2c", "pclk"; 1160 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&i2c0_xfer>; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 i2c4: i2c@ff3d0000 { 1169 compatible = "rockchip,rk3399-i2c"; 1170 reg = <0x0 0xff3d0000 0x0 0x1000>; 1171 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1172 assigned-clock-rates = <200000000>; 1173 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1174 clock-names = "i2c", "pclk"; 1175 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&i2c4_xfer>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 status = "disabled"; 1181 }; 1182 1183 i2c8: i2c@ff3e0000 { 1184 compatible = "rockchip,rk3399-i2c"; 1185 reg = <0x0 0xff3e0000 0x0 0x1000>; 1186 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1187 assigned-clock-rates = <200000000>; 1188 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1189 clock-names = "i2c", "pclk"; 1190 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&i2c8_xfer>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 status = "disabled"; 1196 }; 1197 1198 pwm0: pwm@ff420000 { 1199 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1200 reg = <0x0 0xff420000 0x0 0x10>; 1201 #pwm-cells = <3>; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&pwm0_pin>; 1204 clocks = <&pmucru PCLK_RKPWM_PMU>; 1205 status = "disabled"; 1206 }; 1207 1208 pwm1: pwm@ff420010 { 1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1210 reg = <0x0 0xff420010 0x0 0x10>; 1211 #pwm-cells = <3>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&pwm1_pin>; 1214 clocks = <&pmucru PCLK_RKPWM_PMU>; 1215 status = "disabled"; 1216 }; 1217 1218 pwm2: pwm@ff420020 { 1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1220 reg = <0x0 0xff420020 0x0 0x10>; 1221 #pwm-cells = <3>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&pwm2_pin>; 1224 clocks = <&pmucru PCLK_RKPWM_PMU>; 1225 status = "disabled"; 1226 }; 1227 1228 pwm3: pwm@ff420030 { 1229 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1230 reg = <0x0 0xff420030 0x0 0x10>; 1231 #pwm-cells = <3>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&pwm3a_pin>; 1234 clocks = <&pmucru PCLK_RKPWM_PMU>; 1235 status = "disabled"; 1236 }; 1237 1238 vpu: video-codec@ff650000 { 1239 compatible = "rockchip,rk3399-vpu"; 1240 reg = <0x0 0xff650000 0x0 0x800>; 1241 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1242 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1243 interrupt-names = "vepu", "vdpu"; 1244 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1245 clock-names = "aclk", "hclk"; 1246 iommus = <&vpu_mmu>; 1247 power-domains = <&power RK3399_PD_VCODEC>; 1248 }; 1249 1250 vpu_mmu: iommu@ff650800 { 1251 compatible = "rockchip,iommu"; 1252 reg = <0x0 0xff650800 0x0 0x40>; 1253 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1254 interrupt-names = "vpu_mmu"; 1255 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1256 clock-names = "aclk", "iface"; 1257 #iommu-cells = <0>; 1258 power-domains = <&power RK3399_PD_VCODEC>; 1259 }; 1260 1261 vdec: video-codec@ff660000 { 1262 compatible = "rockchip,rk3399-vdec"; 1263 reg = <0x0 0xff660000 0x0 0x400>; 1264 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1265 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1266 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1267 clock-names = "axi", "ahb", "cabac", "core"; 1268 iommus = <&vdec_mmu>; 1269 power-domains = <&power RK3399_PD_VDU>; 1270 }; 1271 1272 vdec_mmu: iommu@ff660480 { 1273 compatible = "rockchip,iommu"; 1274 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1275 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1276 interrupt-names = "vdec_mmu"; 1277 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1278 clock-names = "aclk", "iface"; 1279 power-domains = <&power RK3399_PD_VDU>; 1280 #iommu-cells = <0>; 1281 }; 1282 1283 iep_mmu: iommu@ff670800 { 1284 compatible = "rockchip,iommu"; 1285 reg = <0x0 0xff670800 0x0 0x40>; 1286 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1287 interrupt-names = "iep_mmu"; 1288 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1289 clock-names = "aclk", "iface"; 1290 #iommu-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 rga: rga@ff680000 { 1295 compatible = "rockchip,rk3399-rga"; 1296 reg = <0x0 0xff680000 0x0 0x10000>; 1297 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1298 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1299 clock-names = "aclk", "hclk", "sclk"; 1300 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1301 reset-names = "core", "axi", "ahb"; 1302 power-domains = <&power RK3399_PD_RGA>; 1303 }; 1304 1305 efuse0: efuse@ff690000 { 1306 compatible = "rockchip,rk3399-efuse"; 1307 reg = <0x0 0xff690000 0x0 0x80>; 1308 #address-cells = <1>; 1309 #size-cells = <1>; 1310 clocks = <&cru PCLK_EFUSE1024NS>; 1311 clock-names = "pclk_efuse"; 1312 1313 /* Data cells */ 1314 cpu_id: cpu-id@7 { 1315 reg = <0x07 0x10>; 1316 }; 1317 cpub_leakage: cpu-leakage@17 { 1318 reg = <0x17 0x1>; 1319 }; 1320 gpu_leakage: gpu-leakage@18 { 1321 reg = <0x18 0x1>; 1322 }; 1323 center_leakage: center-leakage@19 { 1324 reg = <0x19 0x1>; 1325 }; 1326 cpul_leakage: cpu-leakage@1a { 1327 reg = <0x1a 0x1>; 1328 }; 1329 logic_leakage: logic-leakage@1b { 1330 reg = <0x1b 0x1>; 1331 }; 1332 wafer_info: wafer-info@1c { 1333 reg = <0x1c 0x1>; 1334 }; 1335 }; 1336 1337 dmac_bus: dma-controller@ff6d0000 { 1338 compatible = "arm,pl330", "arm,primecell"; 1339 reg = <0x0 0xff6d0000 0x0 0x4000>; 1340 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1341 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1342 #dma-cells = <1>; 1343 arm,pl330-periph-burst; 1344 clocks = <&cru ACLK_DMAC0_PERILP>; 1345 clock-names = "apb_pclk"; 1346 }; 1347 1348 dmac_peri: dma-controller@ff6e0000 { 1349 compatible = "arm,pl330", "arm,primecell"; 1350 reg = <0x0 0xff6e0000 0x0 0x4000>; 1351 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1352 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1353 #dma-cells = <1>; 1354 arm,pl330-periph-burst; 1355 clocks = <&cru ACLK_DMAC1_PERILP>; 1356 clock-names = "apb_pclk"; 1357 }; 1358 1359 pmucru: pmu-clock-controller@ff750000 { 1360 compatible = "rockchip,rk3399-pmucru"; 1361 reg = <0x0 0xff750000 0x0 0x1000>; 1362 rockchip,grf = <&pmugrf>; 1363 #clock-cells = <1>; 1364 #reset-cells = <1>; 1365 assigned-clocks = <&pmucru PLL_PPLL>; 1366 assigned-clock-rates = <676000000>; 1367 }; 1368 1369 cru: clock-controller@ff760000 { 1370 compatible = "rockchip,rk3399-cru"; 1371 reg = <0x0 0xff760000 0x0 0x1000>; 1372 rockchip,grf = <&grf>; 1373 #clock-cells = <1>; 1374 #reset-cells = <1>; 1375 assigned-clocks = 1376 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1377 <&cru PLL_NPLL>, 1378 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1379 <&cru PCLK_PERIHP>, 1380 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1381 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1382 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1383 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1384 <&cru ACLK_GIC_PRE>, 1385 <&cru PCLK_DDR>; 1386 assigned-clock-rates = 1387 <594000000>, <800000000>, 1388 <1000000000>, 1389 <150000000>, <75000000>, 1390 <37500000>, 1391 <100000000>, <100000000>, 1392 <50000000>, <600000000>, 1393 <100000000>, <50000000>, 1394 <400000000>, <400000000>, 1395 <200000000>, 1396 <200000000>; 1397 }; 1398 1399 grf: syscon@ff770000 { 1400 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1401 reg = <0x0 0xff770000 0x0 0x10000>; 1402 #address-cells = <1>; 1403 #size-cells = <1>; 1404 1405 io_domains: io-domains { 1406 compatible = "rockchip,rk3399-io-voltage-domain"; 1407 status = "disabled"; 1408 }; 1409 1410 mipi_dphy_rx0: mipi-dphy-rx0 { 1411 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1412 clocks = <&cru SCLK_MIPIDPHY_REF>, 1413 <&cru SCLK_DPHY_RX0_CFG>, 1414 <&cru PCLK_VIO_GRF>; 1415 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1416 power-domains = <&power RK3399_PD_VIO>; 1417 #phy-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 u2phy0: usb2phy@e450 { 1422 compatible = "rockchip,rk3399-usb2phy"; 1423 reg = <0xe450 0x10>; 1424 clocks = <&cru SCLK_USB2PHY0_REF>; 1425 clock-names = "phyclk"; 1426 #clock-cells = <0>; 1427 clock-output-names = "clk_usbphy0_480m"; 1428 status = "disabled"; 1429 1430 u2phy0_host: host-port { 1431 #phy-cells = <0>; 1432 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1433 interrupt-names = "linestate"; 1434 status = "disabled"; 1435 }; 1436 1437 u2phy0_otg: otg-port { 1438 #phy-cells = <0>; 1439 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1440 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1441 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1442 interrupt-names = "otg-bvalid", "otg-id", 1443 "linestate"; 1444 status = "disabled"; 1445 }; 1446 }; 1447 1448 u2phy1: usb2phy@e460 { 1449 compatible = "rockchip,rk3399-usb2phy"; 1450 reg = <0xe460 0x10>; 1451 clocks = <&cru SCLK_USB2PHY1_REF>; 1452 clock-names = "phyclk"; 1453 #clock-cells = <0>; 1454 clock-output-names = "clk_usbphy1_480m"; 1455 status = "disabled"; 1456 1457 u2phy1_host: host-port { 1458 #phy-cells = <0>; 1459 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1460 interrupt-names = "linestate"; 1461 status = "disabled"; 1462 }; 1463 1464 u2phy1_otg: otg-port { 1465 #phy-cells = <0>; 1466 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1467 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1468 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1469 interrupt-names = "otg-bvalid", "otg-id", 1470 "linestate"; 1471 status = "disabled"; 1472 }; 1473 }; 1474 1475 emmc_phy: phy@f780 { 1476 compatible = "rockchip,rk3399-emmc-phy"; 1477 reg = <0xf780 0x24>; 1478 clocks = <&sdhci>; 1479 clock-names = "emmcclk"; 1480 #phy-cells = <0>; 1481 status = "disabled"; 1482 }; 1483 1484 pcie_phy: pcie-phy { 1485 compatible = "rockchip,rk3399-pcie-phy"; 1486 clocks = <&cru SCLK_PCIEPHY_REF>; 1487 clock-names = "refclk"; 1488 #phy-cells = <1>; 1489 resets = <&cru SRST_PCIEPHY>; 1490 drive-impedance-ohm = <50>; 1491 reset-names = "phy"; 1492 status = "disabled"; 1493 }; 1494 }; 1495 1496 tcphy0: phy@ff7c0000 { 1497 compatible = "rockchip,rk3399-typec-phy"; 1498 reg = <0x0 0xff7c0000 0x0 0x40000>; 1499 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1500 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1501 clock-names = "tcpdcore", "tcpdphy-ref"; 1502 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1503 assigned-clock-rates = <50000000>; 1504 power-domains = <&power RK3399_PD_TCPD0>; 1505 resets = <&cru SRST_UPHY0>, 1506 <&cru SRST_UPHY0_PIPE_L00>, 1507 <&cru SRST_P_UPHY0_TCPHY>; 1508 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1509 rockchip,grf = <&grf>; 1510 status = "disabled"; 1511 1512 tcphy0_dp: dp-port { 1513 #phy-cells = <0>; 1514 }; 1515 1516 tcphy0_usb3: usb3-port { 1517 #phy-cells = <0>; 1518 }; 1519 }; 1520 1521 tcphy1: phy@ff800000 { 1522 compatible = "rockchip,rk3399-typec-phy"; 1523 reg = <0x0 0xff800000 0x0 0x40000>; 1524 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1525 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1526 clock-names = "tcpdcore", "tcpdphy-ref"; 1527 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1528 assigned-clock-rates = <50000000>; 1529 power-domains = <&power RK3399_PD_TCPD1>; 1530 resets = <&cru SRST_UPHY1>, 1531 <&cru SRST_UPHY1_PIPE_L00>, 1532 <&cru SRST_P_UPHY1_TCPHY>; 1533 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1534 rockchip,grf = <&grf>; 1535 status = "disabled"; 1536 1537 tcphy1_dp: dp-port { 1538 #phy-cells = <0>; 1539 }; 1540 1541 tcphy1_usb3: usb3-port { 1542 #phy-cells = <0>; 1543 }; 1544 }; 1545 1546 watchdog@ff848000 { 1547 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1548 reg = <0x0 0xff848000 0x0 0x100>; 1549 clocks = <&cru PCLK_WDT>; 1550 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1551 }; 1552 1553 rktimer: rktimer@ff850000 { 1554 compatible = "rockchip,rk3399-timer"; 1555 reg = <0x0 0xff850000 0x0 0x1000>; 1556 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1557 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1558 clock-names = "pclk", "timer"; 1559 }; 1560 1561 spdif: spdif@ff870000 { 1562 compatible = "rockchip,rk3399-spdif"; 1563 reg = <0x0 0xff870000 0x0 0x1000>; 1564 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1565 dmas = <&dmac_bus 7>; 1566 dma-names = "tx"; 1567 clock-names = "mclk", "hclk"; 1568 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&spdif_bus>; 1571 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1572 #sound-dai-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 i2s0: i2s@ff880000 { 1577 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1578 reg = <0x0 0xff880000 0x0 0x1000>; 1579 rockchip,grf = <&grf>; 1580 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1581 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1582 dma-names = "tx", "rx"; 1583 clock-names = "i2s_clk", "i2s_hclk"; 1584 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&i2s0_8ch_bus>; 1587 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1588 #sound-dai-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2s1: i2s@ff890000 { 1593 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1594 reg = <0x0 0xff890000 0x0 0x1000>; 1595 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1596 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1597 dma-names = "tx", "rx"; 1598 clock-names = "i2s_clk", "i2s_hclk"; 1599 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&i2s1_2ch_bus>; 1602 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1603 #sound-dai-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 i2s2: i2s@ff8a0000 { 1608 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1609 reg = <0x0 0xff8a0000 0x0 0x1000>; 1610 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1611 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1612 dma-names = "tx", "rx"; 1613 clock-names = "i2s_clk", "i2s_hclk"; 1614 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1615 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1616 #sound-dai-cells = <0>; 1617 status = "disabled"; 1618 }; 1619 1620 vopl: vop@ff8f0000 { 1621 compatible = "rockchip,rk3399-vop-lit"; 1622 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1623 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1624 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1625 assigned-clock-rates = <400000000>, <100000000>; 1626 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1627 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1628 iommus = <&vopl_mmu>; 1629 power-domains = <&power RK3399_PD_VOPL>; 1630 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1631 reset-names = "axi", "ahb", "dclk"; 1632 status = "disabled"; 1633 1634 vopl_out: port { 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 vopl_out_mipi: endpoint@0 { 1639 reg = <0>; 1640 remote-endpoint = <&mipi_in_vopl>; 1641 }; 1642 1643 vopl_out_edp: endpoint@1 { 1644 reg = <1>; 1645 remote-endpoint = <&edp_in_vopl>; 1646 }; 1647 1648 vopl_out_hdmi: endpoint@2 { 1649 reg = <2>; 1650 remote-endpoint = <&hdmi_in_vopl>; 1651 }; 1652 1653 vopl_out_mipi1: endpoint@3 { 1654 reg = <3>; 1655 remote-endpoint = <&mipi1_in_vopl>; 1656 }; 1657 1658 vopl_out_dp: endpoint@4 { 1659 reg = <4>; 1660 remote-endpoint = <&dp_in_vopl>; 1661 }; 1662 }; 1663 }; 1664 1665 vopl_mmu: iommu@ff8f3f00 { 1666 compatible = "rockchip,iommu"; 1667 reg = <0x0 0xff8f3f00 0x0 0x100>; 1668 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1669 interrupt-names = "vopl_mmu"; 1670 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1671 clock-names = "aclk", "iface"; 1672 power-domains = <&power RK3399_PD_VOPL>; 1673 #iommu-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 vopb: vop@ff900000 { 1678 compatible = "rockchip,rk3399-vop-big"; 1679 reg = <0x0 0xff900000 0x0 0x3efc>; 1680 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1681 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1682 assigned-clock-rates = <400000000>, <100000000>; 1683 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1685 iommus = <&vopb_mmu>; 1686 power-domains = <&power RK3399_PD_VOPB>; 1687 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1688 reset-names = "axi", "ahb", "dclk"; 1689 status = "disabled"; 1690 1691 vopb_out: port { 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 1695 vopb_out_edp: endpoint@0 { 1696 reg = <0>; 1697 remote-endpoint = <&edp_in_vopb>; 1698 }; 1699 1700 vopb_out_mipi: endpoint@1 { 1701 reg = <1>; 1702 remote-endpoint = <&mipi_in_vopb>; 1703 }; 1704 1705 vopb_out_hdmi: endpoint@2 { 1706 reg = <2>; 1707 remote-endpoint = <&hdmi_in_vopb>; 1708 }; 1709 1710 vopb_out_mipi1: endpoint@3 { 1711 reg = <3>; 1712 remote-endpoint = <&mipi1_in_vopb>; 1713 }; 1714 1715 vopb_out_dp: endpoint@4 { 1716 reg = <4>; 1717 remote-endpoint = <&dp_in_vopb>; 1718 }; 1719 }; 1720 }; 1721 1722 vopb_mmu: iommu@ff903f00 { 1723 compatible = "rockchip,iommu"; 1724 reg = <0x0 0xff903f00 0x0 0x100>; 1725 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1726 interrupt-names = "vopb_mmu"; 1727 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1728 clock-names = "aclk", "iface"; 1729 power-domains = <&power RK3399_PD_VOPB>; 1730 #iommu-cells = <0>; 1731 status = "disabled"; 1732 }; 1733 1734 isp0: isp0@ff910000 { 1735 compatible = "rockchip,rk3399-cif-isp"; 1736 reg = <0x0 0xff910000 0x0 0x4000>; 1737 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1738 clocks = <&cru SCLK_ISP0>, 1739 <&cru ACLK_ISP0_WRAPPER>, 1740 <&cru HCLK_ISP0_WRAPPER>; 1741 clock-names = "isp", "aclk", "hclk"; 1742 iommus = <&isp0_mmu>; 1743 phys = <&mipi_dphy_rx0>; 1744 phy-names = "dphy"; 1745 power-domains = <&power RK3399_PD_ISP0>; 1746 status = "disabled"; 1747 1748 ports { 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 1752 port@0 { 1753 reg = <0>; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 }; 1757 }; 1758 }; 1759 1760 isp0_mmu: iommu@ff914000 { 1761 compatible = "rockchip,iommu"; 1762 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1763 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1764 interrupt-names = "isp0_mmu"; 1765 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1766 clock-names = "aclk", "iface"; 1767 #iommu-cells = <0>; 1768 power-domains = <&power RK3399_PD_ISP0>; 1769 rockchip,disable-mmu-reset; 1770 }; 1771 1772 isp1_mmu: iommu@ff924000 { 1773 compatible = "rockchip,iommu"; 1774 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1775 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1776 interrupt-names = "isp1_mmu"; 1777 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1778 clock-names = "aclk", "iface"; 1779 #iommu-cells = <0>; 1780 power-domains = <&power RK3399_PD_ISP1>; 1781 rockchip,disable-mmu-reset; 1782 }; 1783 1784 hdmi_sound: hdmi-sound { 1785 compatible = "simple-audio-card"; 1786 simple-audio-card,format = "i2s"; 1787 simple-audio-card,mclk-fs = <256>; 1788 simple-audio-card,name = "hdmi-sound"; 1789 status = "disabled"; 1790 1791 simple-audio-card,cpu { 1792 sound-dai = <&i2s2>; 1793 }; 1794 simple-audio-card,codec { 1795 sound-dai = <&hdmi>; 1796 }; 1797 }; 1798 1799 hdmi: hdmi@ff940000 { 1800 compatible = "rockchip,rk3399-dw-hdmi"; 1801 reg = <0x0 0xff940000 0x0 0x20000>; 1802 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1803 clocks = <&cru PCLK_HDMI_CTRL>, 1804 <&cru SCLK_HDMI_SFR>, 1805 <&cru PLL_VPLL>, 1806 <&cru PCLK_VIO_GRF>, 1807 <&cru SCLK_HDMI_CEC>; 1808 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1809 power-domains = <&power RK3399_PD_HDCP>; 1810 reg-io-width = <4>; 1811 rockchip,grf = <&grf>; 1812 #sound-dai-cells = <0>; 1813 status = "disabled"; 1814 1815 ports { 1816 hdmi_in: port { 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 1820 hdmi_in_vopb: endpoint@0 { 1821 reg = <0>; 1822 remote-endpoint = <&vopb_out_hdmi>; 1823 }; 1824 hdmi_in_vopl: endpoint@1 { 1825 reg = <1>; 1826 remote-endpoint = <&vopl_out_hdmi>; 1827 }; 1828 }; 1829 }; 1830 }; 1831 1832 mipi_dsi: mipi@ff960000 { 1833 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1834 reg = <0x0 0xff960000 0x0 0x8000>; 1835 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1836 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1837 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1838 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1839 power-domains = <&power RK3399_PD_VIO>; 1840 resets = <&cru SRST_P_MIPI_DSI0>; 1841 reset-names = "apb"; 1842 rockchip,grf = <&grf>; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 1847 ports { 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 1851 mipi_in: port@0 { 1852 reg = <0>; 1853 #address-cells = <1>; 1854 #size-cells = <0>; 1855 1856 mipi_in_vopb: endpoint@0 { 1857 reg = <0>; 1858 remote-endpoint = <&vopb_out_mipi>; 1859 }; 1860 mipi_in_vopl: endpoint@1 { 1861 reg = <1>; 1862 remote-endpoint = <&vopl_out_mipi>; 1863 }; 1864 }; 1865 }; 1866 }; 1867 1868 mipi_dsi1: mipi@ff968000 { 1869 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1870 reg = <0x0 0xff968000 0x0 0x8000>; 1871 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1872 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1873 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1874 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1875 power-domains = <&power RK3399_PD_VIO>; 1876 resets = <&cru SRST_P_MIPI_DSI1>; 1877 reset-names = "apb"; 1878 rockchip,grf = <&grf>; 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 status = "disabled"; 1882 1883 ports { 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 1887 mipi1_in: port@0 { 1888 reg = <0>; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 1892 mipi1_in_vopb: endpoint@0 { 1893 reg = <0>; 1894 remote-endpoint = <&vopb_out_mipi1>; 1895 }; 1896 1897 mipi1_in_vopl: endpoint@1 { 1898 reg = <1>; 1899 remote-endpoint = <&vopl_out_mipi1>; 1900 }; 1901 }; 1902 }; 1903 }; 1904 1905 edp: edp@ff970000 { 1906 compatible = "rockchip,rk3399-edp"; 1907 reg = <0x0 0xff970000 0x0 0x8000>; 1908 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1909 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1910 clock-names = "dp", "pclk", "grf"; 1911 pinctrl-names = "default"; 1912 pinctrl-0 = <&edp_hpd>; 1913 power-domains = <&power RK3399_PD_EDP>; 1914 resets = <&cru SRST_P_EDP_CTRL>; 1915 reset-names = "dp"; 1916 rockchip,grf = <&grf>; 1917 status = "disabled"; 1918 1919 ports { 1920 #address-cells = <1>; 1921 #size-cells = <0>; 1922 edp_in: port@0 { 1923 reg = <0>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 1927 edp_in_vopb: endpoint@0 { 1928 reg = <0>; 1929 remote-endpoint = <&vopb_out_edp>; 1930 }; 1931 1932 edp_in_vopl: endpoint@1 { 1933 reg = <1>; 1934 remote-endpoint = <&vopl_out_edp>; 1935 }; 1936 }; 1937 }; 1938 }; 1939 1940 gpu: gpu@ff9a0000 { 1941 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1942 reg = <0x0 0xff9a0000 0x0 0x10000>; 1943 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1944 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1945 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1946 interrupt-names = "job", "mmu", "gpu"; 1947 clocks = <&cru ACLK_GPU>; 1948 #cooling-cells = <2>; 1949 power-domains = <&power RK3399_PD_GPU>; 1950 status = "disabled"; 1951 }; 1952 1953 pinctrl: pinctrl { 1954 compatible = "rockchip,rk3399-pinctrl"; 1955 rockchip,grf = <&grf>; 1956 rockchip,pmu = <&pmugrf>; 1957 #address-cells = <2>; 1958 #size-cells = <2>; 1959 ranges; 1960 1961 gpio0: gpio0@ff720000 { 1962 compatible = "rockchip,gpio-bank"; 1963 reg = <0x0 0xff720000 0x0 0x100>; 1964 clocks = <&pmucru PCLK_GPIO0_PMU>; 1965 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1966 1967 gpio-controller; 1968 #gpio-cells = <0x2>; 1969 1970 interrupt-controller; 1971 #interrupt-cells = <0x2>; 1972 }; 1973 1974 gpio1: gpio1@ff730000 { 1975 compatible = "rockchip,gpio-bank"; 1976 reg = <0x0 0xff730000 0x0 0x100>; 1977 clocks = <&pmucru PCLK_GPIO1_PMU>; 1978 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1979 1980 gpio-controller; 1981 #gpio-cells = <0x2>; 1982 1983 interrupt-controller; 1984 #interrupt-cells = <0x2>; 1985 }; 1986 1987 gpio2: gpio2@ff780000 { 1988 compatible = "rockchip,gpio-bank"; 1989 reg = <0x0 0xff780000 0x0 0x100>; 1990 clocks = <&cru PCLK_GPIO2>; 1991 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1992 1993 gpio-controller; 1994 #gpio-cells = <0x2>; 1995 1996 interrupt-controller; 1997 #interrupt-cells = <0x2>; 1998 }; 1999 2000 gpio3: gpio3@ff788000 { 2001 compatible = "rockchip,gpio-bank"; 2002 reg = <0x0 0xff788000 0x0 0x100>; 2003 clocks = <&cru PCLK_GPIO3>; 2004 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2005 2006 gpio-controller; 2007 #gpio-cells = <0x2>; 2008 2009 interrupt-controller; 2010 #interrupt-cells = <0x2>; 2011 }; 2012 2013 gpio4: gpio4@ff790000 { 2014 compatible = "rockchip,gpio-bank"; 2015 reg = <0x0 0xff790000 0x0 0x100>; 2016 clocks = <&cru PCLK_GPIO4>; 2017 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2018 2019 gpio-controller; 2020 #gpio-cells = <0x2>; 2021 2022 interrupt-controller; 2023 #interrupt-cells = <0x2>; 2024 }; 2025 2026 pcfg_pull_up: pcfg-pull-up { 2027 bias-pull-up; 2028 }; 2029 2030 pcfg_pull_down: pcfg-pull-down { 2031 bias-pull-down; 2032 }; 2033 2034 pcfg_pull_none: pcfg-pull-none { 2035 bias-disable; 2036 }; 2037 2038 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2039 bias-disable; 2040 drive-strength = <12>; 2041 }; 2042 2043 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2044 bias-disable; 2045 drive-strength = <13>; 2046 }; 2047 2048 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2049 bias-disable; 2050 drive-strength = <18>; 2051 }; 2052 2053 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2054 bias-disable; 2055 drive-strength = <20>; 2056 }; 2057 2058 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2059 bias-pull-up; 2060 drive-strength = <2>; 2061 }; 2062 2063 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2064 bias-pull-up; 2065 drive-strength = <8>; 2066 }; 2067 2068 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2069 bias-pull-up; 2070 drive-strength = <18>; 2071 }; 2072 2073 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2074 bias-pull-up; 2075 drive-strength = <20>; 2076 }; 2077 2078 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2079 bias-pull-down; 2080 drive-strength = <4>; 2081 }; 2082 2083 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2084 bias-pull-down; 2085 drive-strength = <8>; 2086 }; 2087 2088 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2089 bias-pull-down; 2090 drive-strength = <12>; 2091 }; 2092 2093 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2094 bias-pull-down; 2095 drive-strength = <18>; 2096 }; 2097 2098 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2099 bias-pull-down; 2100 drive-strength = <20>; 2101 }; 2102 2103 pcfg_output_high: pcfg-output-high { 2104 output-high; 2105 }; 2106 2107 pcfg_output_low: pcfg-output-low { 2108 output-low; 2109 }; 2110 2111 clock { 2112 clk_32k: clk-32k { 2113 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2114 }; 2115 }; 2116 2117 edp { 2118 edp_hpd: edp-hpd { 2119 rockchip,pins = 2120 <4 RK_PC7 2 &pcfg_pull_none>; 2121 }; 2122 }; 2123 2124 gmac { 2125 rgmii_pins: rgmii-pins { 2126 rockchip,pins = 2127 /* mac_txclk */ 2128 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2129 /* mac_rxclk */ 2130 <3 RK_PB6 1 &pcfg_pull_none>, 2131 /* mac_mdio */ 2132 <3 RK_PB5 1 &pcfg_pull_none>, 2133 /* mac_txen */ 2134 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2135 /* mac_clk */ 2136 <3 RK_PB3 1 &pcfg_pull_none>, 2137 /* mac_rxdv */ 2138 <3 RK_PB1 1 &pcfg_pull_none>, 2139 /* mac_mdc */ 2140 <3 RK_PB0 1 &pcfg_pull_none>, 2141 /* mac_rxd1 */ 2142 <3 RK_PA7 1 &pcfg_pull_none>, 2143 /* mac_rxd0 */ 2144 <3 RK_PA6 1 &pcfg_pull_none>, 2145 /* mac_txd1 */ 2146 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2147 /* mac_txd0 */ 2148 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2149 /* mac_rxd3 */ 2150 <3 RK_PA3 1 &pcfg_pull_none>, 2151 /* mac_rxd2 */ 2152 <3 RK_PA2 1 &pcfg_pull_none>, 2153 /* mac_txd3 */ 2154 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2155 /* mac_txd2 */ 2156 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2157 }; 2158 2159 rmii_pins: rmii-pins { 2160 rockchip,pins = 2161 /* mac_mdio */ 2162 <3 RK_PB5 1 &pcfg_pull_none>, 2163 /* mac_txen */ 2164 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2165 /* mac_clk */ 2166 <3 RK_PB3 1 &pcfg_pull_none>, 2167 /* mac_rxer */ 2168 <3 RK_PB2 1 &pcfg_pull_none>, 2169 /* mac_rxdv */ 2170 <3 RK_PB1 1 &pcfg_pull_none>, 2171 /* mac_mdc */ 2172 <3 RK_PB0 1 &pcfg_pull_none>, 2173 /* mac_rxd1 */ 2174 <3 RK_PA7 1 &pcfg_pull_none>, 2175 /* mac_rxd0 */ 2176 <3 RK_PA6 1 &pcfg_pull_none>, 2177 /* mac_txd1 */ 2178 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2179 /* mac_txd0 */ 2180 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2181 }; 2182 }; 2183 2184 i2c0 { 2185 i2c0_xfer: i2c0-xfer { 2186 rockchip,pins = 2187 <1 RK_PB7 2 &pcfg_pull_none>, 2188 <1 RK_PC0 2 &pcfg_pull_none>; 2189 }; 2190 }; 2191 2192 i2c1 { 2193 i2c1_xfer: i2c1-xfer { 2194 rockchip,pins = 2195 <4 RK_PA2 1 &pcfg_pull_none>, 2196 <4 RK_PA1 1 &pcfg_pull_none>; 2197 }; 2198 }; 2199 2200 i2c2 { 2201 i2c2_xfer: i2c2-xfer { 2202 rockchip,pins = 2203 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2204 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2205 }; 2206 }; 2207 2208 i2c3 { 2209 i2c3_xfer: i2c3-xfer { 2210 rockchip,pins = 2211 <4 RK_PC1 1 &pcfg_pull_none>, 2212 <4 RK_PC0 1 &pcfg_pull_none>; 2213 }; 2214 }; 2215 2216 i2c4 { 2217 i2c4_xfer: i2c4-xfer { 2218 rockchip,pins = 2219 <1 RK_PB4 1 &pcfg_pull_none>, 2220 <1 RK_PB3 1 &pcfg_pull_none>; 2221 }; 2222 }; 2223 2224 i2c5 { 2225 i2c5_xfer: i2c5-xfer { 2226 rockchip,pins = 2227 <3 RK_PB3 2 &pcfg_pull_none>, 2228 <3 RK_PB2 2 &pcfg_pull_none>; 2229 }; 2230 }; 2231 2232 i2c6 { 2233 i2c6_xfer: i2c6-xfer { 2234 rockchip,pins = 2235 <2 RK_PB2 2 &pcfg_pull_none>, 2236 <2 RK_PB1 2 &pcfg_pull_none>; 2237 }; 2238 }; 2239 2240 i2c7 { 2241 i2c7_xfer: i2c7-xfer { 2242 rockchip,pins = 2243 <2 RK_PB0 2 &pcfg_pull_none>, 2244 <2 RK_PA7 2 &pcfg_pull_none>; 2245 }; 2246 }; 2247 2248 i2c8 { 2249 i2c8_xfer: i2c8-xfer { 2250 rockchip,pins = 2251 <1 RK_PC5 1 &pcfg_pull_none>, 2252 <1 RK_PC4 1 &pcfg_pull_none>; 2253 }; 2254 }; 2255 2256 i2s0 { 2257 i2s0_2ch_bus: i2s0-2ch-bus { 2258 rockchip,pins = 2259 <3 RK_PD0 1 &pcfg_pull_none>, 2260 <3 RK_PD1 1 &pcfg_pull_none>, 2261 <3 RK_PD2 1 &pcfg_pull_none>, 2262 <3 RK_PD3 1 &pcfg_pull_none>, 2263 <3 RK_PD7 1 &pcfg_pull_none>, 2264 <4 RK_PA0 1 &pcfg_pull_none>; 2265 }; 2266 2267 i2s0_8ch_bus: i2s0-8ch-bus { 2268 rockchip,pins = 2269 <3 RK_PD0 1 &pcfg_pull_none>, 2270 <3 RK_PD1 1 &pcfg_pull_none>, 2271 <3 RK_PD2 1 &pcfg_pull_none>, 2272 <3 RK_PD3 1 &pcfg_pull_none>, 2273 <3 RK_PD4 1 &pcfg_pull_none>, 2274 <3 RK_PD5 1 &pcfg_pull_none>, 2275 <3 RK_PD6 1 &pcfg_pull_none>, 2276 <3 RK_PD7 1 &pcfg_pull_none>, 2277 <4 RK_PA0 1 &pcfg_pull_none>; 2278 }; 2279 }; 2280 2281 i2s1 { 2282 i2s1_2ch_bus: i2s1-2ch-bus { 2283 rockchip,pins = 2284 <4 RK_PA3 1 &pcfg_pull_none>, 2285 <4 RK_PA4 1 &pcfg_pull_none>, 2286 <4 RK_PA5 1 &pcfg_pull_none>, 2287 <4 RK_PA6 1 &pcfg_pull_none>, 2288 <4 RK_PA7 1 &pcfg_pull_none>; 2289 }; 2290 }; 2291 2292 sdio0 { 2293 sdio0_bus1: sdio0-bus1 { 2294 rockchip,pins = 2295 <2 RK_PC4 1 &pcfg_pull_up>; 2296 }; 2297 2298 sdio0_bus4: sdio0-bus4 { 2299 rockchip,pins = 2300 <2 RK_PC4 1 &pcfg_pull_up>, 2301 <2 RK_PC5 1 &pcfg_pull_up>, 2302 <2 RK_PC6 1 &pcfg_pull_up>, 2303 <2 RK_PC7 1 &pcfg_pull_up>; 2304 }; 2305 2306 sdio0_cmd: sdio0-cmd { 2307 rockchip,pins = 2308 <2 RK_PD0 1 &pcfg_pull_up>; 2309 }; 2310 2311 sdio0_clk: sdio0-clk { 2312 rockchip,pins = 2313 <2 RK_PD1 1 &pcfg_pull_none>; 2314 }; 2315 2316 sdio0_cd: sdio0-cd { 2317 rockchip,pins = 2318 <2 RK_PD2 1 &pcfg_pull_up>; 2319 }; 2320 2321 sdio0_pwr: sdio0-pwr { 2322 rockchip,pins = 2323 <2 RK_PD3 1 &pcfg_pull_up>; 2324 }; 2325 2326 sdio0_bkpwr: sdio0-bkpwr { 2327 rockchip,pins = 2328 <2 RK_PD4 1 &pcfg_pull_up>; 2329 }; 2330 2331 sdio0_wp: sdio0-wp { 2332 rockchip,pins = 2333 <0 RK_PA3 1 &pcfg_pull_up>; 2334 }; 2335 2336 sdio0_int: sdio0-int { 2337 rockchip,pins = 2338 <0 RK_PA4 1 &pcfg_pull_up>; 2339 }; 2340 }; 2341 2342 sdmmc { 2343 sdmmc_bus1: sdmmc-bus1 { 2344 rockchip,pins = 2345 <4 RK_PB0 1 &pcfg_pull_up>; 2346 }; 2347 2348 sdmmc_bus4: sdmmc-bus4 { 2349 rockchip,pins = 2350 <4 RK_PB0 1 &pcfg_pull_up>, 2351 <4 RK_PB1 1 &pcfg_pull_up>, 2352 <4 RK_PB2 1 &pcfg_pull_up>, 2353 <4 RK_PB3 1 &pcfg_pull_up>; 2354 }; 2355 2356 sdmmc_clk: sdmmc-clk { 2357 rockchip,pins = 2358 <4 RK_PB4 1 &pcfg_pull_none>; 2359 }; 2360 2361 sdmmc_cmd: sdmmc-cmd { 2362 rockchip,pins = 2363 <4 RK_PB5 1 &pcfg_pull_up>; 2364 }; 2365 2366 sdmmc_cd: sdmmc-cd { 2367 rockchip,pins = 2368 <0 RK_PA7 1 &pcfg_pull_up>; 2369 }; 2370 2371 sdmmc_wp: sdmmc-wp { 2372 rockchip,pins = 2373 <0 RK_PB0 1 &pcfg_pull_up>; 2374 }; 2375 }; 2376 2377 suspend { 2378 ap_pwroff: ap-pwroff { 2379 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2380 }; 2381 2382 ddrio_pwroff: ddrio-pwroff { 2383 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2384 }; 2385 }; 2386 2387 spdif { 2388 spdif_bus: spdif-bus { 2389 rockchip,pins = 2390 <4 RK_PC5 1 &pcfg_pull_none>; 2391 }; 2392 2393 spdif_bus_1: spdif-bus-1 { 2394 rockchip,pins = 2395 <3 RK_PC0 3 &pcfg_pull_none>; 2396 }; 2397 }; 2398 2399 spi0 { 2400 spi0_clk: spi0-clk { 2401 rockchip,pins = 2402 <3 RK_PA6 2 &pcfg_pull_up>; 2403 }; 2404 spi0_cs0: spi0-cs0 { 2405 rockchip,pins = 2406 <3 RK_PA7 2 &pcfg_pull_up>; 2407 }; 2408 spi0_cs1: spi0-cs1 { 2409 rockchip,pins = 2410 <3 RK_PB0 2 &pcfg_pull_up>; 2411 }; 2412 spi0_tx: spi0-tx { 2413 rockchip,pins = 2414 <3 RK_PA5 2 &pcfg_pull_up>; 2415 }; 2416 spi0_rx: spi0-rx { 2417 rockchip,pins = 2418 <3 RK_PA4 2 &pcfg_pull_up>; 2419 }; 2420 }; 2421 2422 spi1 { 2423 spi1_clk: spi1-clk { 2424 rockchip,pins = 2425 <1 RK_PB1 2 &pcfg_pull_up>; 2426 }; 2427 spi1_cs0: spi1-cs0 { 2428 rockchip,pins = 2429 <1 RK_PB2 2 &pcfg_pull_up>; 2430 }; 2431 spi1_rx: spi1-rx { 2432 rockchip,pins = 2433 <1 RK_PA7 2 &pcfg_pull_up>; 2434 }; 2435 spi1_tx: spi1-tx { 2436 rockchip,pins = 2437 <1 RK_PB0 2 &pcfg_pull_up>; 2438 }; 2439 }; 2440 2441 spi2 { 2442 spi2_clk: spi2-clk { 2443 rockchip,pins = 2444 <2 RK_PB3 1 &pcfg_pull_up>; 2445 }; 2446 spi2_cs0: spi2-cs0 { 2447 rockchip,pins = 2448 <2 RK_PB4 1 &pcfg_pull_up>; 2449 }; 2450 spi2_rx: spi2-rx { 2451 rockchip,pins = 2452 <2 RK_PB1 1 &pcfg_pull_up>; 2453 }; 2454 spi2_tx: spi2-tx { 2455 rockchip,pins = 2456 <2 RK_PB2 1 &pcfg_pull_up>; 2457 }; 2458 }; 2459 2460 spi3 { 2461 spi3_clk: spi3-clk { 2462 rockchip,pins = 2463 <1 RK_PC1 1 &pcfg_pull_up>; 2464 }; 2465 spi3_cs0: spi3-cs0 { 2466 rockchip,pins = 2467 <1 RK_PC2 1 &pcfg_pull_up>; 2468 }; 2469 spi3_rx: spi3-rx { 2470 rockchip,pins = 2471 <1 RK_PB7 1 &pcfg_pull_up>; 2472 }; 2473 spi3_tx: spi3-tx { 2474 rockchip,pins = 2475 <1 RK_PC0 1 &pcfg_pull_up>; 2476 }; 2477 }; 2478 2479 spi4 { 2480 spi4_clk: spi4-clk { 2481 rockchip,pins = 2482 <3 RK_PA2 2 &pcfg_pull_up>; 2483 }; 2484 spi4_cs0: spi4-cs0 { 2485 rockchip,pins = 2486 <3 RK_PA3 2 &pcfg_pull_up>; 2487 }; 2488 spi4_rx: spi4-rx { 2489 rockchip,pins = 2490 <3 RK_PA0 2 &pcfg_pull_up>; 2491 }; 2492 spi4_tx: spi4-tx { 2493 rockchip,pins = 2494 <3 RK_PA1 2 &pcfg_pull_up>; 2495 }; 2496 }; 2497 2498 spi5 { 2499 spi5_clk: spi5-clk { 2500 rockchip,pins = 2501 <2 RK_PC6 2 &pcfg_pull_up>; 2502 }; 2503 spi5_cs0: spi5-cs0 { 2504 rockchip,pins = 2505 <2 RK_PC7 2 &pcfg_pull_up>; 2506 }; 2507 spi5_rx: spi5-rx { 2508 rockchip,pins = 2509 <2 RK_PC4 2 &pcfg_pull_up>; 2510 }; 2511 spi5_tx: spi5-tx { 2512 rockchip,pins = 2513 <2 RK_PC5 2 &pcfg_pull_up>; 2514 }; 2515 }; 2516 2517 testclk { 2518 test_clkout0: test-clkout0 { 2519 rockchip,pins = 2520 <0 RK_PA0 1 &pcfg_pull_none>; 2521 }; 2522 2523 test_clkout1: test-clkout1 { 2524 rockchip,pins = 2525 <2 RK_PD1 2 &pcfg_pull_none>; 2526 }; 2527 2528 test_clkout2: test-clkout2 { 2529 rockchip,pins = 2530 <0 RK_PB0 3 &pcfg_pull_none>; 2531 }; 2532 }; 2533 2534 tsadc { 2535 otp_pin: otp-pin { 2536 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2537 }; 2538 2539 otp_out: otp-out { 2540 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2541 }; 2542 }; 2543 2544 uart0 { 2545 uart0_xfer: uart0-xfer { 2546 rockchip,pins = 2547 <2 RK_PC0 1 &pcfg_pull_up>, 2548 <2 RK_PC1 1 &pcfg_pull_none>; 2549 }; 2550 2551 uart0_cts: uart0-cts { 2552 rockchip,pins = 2553 <2 RK_PC2 1 &pcfg_pull_none>; 2554 }; 2555 2556 uart0_rts: uart0-rts { 2557 rockchip,pins = 2558 <2 RK_PC3 1 &pcfg_pull_none>; 2559 }; 2560 }; 2561 2562 uart1 { 2563 uart1_xfer: uart1-xfer { 2564 rockchip,pins = 2565 <3 RK_PB4 2 &pcfg_pull_up>, 2566 <3 RK_PB5 2 &pcfg_pull_none>; 2567 }; 2568 }; 2569 2570 uart2a { 2571 uart2a_xfer: uart2a-xfer { 2572 rockchip,pins = 2573 <4 RK_PB0 2 &pcfg_pull_up>, 2574 <4 RK_PB1 2 &pcfg_pull_none>; 2575 }; 2576 }; 2577 2578 uart2b { 2579 uart2b_xfer: uart2b-xfer { 2580 rockchip,pins = 2581 <4 RK_PC0 2 &pcfg_pull_up>, 2582 <4 RK_PC1 2 &pcfg_pull_none>; 2583 }; 2584 }; 2585 2586 uart2c { 2587 uart2c_xfer: uart2c-xfer { 2588 rockchip,pins = 2589 <4 RK_PC3 1 &pcfg_pull_up>, 2590 <4 RK_PC4 1 &pcfg_pull_none>; 2591 }; 2592 }; 2593 2594 uart3 { 2595 uart3_xfer: uart3-xfer { 2596 rockchip,pins = 2597 <3 RK_PB6 2 &pcfg_pull_up>, 2598 <3 RK_PB7 2 &pcfg_pull_none>; 2599 }; 2600 2601 uart3_cts: uart3-cts { 2602 rockchip,pins = 2603 <3 RK_PC0 2 &pcfg_pull_none>; 2604 }; 2605 2606 uart3_rts: uart3-rts { 2607 rockchip,pins = 2608 <3 RK_PC1 2 &pcfg_pull_none>; 2609 }; 2610 }; 2611 2612 uart4 { 2613 uart4_xfer: uart4-xfer { 2614 rockchip,pins = 2615 <1 RK_PA7 1 &pcfg_pull_up>, 2616 <1 RK_PB0 1 &pcfg_pull_none>; 2617 }; 2618 }; 2619 2620 uarthdcp { 2621 uarthdcp_xfer: uarthdcp-xfer { 2622 rockchip,pins = 2623 <4 RK_PC5 2 &pcfg_pull_up>, 2624 <4 RK_PC6 2 &pcfg_pull_none>; 2625 }; 2626 }; 2627 2628 pwm0 { 2629 pwm0_pin: pwm0-pin { 2630 rockchip,pins = 2631 <4 RK_PC2 1 &pcfg_pull_none>; 2632 }; 2633 2634 pwm0_pin_pull_down: pwm0-pin-pull-down { 2635 rockchip,pins = 2636 <4 RK_PC2 1 &pcfg_pull_down>; 2637 }; 2638 2639 vop0_pwm_pin: vop0-pwm-pin { 2640 rockchip,pins = 2641 <4 RK_PC2 2 &pcfg_pull_none>; 2642 }; 2643 2644 vop1_pwm_pin: vop1-pwm-pin { 2645 rockchip,pins = 2646 <4 RK_PC2 3 &pcfg_pull_none>; 2647 }; 2648 }; 2649 2650 pwm1 { 2651 pwm1_pin: pwm1-pin { 2652 rockchip,pins = 2653 <4 RK_PC6 1 &pcfg_pull_none>; 2654 }; 2655 2656 pwm1_pin_pull_down: pwm1-pin-pull-down { 2657 rockchip,pins = 2658 <4 RK_PC6 1 &pcfg_pull_down>; 2659 }; 2660 }; 2661 2662 pwm2 { 2663 pwm2_pin: pwm2-pin { 2664 rockchip,pins = 2665 <1 RK_PC3 1 &pcfg_pull_none>; 2666 }; 2667 2668 pwm2_pin_pull_down: pwm2-pin-pull-down { 2669 rockchip,pins = 2670 <1 RK_PC3 1 &pcfg_pull_down>; 2671 }; 2672 }; 2673 2674 pwm3a { 2675 pwm3a_pin: pwm3a-pin { 2676 rockchip,pins = 2677 <0 RK_PA6 1 &pcfg_pull_none>; 2678 }; 2679 }; 2680 2681 pwm3b { 2682 pwm3b_pin: pwm3b-pin { 2683 rockchip,pins = 2684 <1 RK_PB6 1 &pcfg_pull_none>; 2685 }; 2686 }; 2687 2688 hdmi { 2689 hdmi_i2c_xfer: hdmi-i2c-xfer { 2690 rockchip,pins = 2691 <4 RK_PC1 3 &pcfg_pull_none>, 2692 <4 RK_PC0 3 &pcfg_pull_none>; 2693 }; 2694 2695 hdmi_cec: hdmi-cec { 2696 rockchip,pins = 2697 <4 RK_PC7 1 &pcfg_pull_none>; 2698 }; 2699 }; 2700 2701 pcie { 2702 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2703 rockchip,pins = 2704 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2705 }; 2706 2707 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2708 rockchip,pins = 2709 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2710 }; 2711 }; 2712 2713 }; 2714 }; 2715
Indexes created Thu Oct 02 10:09:58 GMT 2025