1 /* $NetBSD: tdvfb.c,v 1.11 2023/08/01 20:50:11 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * A console driver for 3Dfx Voodoo2 (CVG) and 3Dfx Voodoo Graphics (SST-1). 33 * 34 * 3Dfx Glide 2.x source code, Linux driver by Ghozlane Toumi, and 35 * "Voodoo2 Graphics Engine for 3D Game Acceleration" document were used as 36 * reference. wscons attachment code based mostly on genfb by Michael 37 * Lorenz. 38 * 39 * This driver currently only support boards with ICS GENDAC (which seems to 40 * be most popular, however at least two different DACs were used with CVG). 41 * 42 * TODO (in no particular order): 43 * - Finally fix 16-bit depth handling on big-endian machines. 44 * - Expose card to userspace through /dev/3dfx compatible device file 45 * (for Glide). 46 * - Allow mmap'ing of registers through wscons access op. 47 * - Complete wscons emul ops acceleration support. 48 * - Add support for others DACs (need hardware). 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: tdvfb.c,v 1.11 2023/08/01 20:50:11 andvar Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/endian.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 #include <dev/pci/pciio.h> 64 65 #include <dev/pci/tdvfbreg.h> 66 #include <dev/pci/tdvfbvar.h> 67 68 #include <dev/videomode/videomode.h> 69 #include <dev/pci/wsdisplay_pci.h> 70 71 #include "opt_wsemul.h" 72 #include "opt_tdvfb.h" 73 74 #define MAXLOOP 4096 75 /* #define TDVFB_DEBUG 1 */ 76 77 static int tdvfb_match(device_t, cfdata_t, void *); 78 static void tdvfb_attach(device_t, device_t, void *); 79 80 static uint32_t tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg); 81 static void tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, 82 uint32_t val); 83 static void tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, 84 uint32_t bits); 85 static void tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, 86 uint32_t bits); 87 static uint8_t tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg); 88 static void tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, 89 uint32_t val); 90 static void tdvfb_wait(struct tdvfb_softc *sc); 91 92 static bool tdvfb_init(struct tdvfb_softc *sc); 93 static void tdvfb_fbiinit_defaults(struct tdvfb_softc *sc); 94 static size_t tdvfb_mem_size(struct tdvfb_softc *sc); 95 96 static bool tdvfb_videomode_set(struct tdvfb_softc *sc); 97 static void tdvfb_videomode_dac(struct tdvfb_softc *sc); 98 99 static bool tdvfb_gendac_detect(struct tdvfb_softc *sc); 100 static struct tdvfb_dac_timing tdvfb_gendac_calc_pll(int freq); 101 static void tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 102 struct tdvfb_dac_timing *timing); 103 static void tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 104 struct tdvfb_dac_timing *timing); 105 106 static paddr_t tdvfb_mmap(void *v, void *vs, off_t offset, int prot); 107 static int tdvfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 108 struct lwp *l); 109 static void tdvfb_init_screen(void *cookie, struct vcons_screen *scr, 110 int existing, long *defattr); 111 static void tdvfb_init_palette(struct tdvfb_softc *sc); 112 /* blitter support */ 113 static void tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, 114 int he, uint32_t color); 115 static void tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, 116 int yd, int wi, int he); 117 /* accelerated raster ops */ 118 static void tdvfb_eraserows(void *cookie, int row, int nrows, 119 long fillattr); 120 static void tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows); 121 122 CFATTACH_DECL_NEW(tdvfb, sizeof(struct tdvfb_softc), 123 tdvfb_match, tdvfb_attach, NULL, NULL); 124 125 struct wsdisplay_accessops tdvfb_accessops = { 126 tdvfb_ioctl, 127 tdvfb_mmap, 128 NULL, /* alloc_screen */ 129 NULL, /* free_screen */ 130 NULL, /* show_screen */ 131 NULL, /* load_font */ 132 NULL, /* pollc */ 133 NULL /* scroll */ 134 }; 135 136 static int 137 tdvfb_match(device_t parent, cfdata_t match, void *aux) 138 { 139 const struct pci_attach_args *pa = (const struct pci_attach_args *)aux; 140 141 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 142 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2)) 143 return 100; 144 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 145 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO)) 146 return 100; 147 148 return 0; 149 } 150 151 static void 152 tdvfb_attach(device_t parent, device_t self, void *aux) 153 { 154 struct tdvfb_softc *sc = device_private(self); 155 struct wsemuldisplaydev_attach_args ws_aa; 156 struct rasops_info *ri; 157 const struct pci_attach_args *pa = aux; 158 pcireg_t screg; 159 bool console; 160 long defattr; 161 162 #ifdef TDVFB_CONSOLE 163 console = true; 164 #else 165 console = false; 166 #endif 167 168 sc->sc_pc = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag; 170 sc->sc_dev = self; 171 172 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2) 173 sc->sc_voodootype = TDV_VOODOO_2; 174 else 175 sc->sc_voodootype = TDV_VOODOO_1; 176 177 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 178 PCI_COMMAND_STATUS_REG); 179 screg |= PCI_COMMAND_MEM_ENABLE; 180 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 181 screg); 182 183 pci_aprint_devinfo(pa, NULL); 184 185 /* map the BAR */ 186 if (pci_mapreg_map(pa, TDV_MM_BAR, PCI_MAPREG_TYPE_MEM, 187 BUS_SPACE_MAP_LINEAR, &sc->sc_cvgt, &sc->sc_cvgh, 188 &sc->sc_cvg_pa, 0) != 0 ) { 189 aprint_error_dev(sc->sc_dev, "unable to map CVG BAR"); 190 return; 191 } 192 193 /* Map the framebuffer. */ 194 if (bus_space_subregion(sc->sc_cvgt, sc->sc_cvgh, TDV_OFF_FB, 195 TDV_FB_SIZE, &sc->sc_fbh)) { 196 aprint_error_dev(sc->sc_dev, "unable to map the framebuffer"); 197 } 198 199 aprint_normal_dev(sc->sc_dev, "registers at 0x%08x, fb at 0x%08x\n", 200 (uint32_t) sc->sc_cvg_pa, (uint32_t) sc->sc_cvg_pa + TDV_OFF_FB); 201 202 /* Do the low level setup. */ 203 if (!tdvfb_init(sc)) { 204 aprint_error_dev(sc->sc_dev, "could not initialize CVG\n"); 205 return; 206 } 207 208 /* 209 * The card is alive now, let's check how much framebuffer memory 210 * do we have. 211 */ 212 sc->sc_memsize = tdvfb_mem_size(sc); 213 214 aprint_normal_dev(sc->sc_dev, "%zu MB framebuffer memory present\n", 215 sc->sc_memsize / 1024 / 1024); 216 217 /* Select video mode, 800x600 32bpp 60Hz by default... */ 218 sc->sc_width = 800; 219 sc->sc_height = 600; 220 #if BYTE_ORDER == BIG_ENDIAN 221 sc->sc_bpp = 32; /* XXX: 16 would allow blitter use. */ 222 #else 223 sc->sc_bpp = 16; 224 #endif 225 sc->sc_linebytes = 1024 * (sc->sc_bpp / 8); 226 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, sc->sc_height, 60); 227 228 aprint_normal_dev(sc->sc_dev, "setting %dx%d %d bpp resolution\n", 229 sc->sc_width, sc->sc_height, sc->sc_bpp); 230 231 tdvfb_videomode_set(sc); 232 233 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 234 "default", 235 0, 0, 236 NULL, 237 8, 16, 238 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 239 NULL 240 }; 241 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 242 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 243 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 244 245 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 246 &tdvfb_accessops); 247 sc->vd.init_screen = tdvfb_init_screen; 248 249 ri = &sc->sc_console_screen.scr_ri; 250 251 tdvfb_init_palette(sc); 252 253 if (console) { 254 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 255 &defattr); 256 257 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC | 258 VCONS_DONT_READ; 259 vcons_redraw_screen(&sc->sc_console_screen); 260 261 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 262 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 263 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 264 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 265 266 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 267 defattr); 268 vcons_replay_msgbuf(&sc->sc_console_screen); 269 } else { 270 if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 271 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 272 &defattr); 273 } else 274 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 275 } 276 277 ws_aa.console = console; 278 ws_aa.scrdata = &sc->sc_screenlist; 279 ws_aa.accessops = &tdvfb_accessops; 280 ws_aa.accesscookie = &sc->vd; 281 282 config_found(sc->sc_dev, &ws_aa, wsemuldisplaydevprint, CFARGS_NONE); 283 } 284 285 static void 286 tdvfb_init_palette(struct tdvfb_softc *sc) 287 { 288 int i, j; 289 290 j = 0; 291 for (i = 0; i < 256; i++) { 292 sc->sc_cmap_red[i] = rasops_cmap[j]; 293 sc->sc_cmap_green[i] = rasops_cmap[j + 1]; 294 sc->sc_cmap_blue[i] = rasops_cmap[j + 2]; 295 j += 3; 296 } 297 } 298 299 static void 300 tdvfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 301 long *defattr) 302 { 303 struct tdvfb_softc *sc = cookie; 304 struct rasops_info *ri = &scr->scr_ri; 305 306 wsfont_init(); 307 308 ri->ri_depth = sc->sc_bpp; 309 ri->ri_width = sc->sc_width; 310 ri->ri_height = sc->sc_height; 311 ri->ri_stride = sc->sc_linebytes; 312 ri->ri_flg = RI_CENTER; 313 314 #if BYTE_ORDER == BIG_ENDIAN 315 #if 0 /* XXX: not yet :( */ 316 if (sc->sc_bpp == 16) 317 ri->ri_flg |= RI_BITSWAP; 318 #endif 319 #endif 320 321 ri->ri_bits = (char *) bus_space_vaddr(sc->sc_cvgt, sc->sc_fbh); 322 #ifdef TDVFB_DEBUG 323 aprint_normal_dev(sc->sc_dev, "fb handle: %lx, ri_bits: %p\n", sc->sc_fbh, ri->ri_bits); 324 #endif /* TDVFB_DEBUG */ 325 326 scr->scr_flags |= VCONS_DONT_READ; 327 328 rasops_init(ri, 0, 0); 329 ri->ri_caps = WSSCREEN_WSCOLORS; 330 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 331 sc->sc_width / ri->ri_font->fontwidth); 332 333 ri->ri_hw = scr; 334 335 /* If we are a Voodoo2 and running in 16 bits try to use blitter. */ 336 if ((sc->sc_voodootype == TDV_VOODOO_2) && (sc->sc_bpp == 16)) { 337 aprint_normal_dev(sc->sc_dev, "using CVG blitter\n"); 338 ri->ri_ops.eraserows = tdvfb_eraserows; 339 ri->ri_ops.copyrows = tdvfb_copyrows; 340 } 341 } 342 343 static bool 344 tdvfb_videomode_set(struct tdvfb_softc *sc) 345 { 346 uint32_t fbiinit1, fbiinit5, fbiinit6, lfbmode; 347 uint16_t vbackporch, vsyncon, vsyncoff; 348 uint16_t hbackporch, hsyncon, hsyncoff; 349 uint16_t yheight, xwidth; 350 351 fbiinit5 = fbiinit6 = 0; /* XXX gcc */ 352 353 yheight = sc->sc_videomode->vdisplay; 354 xwidth = sc->sc_videomode->hdisplay; 355 356 vbackporch = sc->sc_videomode->vtotal - sc->sc_videomode->vsync_end; 357 hbackporch = sc->sc_videomode->htotal - sc->sc_videomode->hsync_end; 358 359 vsyncon = sc->sc_videomode->vsync_end - sc->sc_videomode->vsync_start; 360 hsyncon = sc->sc_videomode->hsync_end - sc->sc_videomode->hsync_start; 361 362 vsyncoff = sc->sc_videomode->vtotal - vsyncon; 363 hsyncoff = sc->sc_videomode->htotal - hsyncon; 364 #ifdef TDVFB_DEBUG 365 aprint_normal_dev(sc->sc_dev, 366 "xy %d %d hbp %d vbp %d, hson %d, hsoff %d, vson %d, vsoff %d\n", 367 xwidth, yheight, hbackporch, vbackporch, hsyncon, hsyncoff, 368 vsyncon, vsyncoff); 369 #endif /* TDVFB_DEBUG */ 370 371 sc->vid_timing = tdvfb_gendac_calc_pll(sc->sc_videomode->dot_clock); 372 373 if(sc->sc_voodootype == TDV_VOODOO_2) 374 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64 * 2; 375 else 376 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64; 377 378 tdvfb_cvg_write(sc, TDV_OFF_NOPCMD, 0); 379 tdvfb_wait(sc); 380 381 /* enable writing to fbiinit regs, reset, disable DRAM refresh */ 382 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 383 TDV_INITENABLE_EN_INIT); 384 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 385 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 386 TDV_FBIINIT0_FIFO_RST); 387 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 388 tdvfb_wait(sc); 389 390 /* program video timings into CVG/SST-1*/ 391 tdvfb_cvg_write(sc, TDV_OFF_VDIMENSIONS, yheight << 16 | (xwidth - 1)); 392 tdvfb_cvg_write(sc, TDV_OFF_BACKPORCH, vbackporch << 16 | 393 (hbackporch - 2)); 394 tdvfb_cvg_write(sc, TDV_OFF_HSYNC, hsyncoff << 16 | (hsyncon - 1)); 395 tdvfb_cvg_write(sc, TDV_OFF_VSYNC, vsyncoff << 16 | vsyncon); 396 397 tdvfb_videomode_dac(sc); 398 399 fbiinit1 = ((tdvfb_cvg_read(sc, TDV_OFF_FBIINIT1) & 400 TDV_FBIINIT1_VIDMASK) | 401 TDV_FBIINIT1_DR_DATA | 402 TDV_FBIINIT1_DR_BLANKING | 403 TDV_FBIINIT1_DR_HVSYNC | 404 TDV_FBIINIT1_DR_DCLK | 405 TDV_FBIINIT1_IN_VCLK_2X ); 406 407 if (sc->sc_voodootype == TDV_VOODOO_2) { 408 fbiinit1 |= ((sc->sc_x_tiles & 0x20) >> 5) 409 << TDV_FBIINIT1_TILES_X_MSB | ((sc->sc_x_tiles & 0x1e) >> 1) 410 << TDV_FBIINIT1_TILES_X; 411 fbiinit6 = (sc->sc_x_tiles & 0x1) << TDV_FBIINIT6_TILES_X_LSB; 412 } else 413 fbiinit1 |= sc->sc_x_tiles << TDV_FBIINIT1_TILES_X; 414 415 fbiinit1 |= TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC; 416 417 if (sc->sc_voodootype == TDV_VOODOO_2) { 418 fbiinit5 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT5) 419 & TDV_FBIINIT5_VIDMASK; 420 if (sc->sc_videomode->flags & VID_PHSYNC) 421 fbiinit5 |= TDV_FBIINIT5_PHSYNC; 422 if (sc->sc_videomode->flags & VID_PVSYNC) 423 fbiinit5 |= TDV_FBIINIT5_PVSYNC; 424 } 425 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 426 if (sc->sc_voodootype == TDV_VOODOO_2) { 427 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 428 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT5, fbiinit5); 429 } 430 tdvfb_wait(sc); 431 432 /* unreset, enable DRAM refresh */ 433 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 434 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 435 TDV_FBIINIT0_FIFO_RST); 436 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 437 /* disable access to FBIINIT regs */ 438 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 439 TDV_INITENABLE_EN_FIFO); 440 tdvfb_wait(sc); 441 442 if (sc->sc_bpp == 16) 443 lfbmode = TDV_LFBMODE_565; 444 else if (sc->sc_bpp == 32) 445 lfbmode = TDV_LFBMODE_8888; 446 else 447 return false; 448 449 #if BYTE_ORDER == BIG_ENDIAN 450 lfbmode |= TDV_LFBMODE_BSW_WR | TDV_LFBMODE_BSW_RD; 451 #endif 452 453 tdvfb_cvg_write(sc, TDV_OFF_LFBMODE, lfbmode); 454 455 return true; 456 } 457 458 /* 459 * Update DAC parameters for selected video mode. 460 */ 461 static void 462 tdvfb_videomode_dac(struct tdvfb_softc *sc) 463 { 464 uint32_t fbiinit2, fbiinit3; 465 466 /* remember current FBIINIT settings */ 467 fbiinit2 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); 468 fbiinit3 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT3); 469 470 /* remap DAC */ 471 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 472 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 473 474 tdvfb_cvg_dac_write(sc, TDV_GENDAC_CMD, TDV_GENDAC_CMD_16BITS); 475 476 tdvfb_gendac_set_vid_timing(sc, &(sc->vid_timing)); 477 478 /* disable remapping */ 479 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 480 TDV_INITENABLE_EN_INIT); 481 /* restore */ 482 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 483 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit3); 484 } 485 486 /* 487 * Check how much memory do we have. Actually, Voodoo1/2 has separate 488 * framebuffer and texture memory. This function only checks for framebuffer 489 * memory. Texture memory ramains unused. 490 */ 491 static size_t 492 tdvfb_mem_size(struct tdvfb_softc *sc) 493 { 494 size_t mem_size; 495 uint32_t vram_test4, vram_test2; 496 497 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0, 0x11aabbaa); 498 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x100000, 0x22aabbaa); 499 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x200000, 0x44aabbaa); 500 501 vram_test4 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x400000); 502 vram_test2 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x200000); 503 504 if (vram_test4 == 0x44aabbaa) 505 mem_size = 4*1024*1024; 506 else if (vram_test2 == 0x22aabbaa) { 507 mem_size = 2*1024*1024; 508 } else 509 mem_size = 1*1024*1024; 510 511 return mem_size; 512 } 513 514 /* do the low level init of Voodoo board */ 515 static bool 516 tdvfb_init(struct tdvfb_softc *sc) 517 { 518 /* undocumented - found in glide code */ 519 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_DISABLE_REG, 0); 520 /* allow write to hardware initialization registers */ 521 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 522 TDV_INITENABLE_EN_INIT); 523 524 /* reset the board */ 525 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 526 tdvfb_wait(sc); 527 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 528 TDV_FBIINIT0_FIFO_RST); 529 tdvfb_wait(sc); 530 531 /* disable video RAM refresh */ 532 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 533 tdvfb_wait(sc); 534 535 /* on voodoo1 I had to read FBIINIT2 before remapping, 536 * otherwise weird things were happening, on v2 it works just fine */ 537 /* tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); */ 538 539 /* remap DAC */ 540 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 541 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 542 543 /* detect supported DAC, TODO: we really should support other DACs */ 544 if(!tdvfb_gendac_detect(sc)) { 545 aprint_error_dev(sc->sc_dev, "could not detect ICS GENDAC\n"); 546 return false; 547 } 548 549 /* calculate PLL used to drive the chips (graphics clock) */ 550 if(sc->sc_voodootype == TDV_VOODOO_2) 551 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_CVG_CLK); 552 else 553 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_SST_CLK); 554 555 /* set PLL for gfx clock */ 556 tdvfb_gendac_set_cvg_timing(sc, &(sc->cvg_timing)); 557 558 /* don't remap the DAC anymore */ 559 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 560 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_EN_FIFO); 561 562 /* set FBIINIT registers to some default values that make sense */ 563 tdvfb_fbiinit_defaults(sc); 564 565 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 566 TDV_INITENABLE_EN_FIFO); 567 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_ENABLE_REG, 0); 568 569 return true; 570 } 571 572 static void 573 tdvfb_fbiinit_defaults(struct tdvfb_softc *sc) 574 { 575 uint32_t fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6; 576 577 fbiinit0 = TDV_FBIINIT0_VGA_PASS; /* disable VGA passthrough */ 578 fbiinit1 = /*TDV_FBIINIT1_PCIWAIT |*/ /* one wait state for PCI write */ 579 TDV_FBIINIT1_LFB_EN | /* enable lfb reads */ 580 TDV_FBIINIT1_VIDEO_RST | /* video timing reset */ 581 10 << TDV_FBIINIT1_TILES_X | /* tiles x/horizontal */ 582 TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC ; 583 584 fbiinit2 = TDV_FBIINIT2_SWB_ALG |/* swap buffer use DAC sync */ 585 TDV_FBIINIT2_FAST_RAS | /* fast RAS read */ 586 TDV_FBIINIT2_DRAM_OE | /* enable DRAM OE */ 587 TDV_FBIINIT2_DRAM_REFR | /* enable DRAM refresh */ 588 TDV_FBIINIT2_FIFO_RDA | /* FIFO read ahead */ 589 TDV_FBIINIT2_DRAM_REF16 << TDV_FBIINIT2_DRAM_REFLD; /* 16 ms */ 590 591 fbiinit3 = TDV_FBIINIT3_TREX_DIS; /* disable texture mapping */ 592 593 fbiinit4 = /*TDV_FBIINIT4_PCIWAIT|*/ /* one wait state for PCI write */ 594 TDV_FBIINIT4_LFB_RDA; /* lfb read ahead */ 595 596 fbiinit6 = 0; 597 #ifdef TDVFB_DEBUG 598 aprint_normal("fbiinit: 0 %x, 1 %x, 2 %x, 3 %x, 4 %x, 6 %x\n", 599 fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6); 600 #endif /* TDVFB_DEBUG */ 601 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT0, fbiinit0); 602 tdvfb_wait(sc); 603 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 604 tdvfb_wait(sc); 605 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 606 tdvfb_wait(sc); 607 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT3, fbiinit3); 608 tdvfb_wait(sc); 609 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT4, fbiinit4); 610 tdvfb_wait(sc); 611 if (sc->sc_voodootype == TDV_VOODOO_2) { 612 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 613 tdvfb_wait(sc); 614 } 615 } 616 617 static void 618 tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 619 struct tdvfb_dac_timing *timing) 620 { 621 uint8_t pllreg; 622 623 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 624 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 625 626 /* write the timing for gfx clock into "slot" 0 */ 627 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0); 628 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 629 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 630 /* select "slot" 0 for output */ 631 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 632 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 633 (pllreg & TDV_GENDAC_VIDPLLMASK) | TDV_GENDAC_PLL_VIDCLK | 634 TDV_GENDAC_PLL_VIDCLK0); 635 tdvfb_wait(sc); 636 tdvfb_wait(sc); 637 #ifdef TDVFB_DEBUG 638 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_0); 639 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 640 aprint_normal("vid read again: %d\n", pllreg); 641 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 642 aprint_normal("vid read again: %d\n", pllreg); 643 #endif /* TDVFB_DEBUG */ 644 } 645 646 static void 647 tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 648 struct tdvfb_dac_timing *timing) 649 { 650 uint8_t pllreg; 651 652 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 653 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 654 655 /* write the timing for gfx clock into "slot" A */ 656 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_A); 657 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 658 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 659 /* select "slot" A for output */ 660 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 661 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 662 (pllreg & TDV_GENDAC_CVGPLLMASK) | TDV_GENDAC_PLL_CVGCLKA); 663 #ifdef TDVFB_DEBUG 664 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_A); 665 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 666 aprint_normal("read again: %d\n", pllreg); 667 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 668 aprint_normal("read again: %d\n", pllreg); 669 #endif /* TDVFB_DEBUG */ 670 tdvfb_wait(sc); 671 } 672 673 static struct tdvfb_dac_timing 674 tdvfb_gendac_calc_pll(int freq) 675 { 676 int n1, n2; 677 int m, mdbl; 678 int best_m, best_n1, best_error; 679 int fout; 680 struct tdvfb_dac_timing timing; 681 682 best_m = -1; best_n1 = -1; 683 684 /* select highest possible n2, check n2 * fCLK < TDV_GENDAC_MAXVCO */ 685 for (n2 = TDV_GENDAC_MAX_N2; n2 >= TDV_GENDAC_MIN_N2; n2--) { 686 if ((freq * (1 << n2)) < TDV_GENDAC_MAXVCO) 687 break; 688 } 689 690 best_error = freq; 691 692 /* 693 * m+2 2^n2 * fOUT 694 * ---- = ----------- 695 * n1+2 fREF 696 */ 697 for (n1 = TDV_GENDAC_MIN_N1; n1 <= TDV_GENDAC_MAX_N1; n1++) { 698 /* loop mostly inspired by Linux driver */ 699 mdbl = (2 * freq * (1 << n2)*(n1 + 2)) / TDV_GENDAC_REFFREQ - 4; 700 if (mdbl % 2) 701 m = mdbl/2+1; 702 else 703 m = mdbl/2; 704 705 if(m > TDV_GENDAC_MAX_M) 706 break; 707 708 fout = (TDV_GENDAC_REFFREQ * (m + 2)) / ((1 << n2) * (n1 + 2)); 709 if ((abs(fout - freq) < best_error) && (m > 0)) { 710 best_n1 = n1; 711 best_m = m; 712 best_error = abs(fout - freq); 713 if (200*best_error < freq) break; 714 } 715 716 } 717 718 fout = (TDV_GENDAC_REFFREQ * (best_m + 2)) / ((1 << n2) * (best_n1 + 2)); 719 timing.m = best_m; 720 timing.n = (n2 << 5) | best_n1; 721 timing.fout = fout; 722 723 #ifdef TDVFB_DEBUG 724 aprint_normal("tdvfb_gendac_calc_pll ret: m %d, n %d, fout %d kHz\n", 725 timing.m, timing.n, timing.fout); 726 #endif /* TDVFB_DEBUG */ 727 728 return timing; 729 } 730 731 static bool 732 tdvfb_gendac_detect(struct tdvfb_softc *sc) 733 { 734 uint8_t m_f1, m_f7, m_fb; 735 uint8_t n_f1, n_f7, n_fb; 736 737 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x1); 738 m_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 739 n_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 740 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x7); 741 m_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 742 n_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 743 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0xB); 744 m_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 745 n_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 746 747 if( (m_f1 == TDV_GENDAC_DFLT_F1_M) && 748 (n_f1 == TDV_GENDAC_DFLT_F1_N) && 749 (m_f7 == TDV_GENDAC_DFLT_F7_M) && 750 (n_f7 == TDV_GENDAC_DFLT_F7_N) && 751 (m_fb == TDV_GENDAC_DFLT_FB_M) && 752 (n_fb == TDV_GENDAC_DFLT_FB_N) ) { 753 aprint_normal_dev(sc->sc_dev, "ICS 5342 GENDAC\n"); 754 return true; 755 } 756 757 return false; 758 } 759 760 static void 761 tdvfb_wait(struct tdvfb_softc *sc) 762 { 763 uint32_t x, cnt; 764 cnt = 0; 765 for (x = 0; x < MAXLOOP; x++) { 766 if (tdvfb_cvg_read(sc, TDV_OFF_STATUS) & TDV_STATUS_FBI_BUSY) 767 cnt = 0; 768 else 769 cnt++; 770 771 if (cnt >= 5) /* Voodoo2 specs suggest at least 3 */ 772 break; 773 } 774 775 if (x == MAXLOOP) 776 /* 777 * The console probably isn't working now anyway, so maybe 778 * let's panic... At least it will drop into ddb if some other 779 * device a console. 780 */ 781 panic("tdvfb is stuck!\n"); 782 } 783 784 static uint32_t 785 tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg) 786 { 787 uint32_t rv; 788 rv = bus_space_read_4(sc->sc_cvgt, sc->sc_cvgh, reg); 789 #ifdef TDVFB_DEBUG_REGS 790 aprint_normal("cvg_read val %x from reg %x\n", rv, reg); 791 #endif /* TDVFB_DEBUG_REGS */ 792 return rv; 793 } 794 795 static void 796 tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 797 { 798 #ifdef TDVFB_DEBUG_REGS 799 aprint_normal("cvg_write val %x to reg %x\n", val, reg); 800 #endif /* TDVFB_DEBUG_REGS */ 801 bus_space_write_4(sc->sc_cvgt, sc->sc_cvgh, reg, val); 802 } 803 804 static void 805 tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 806 { 807 uint32_t v; 808 v = tdvfb_cvg_read(sc, reg) | bits; 809 tdvfb_cvg_write(sc, reg, v); 810 } 811 812 static void 813 tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 814 { 815 uint32_t v; 816 v = tdvfb_cvg_read(sc, reg) & ~bits; 817 tdvfb_cvg_write(sc, reg, v); 818 } 819 820 static uint8_t 821 tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg) 822 { 823 uint32_t rv; 824 825 tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ); 826 827 rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ); 828 #ifdef TDVFB_DEBUG_REGS 829 aprint_normal("cvg_dac_read val %x from reg %x\n", rv, reg); 830 #endif /* TDVFB_DEBUG_REGS */ 831 return rv & 0xFF; 832 } 833 834 static void 835 tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 836 { 837 uint32_t wreg; 838 839 wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val; 840 841 #ifdef TDVFB_DEBUG_REGS 842 aprint_normal("cvg_dac_write val %x to reg %x (%x)\n", val, reg, 843 wreg); 844 #endif /* TDVFB_DEBUG_REGS */ 845 846 tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg); 847 tdvfb_wait(sc); 848 } 849 850 static void 851 tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, int he, 852 uint32_t color) 853 { 854 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 855 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 856 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 857 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 858 sc->sc_linebytes | (sc->sc_linebytes << 16)); 859 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, x | (y << 16)); 860 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 861 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_RECTFILL | 862 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3 | TDV_BLTCMD_DSTTILED | 863 TDV_BLTCMD_CLIPRECT ); 864 tdvfb_wait(sc); 865 } 866 867 static void 868 tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, int yd, int wi, 869 int he) 870 { 871 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 872 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 873 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 874 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 875 sc->sc_linebytes | (sc->sc_linebytes << 16)); 876 tdvfb_cvg_write(sc, TDV_OFF_BLTSRCXY, xs | (ys << 16)); 877 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, xd | (yd << 16)); 878 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 879 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_SCR2SCR | 880 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3); 881 882 tdvfb_wait(sc); 883 } 884 885 static void 886 tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 887 { 888 struct tdvfb_softc *sc; 889 struct rasops_info *ri; 890 struct vcons_screen *scr; 891 int x, ys, yd, wi, he; 892 893 ri = cookie; 894 scr = ri->ri_hw; 895 sc = scr->scr_cookie; 896 897 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 898 x = ri->ri_xorigin; 899 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 900 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 901 wi = ri->ri_emuwidth; 902 he = ri->ri_font->fontheight * nrows; 903 tdvfb_bitblt(sc, x, ys, x, yd, wi, he); 904 } 905 } 906 907 static void 908 tdvfb_eraserows(void *cookie, int row, int nrows, long fillattr) 909 { 910 911 struct tdvfb_softc *sc; 912 struct rasops_info *ri; 913 struct vcons_screen *scr; 914 int x, y, wi, he, fg, bg, ul; 915 916 ri = cookie; 917 scr = ri->ri_hw; 918 sc = scr->scr_cookie; 919 920 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 921 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 922 if ((row == 0) && (nrows == ri->ri_rows)) 923 tdvfb_rectfill(sc, 0, 0, ri->ri_width, 924 ri->ri_height, ri->ri_devcmap[bg]); 925 else { 926 x = ri->ri_xorigin; 927 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 928 wi = ri->ri_emuwidth; 929 he = ri->ri_font->fontheight * nrows; 930 tdvfb_rectfill(sc, x, y, wi, he, ri->ri_devcmap[bg]); 931 } 932 } 933 } 934 935 static int 936 tdvfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 937 { 938 struct vcons_data *vd; 939 struct tdvfb_softc *sc; 940 struct wsdisplay_fbinfo *wsfbi; 941 struct vcons_screen *ms; 942 943 vd = v; 944 sc = vd->cookie; 945 ms = vd->active; 946 947 switch (cmd) { 948 case WSDISPLAYIO_GTYPE: 949 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 950 return 0; 951 952 case PCI_IOC_CFGREAD: 953 case PCI_IOC_CFGWRITE: 954 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 955 cmd, data, flag, l); 956 957 case WSDISPLAYIO_GET_BUSID: 958 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 959 sc->sc_pcitag, data); 960 961 case WSDISPLAYIO_GINFO: 962 if (ms == NULL) 963 return ENODEV; 964 965 wsfbi = (void*) data; 966 wsfbi->height = ms->scr_ri.ri_height; 967 wsfbi->width = ms->scr_ri.ri_width; 968 wsfbi->depth = ms->scr_ri.ri_depth; 969 wsfbi->cmsize = 256; 970 return 0; 971 972 case WSDISPLAYIO_LINEBYTES: 973 *(u_int*)data = sc->sc_linebytes; 974 return 0; 975 976 case WSDISPLAYIO_SMODE: 977 { 978 int new_mode = *(int*)data; 979 if (new_mode != sc->sc_mode) { 980 sc->sc_mode = new_mode; 981 if(new_mode == WSDISPLAYIO_MODE_EMUL) 982 vcons_redraw_screen(ms); 983 } 984 return 0; 985 } 986 case WSDISPLAYIO_GET_FBINFO: 987 { 988 struct wsdisplayio_fbinfo *fbi = data; 989 struct rasops_info *ri; 990 int ret; 991 992 ri = &sc->vd.active->scr_ri; 993 ret = wsdisplayio_get_fbinfo(ri, fbi); 994 return ret; 995 } 996 } 997 return EPASSTHROUGH; 998 } 999 1000 static paddr_t 1001 tdvfb_mmap(void *v, void *vs, off_t offset, int prot) 1002 { 1003 struct vcons_data *vd; 1004 struct tdvfb_softc *sc; 1005 paddr_t pa; 1006 1007 vd = v; 1008 sc = vd->cookie; 1009 1010 if (offset < sc->sc_memsize) { 1011 pa = bus_space_mmap(sc->sc_cvgt, sc->sc_fbh + offset, 0, prot, 1012 BUS_SPACE_MAP_LINEAR); 1013 return pa; 1014 } 1015 1016 return -1; 1017 } 1018 1019
Indexes created Tue Sep 30 20:09:53 GMT 2025