| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_nv25.c | 38 u32 tiles = DIV_ROUND_UP(size, 0x40); local in function:nv25_fb_tile_comp
39 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
|
| nouveau_nvkm_subdev_fb_nv35.c | 38 u32 tiles = DIV_ROUND_UP(size, 0x40); local in function:nv35_fb_tile_comp
39 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
|
| nouveau_nvkm_subdev_fb_nv36.c | 38 u32 tiles = DIV_ROUND_UP(size, 0x40); local in function:nv36_fb_tile_comp
39 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
|
| nouveau_nvkm_subdev_fb_nv40.c | 38 u32 tiles = DIV_ROUND_UP(size, 0x80); local in function:nv40_fb_tile_comp
39 u32 tags = round_up(tiles / fb->ram->parts, 0x100);
|
| nouveau_nvkm_subdev_fb_nv20.c | 51 u32 tiles = DIV_ROUND_UP(size, 0x40); local in function:nv20_fb_tile_comp
52 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
|
| nouveau_nvkm_subdev_fb_nv30.c | 57 u32 tiles = DIV_ROUND_UP(size, 0x40); local in function:nv30_fb_tile_comp
58 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display.c | 2364 unsigned int tiles; local in function:intel_adjust_tile_offset
2370 tiles = (old_offset - new_offset) / tile_size;
2372 *y += tiles / pitch_tiles * tile_height;
2373 *x += tiles % pitch_tiles * tile_width;
2469 unsigned int tile_rows, tiles, pitch_tiles; local in function:intel_compute_aligned_offset
2484 tiles = *x / tile_width;
2487 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2619 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
3097 /* how many tiles does this plane need */
3118 /* how many tiles in total needed in the bo *
[all...] |
