1 /* $NetBSD: intel_display.h,v 1.6 2021/12/19 11:48:27 riastradh Exp $ */ 2 3 /* 4 * Copyright 2006-2019 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _INTEL_DISPLAY_H_ 28 #define _INTEL_DISPLAY_H_ 29 30 /* 31 * NetBSD already has struct pipe, and according to C99 6.2.3 there's 32 * only one namespace for struct, union, and enum tags, but the i915 33 * driver wants a type called enum pipe. 34 * 35 * So rename it to avoid conflicts which confuse tools like ctfmerge -- 36 * but make sure we include <sys/file.h> first to avoid having two 37 * different versions of struct file, one with a pointer to struct pipe 38 * and another with a pointer to struct i915_pipe. 39 * 40 * This will cause trouble if we ever have an API that involves `pipe' 41 * as a member which we need to reference from within drm code. But 42 * for now that is not the case. 43 * 44 * XXX Yes, this is disgusting. Sorry. 45 */ 46 #include <sys/types.h> 47 #include <sys/file.h> 48 #define pipe pipe_drmhack 49 50 #include <drm/drm_util.h> 51 #include <drm/i915_drm.h> 52 53 enum link_m_n_set; 54 struct dpll; 55 struct drm_connector; 56 struct drm_device; 57 struct drm_display_mode; 58 struct drm_encoder; 59 struct drm_file; 60 struct drm_format_info; 61 struct drm_framebuffer; 62 struct drm_i915_error_state_buf; 63 struct drm_i915_gem_object; 64 struct drm_i915_private; 65 struct drm_modeset_acquire_ctx; 66 struct drm_plane; 67 struct drm_plane_state; 68 struct i915_ggtt_view; 69 struct intel_crtc; 70 struct intel_crtc_state; 71 struct intel_digital_port; 72 struct intel_dp; 73 struct intel_encoder; 74 struct intel_load_detect_pipe; 75 struct intel_plane; 76 struct intel_plane_state; 77 struct intel_remapped_info; 78 struct intel_rotation_info; 79 struct intel_crtc_state; 80 81 enum i915_gpio { 82 GPIOA, 83 GPIOB, 84 GPIOC, 85 GPIOD, 86 GPIOE, 87 GPIOF, 88 GPIOG, 89 GPIOH, 90 __GPIOI_UNUSED, 91 GPIOJ, 92 GPIOK, 93 GPIOL, 94 GPIOM, 95 GPION, 96 GPIOO, 97 }; 98 99 /* 100 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 101 * rest have consecutive values and match the enum values of transcoders 102 * with a 1:1 transcoder -> pipe mapping. 103 */ 104 enum pipe { 105 INVALID_PIPE = -1, 106 107 PIPE_A = 0, 108 PIPE_B, 109 PIPE_C, 110 PIPE_D, 111 _PIPE_EDP, 112 113 I915_MAX_PIPES = _PIPE_EDP 114 }; 115 116 #define pipe_name(p) ((p) + 'A') 117 118 enum transcoder { 119 INVALID_TRANSCODER = -1, 120 /* 121 * The following transcoders have a 1:1 transcoder -> pipe mapping, 122 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 123 * rest have consecutive values and match the enum values of the pipes 124 * they map to. 125 */ 126 TRANSCODER_A = PIPE_A, 127 TRANSCODER_B = PIPE_B, 128 TRANSCODER_C = PIPE_C, 129 TRANSCODER_D = PIPE_D, 130 131 /* 132 * The following transcoders can map to any pipe, their enum value 133 * doesn't need to stay fixed. 134 */ 135 TRANSCODER_EDP, 136 TRANSCODER_DSI_0, 137 TRANSCODER_DSI_1, 138 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 139 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 140 141 I915_MAX_TRANSCODERS 142 }; 143 144 static inline const char *transcoder_name(enum transcoder transcoder) 145 { 146 switch (transcoder) { 147 case TRANSCODER_A: 148 return "A"; 149 case TRANSCODER_B: 150 return "B"; 151 case TRANSCODER_C: 152 return "C"; 153 case TRANSCODER_D: 154 return "D"; 155 case TRANSCODER_EDP: 156 return "EDP"; 157 case TRANSCODER_DSI_A: 158 return "DSI A"; 159 case TRANSCODER_DSI_C: 160 return "DSI C"; 161 default: 162 return "<invalid>"; 163 } 164 } 165 166 static inline bool transcoder_is_dsi(enum transcoder transcoder) 167 { 168 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 169 } 170 171 /* 172 * Global legacy plane identifier. Valid only for primary/sprite 173 * planes on pre-g4x, and only for primary planes on g4x-bdw. 174 */ 175 enum i9xx_plane_id { 176 PLANE_A, 177 PLANE_B, 178 PLANE_C, 179 }; 180 181 #define plane_name(p) ((p) + 'A') 182 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 183 184 /* 185 * Per-pipe plane identifier. 186 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 187 * number of planes per CRTC. Not all platforms really have this many planes, 188 * which means some arrays of size I915_MAX_PLANES may have unused entries 189 * between the topmost sprite plane and the cursor plane. 190 * 191 * This is expected to be passed to various register macros 192 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 193 */ 194 enum plane_id { 195 PLANE_PRIMARY, 196 PLANE_SPRITE0, 197 PLANE_SPRITE1, 198 PLANE_SPRITE2, 199 PLANE_SPRITE3, 200 PLANE_SPRITE4, 201 PLANE_SPRITE5, 202 PLANE_CURSOR, 203 204 I915_MAX_PLANES, 205 }; 206 207 #define for_each_plane_id_on_crtc(__crtc, __p) \ 208 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 209 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 210 211 enum port { 212 PORT_NONE = -1, 213 214 PORT_A = 0, 215 PORT_B, 216 PORT_C, 217 PORT_D, 218 PORT_E, 219 PORT_F, 220 PORT_G, 221 PORT_H, 222 PORT_I, 223 224 I915_MAX_PORTS 225 }; 226 227 #define port_name(p) ((p) + 'A') 228 229 /* 230 * Ports identifier referenced from other drivers. 231 * Expected to remain stable over time 232 */ 233 static inline const char *port_identifier(enum port port) 234 { 235 switch (port) { 236 case PORT_A: 237 return "Port A"; 238 case PORT_B: 239 return "Port B"; 240 case PORT_C: 241 return "Port C"; 242 case PORT_D: 243 return "Port D"; 244 case PORT_E: 245 return "Port E"; 246 case PORT_F: 247 return "Port F"; 248 case PORT_G: 249 return "Port G"; 250 case PORT_H: 251 return "Port H"; 252 case PORT_I: 253 return "Port I"; 254 default: 255 return "<invalid>"; 256 } 257 } 258 259 enum tc_port { 260 PORT_TC_NONE = -1, 261 262 PORT_TC1 = 0, 263 PORT_TC2, 264 PORT_TC3, 265 PORT_TC4, 266 PORT_TC5, 267 PORT_TC6, 268 269 I915_MAX_TC_PORTS 270 }; 271 272 enum tc_port_mode { 273 TC_PORT_TBT_ALT, 274 TC_PORT_DP_ALT, 275 TC_PORT_LEGACY, 276 }; 277 278 enum dpio_channel { 279 DPIO_CH0, 280 DPIO_CH1 281 }; 282 283 enum dpio_phy { 284 DPIO_PHY0, 285 DPIO_PHY1, 286 DPIO_PHY2, 287 }; 288 289 #define I915_NUM_PHYS_VLV 2 290 291 enum aux_ch { 292 AUX_CH_A, 293 AUX_CH_B, 294 AUX_CH_C, 295 AUX_CH_D, 296 AUX_CH_E, /* ICL+ */ 297 AUX_CH_F, 298 AUX_CH_G, 299 }; 300 301 #define aux_ch_name(a) ((a) + 'A') 302 303 /* Used by dp and fdi links */ 304 struct intel_link_m_n { 305 u32 tu; 306 u32 gmch_m; 307 u32 gmch_n; 308 u32 link_m; 309 u32 link_n; 310 }; 311 312 enum phy { 313 PHY_NONE = -1, 314 315 PHY_A = 0, 316 PHY_B, 317 PHY_C, 318 PHY_D, 319 PHY_E, 320 PHY_F, 321 PHY_G, 322 PHY_H, 323 PHY_I, 324 325 I915_MAX_PHYS 326 }; 327 328 #define phy_name(a) ((a) + 'A') 329 330 enum phy_fia { 331 FIA1, 332 FIA2, 333 FIA3, 334 }; 335 336 #define for_each_pipe(__dev_priv, __p) \ 337 for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) 338 339 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 340 for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \ 341 for_each_if((__mask) & BIT(__p)) 342 343 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 344 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 345 for_each_if ((__mask) & (1 << (__t))) 346 347 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 348 for ((__p) = 0; \ 349 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 350 (__p)++) 351 352 #define for_each_sprite(__dev_priv, __p, __s) \ 353 for ((__s) = 0; \ 354 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 355 (__s)++) 356 357 #define for_each_port(__port) \ 358 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 359 360 #define for_each_port_masked(__port, __ports_mask) \ 361 for_each_port(__port) \ 362 for_each_if((__ports_mask) & BIT(__port)) 363 364 #define for_each_phy_masked(__phy, __phys_mask) \ 365 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 366 for_each_if((__phys_mask) & BIT(__phy)) 367 368 #define for_each_crtc(dev, crtc) \ 369 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 370 371 #define for_each_intel_plane(dev, intel_plane) \ 372 list_for_each_entry(intel_plane, \ 373 &(dev)->mode_config.plane_list, \ 374 base.head) 375 376 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 377 list_for_each_entry(intel_plane, \ 378 &(dev)->mode_config.plane_list, \ 379 base.head) \ 380 for_each_if((plane_mask) & \ 381 drm_plane_mask(&intel_plane->base)) 382 383 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 384 list_for_each_entry(intel_plane, \ 385 &(dev)->mode_config.plane_list, \ 386 base.head) \ 387 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 388 389 #define for_each_intel_crtc(dev, intel_crtc) \ 390 list_for_each_entry(intel_crtc, \ 391 &(dev)->mode_config.crtc_list, \ 392 base.head) 393 394 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 395 list_for_each_entry(intel_crtc, \ 396 &(dev)->mode_config.crtc_list, \ 397 base.head) \ 398 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 399 400 #define for_each_intel_encoder(dev, intel_encoder) \ 401 list_for_each_entry(intel_encoder, \ 402 &(dev)->mode_config.encoder_list, \ 403 base.head) 404 405 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 406 list_for_each_entry(intel_encoder, \ 407 &(dev)->mode_config.encoder_list, \ 408 base.head) \ 409 for_each_if((encoder_mask) & \ 410 drm_encoder_mask(&intel_encoder->base)) 411 412 #define for_each_intel_dp(dev, intel_encoder) \ 413 for_each_intel_encoder(dev, intel_encoder) \ 414 for_each_if(intel_encoder_is_dp(intel_encoder)) 415 416 #define for_each_intel_connector_iter(intel_connector, iter) \ 417 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 418 419 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 420 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 421 for_each_if((intel_encoder)->base.crtc == (__crtc)) 422 423 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 424 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 425 for_each_if((intel_connector)->base.encoder == (__encoder)) 426 427 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 428 for ((__i) = 0; \ 429 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 430 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 431 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 432 (__i)++) \ 433 for_each_if(plane) 434 435 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 436 for ((__i) = 0; \ 437 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 438 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 439 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 440 (__i)++) \ 441 for_each_if(plane) 442 443 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 444 for ((__i) = 0; \ 445 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 446 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 447 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 448 (__i)++) \ 449 for_each_if(crtc) 450 451 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 452 for ((__i) = 0; \ 453 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 454 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 455 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 456 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 457 (__i)++) \ 458 for_each_if(plane) 459 460 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 461 for ((__i) = 0; \ 462 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 463 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 464 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 465 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 466 (__i)++) \ 467 for_each_if(crtc) 468 469 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 470 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 471 (__i) >= 0 && \ 472 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 473 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 474 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 475 (__i)--) \ 476 for_each_if(crtc) 477 478 #define intel_atomic_crtc_state_for_each_plane_state( \ 479 plane, plane_state, \ 480 crtc_state) \ 481 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 482 ((crtc_state)->uapi.plane_mask)) \ 483 for_each_if ((plane_state = \ 484 const_container_of(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base), struct intel_plane_state, uapi))) 485 486 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 487 for ((__i) = 0; \ 488 (__i) < (__state)->base.num_connector; \ 489 (__i)++) \ 490 for_each_if ((__state)->base.connectors[__i].ptr && \ 491 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 492 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 493 494 void intel_link_compute_m_n(u16 bpp, int nlanes, 495 int pixel_clock, int link_clock, 496 struct intel_link_m_n *m_n, 497 bool constant_n, bool fec_enable); 498 bool is_ccs_modifier(u64 modifier); 499 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); 500 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 501 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 502 u32 pixel_format, u64 modifier); 503 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 504 enum drm_mode_status 505 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 506 const struct drm_display_mode *mode); 507 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 508 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 509 510 void intel_plane_destroy(struct drm_plane *plane); 511 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); 512 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 513 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 514 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 515 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 516 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 517 const char *name, u32 reg, int ref_freq); 518 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 519 const char *name, u32 reg); 520 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 521 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 522 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 523 unsigned int intel_fb_xy_to_linear(int x, int y, 524 const struct intel_plane_state *state, 525 int plane); 526 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 527 int color_plane, unsigned int height); 528 void intel_add_fb_offsets(int *x, int *y, 529 const struct intel_plane_state *state, int plane); 530 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 531 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 532 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 533 int intel_display_suspend(struct drm_device *dev); 534 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 535 void intel_encoder_destroy(struct drm_encoder *encoder); 536 struct drm_display_mode * 537 intel_encoder_current_mode(struct intel_encoder *encoder); 538 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 539 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 540 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 541 enum port port); 542 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 543 struct drm_file *file_priv); 544 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 545 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); 546 547 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 548 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 549 struct intel_digital_port *dport, 550 unsigned int expected_mask); 551 int intel_get_load_detect_pipe(struct drm_connector *connector, 552 struct intel_load_detect_pipe *old, 553 struct drm_modeset_acquire_ctx *ctx); 554 void intel_release_load_detect_pipe(struct drm_connector *connector, 555 struct intel_load_detect_pipe *old, 556 struct drm_modeset_acquire_ctx *ctx); 557 struct i915_vma * 558 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 559 const struct i915_ggtt_view *view, 560 bool uses_fence, 561 unsigned long *out_flags); 562 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 563 struct drm_framebuffer * 564 intel_framebuffer_create(struct drm_i915_gem_object *obj, 565 struct drm_mode_fb_cmd2 *mode_cmd); 566 int intel_prepare_plane_fb(struct drm_plane *plane, 567 struct drm_plane_state *new_state); 568 void intel_cleanup_plane_fb(struct drm_plane *plane, 569 struct drm_plane_state *old_state); 570 571 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 572 enum pipe pipe); 573 574 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 575 const struct dpll *dpll); 576 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 577 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 578 bool intel_fuzzy_clock_check(int clock1, int clock2); 579 580 void intel_prepare_reset(struct drm_i915_private *dev_priv); 581 void intel_finish_reset(struct drm_i915_private *dev_priv); 582 void intel_dp_get_m_n(struct intel_crtc *crtc, 583 struct intel_crtc_state *pipe_config); 584 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 585 enum link_m_n_set m_n); 586 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 587 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 588 struct dpll *best_clock); 589 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 590 591 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 592 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 593 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 594 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 595 enum intel_display_power_domain 596 intel_aux_power_domain(struct intel_digital_port *dig_port); 597 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 598 struct intel_crtc_state *pipe_config); 599 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 600 struct intel_crtc_state *crtc_state); 601 602 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 603 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 604 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); 605 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 606 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 607 const struct intel_plane_state *plane_state); 608 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 609 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 610 const struct intel_plane_state *plane_state); 611 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 612 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 613 int plane); 614 int skl_check_plane_surface(struct intel_plane_state *plane_state); 615 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 616 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 617 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 618 u32 pixel_format, u64 modifier, 619 unsigned int rotation); 620 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 621 622 struct intel_display_error_state * 623 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 624 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 625 struct intel_display_error_state *error); 626 627 bool 628 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 629 uint64_t modifier); 630 631 /* modesetting */ 632 void intel_modeset_init_hw(struct drm_i915_private *i915); 633 int intel_modeset_init(struct drm_i915_private *i915); 634 void intel_modeset_driver_remove(struct drm_i915_private *i915); 635 void intel_display_resume(struct drm_device *dev); 636 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 637 638 /* modesetting asserts */ 639 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 640 enum pipe pipe); 641 void assert_pll(struct drm_i915_private *dev_priv, 642 enum pipe pipe, bool state); 643 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 644 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 645 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 646 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 647 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 648 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 649 enum pipe pipe, bool state); 650 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 651 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 652 void assert_pipe(struct drm_i915_private *dev_priv, 653 enum transcoder cpu_transcoder, bool state); 654 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true) 655 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false) 656 657 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 658 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 659 * which may not necessarily be a user visible problem. This will either 660 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 661 * enable distros and users to tailor their preferred amount of i915 abrt 662 * spam. 663 */ 664 #define I915_STATE_WARN(condition, format...) ({ \ 665 int __ret_warn_on = !!(condition); \ 666 if (unlikely(__ret_warn_on)) \ 667 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 668 DRM_ERROR(format); \ 669 unlikely(__ret_warn_on); \ 670 }) 671 672 #define I915_STATE_WARN_ON(x) \ 673 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 674 675 #endif 676
Indexes created Sat Sep 20 22:09:52 GMT 2025