| /src/sys/dev/pci/ixgbe/ |
| ixv.c | 1730 u32 txctrl, txdctl; local in function:ixv_initialize_transmit_units
1734 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1735 txdctl &= ~IXGBE_TXDCTL_WTHRESH_MASK;
1736 txdctl |= IXGBE_TX_WTHRESH << IXGBE_TXDCTL_WTHRESH_SHIFT;
1737 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1759 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1760 txdctl |= IXGBE_TXDCTL_ENABLE;
1761 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
|
| ixgbe.c | 4056 u32 txdctl, mhadd; local in function:ixgbe_init_locked
4144 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me));
4145 txdctl |= IXGBE_TXDCTL_ENABLE;
4147 txdctl &= ~IXGBE_TXDCTL_WTHRESH_MASK;
4148 txdctl |= IXGBE_TX_WTHRESH << IXGBE_TXDCTL_WTHRESH_SHIFT;
4156 txdctl |= (32 << 0) | (1 << 8);
4157 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl);
|
| /src/sys/dev/pci/igc/ |
| if_igc.c | 3053 uint32_t txdctl = 0; /* Clear txdctl */ local in function:igc_initialize_transmit_unit
3054 txdctl |= 0x1f; /* PTHRESH */
3055 txdctl |= 1 << 8; /* HTHRESH */
3056 txdctl |= 1 << 16; /* WTHRESH */
3057 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3058 txdctl |= IGC_TXDCTL_GRAN;
3059 txdctl |= 1 << 25; /* LWTHRESH */
3061 IGC_WRITE_REG(hw, IGC_TXDCTL(iq), txdctl);
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