| /src/external/gpl3/binutils/dist/include/opcode/ |
| cr16.h | 124 uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, enumerator in enum:__anon10627
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| cr16.h | 124 uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, enumerator in enum:__anon12091
|
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| cr16.h | 124 uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, enumerator in enum:__anon21479
|
| /src/external/gpl3/gdb/dist/include/opcode/ |
| cr16.h | 124 uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, enumerator in enum:__anon1067
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| bfin-parse.c | 265 #define uimm5(x) EXPR_VALUE (x) macro
4387 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
4409 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
4566 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
4652 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
4653 (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
4662 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
4687 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
4688 (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-4].reg), -uimm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
4701 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n")
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| bfin-dis.c | 91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
458 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf) macro
1570 OUTS (outf, uimm5 (src));
1581 OUTS (outf, uimm5 (src));
1592 OUTS (outf, uimm5 (src));
1603 OUTS (outf, uimm5 (src));
1614 OUTS (outf, uimm5 (src));
1624 OUTS (outf, uimm5 (src));
1630 OUTS (outf, uimm5 (src));
1636 OUTS (outf, uimm5 (src))
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| bfin-parse.c | 265 #define uimm5(x) EXPR_VALUE (x) macro
4387 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
4409 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
4566 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
4652 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
4653 (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
4662 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
4687 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
4688 (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-4].reg), -uimm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
4701 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n")
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| bfin-dis.c | 91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
458 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf) macro
1570 OUTS (outf, uimm5 (src));
1581 OUTS (outf, uimm5 (src));
1592 OUTS (outf, uimm5 (src));
1603 OUTS (outf, uimm5 (src));
1614 OUTS (outf, uimm5 (src));
1624 OUTS (outf, uimm5 (src));
1630 OUTS (outf, uimm5 (src));
1636 OUTS (outf, uimm5 (src))
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| bfin-dis.c | 91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
458 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf) macro
1570 OUTS (outf, uimm5 (src));
1581 OUTS (outf, uimm5 (src));
1592 OUTS (outf, uimm5 (src));
1603 OUTS (outf, uimm5 (src));
1614 OUTS (outf, uimm5 (src));
1624 OUTS (outf, uimm5 (src));
1630 OUTS (outf, uimm5 (src));
1636 OUTS (outf, uimm5 (src))
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| bfin-sim.c | 169 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
306 #define uimm5(x) fmtconst_val (c_uimm5, x, 0) macro
2732 int uimm = uimm5 (src);
2737 TRACE_DECODE (cpu, "%s: uimm5:%#x", __func__, uimm);
5949 int shift = uimm5 (newimmag);
5969 int shiftup = uimm5 (immag);
5970 int shiftdn = uimm5 (newimmag);
6056 int count = uimm5 (newimmag);
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| bfin-dis.c | 91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
458 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf) macro
1570 OUTS (outf, uimm5 (src));
1581 OUTS (outf, uimm5 (src));
1592 OUTS (outf, uimm5 (src));
1603 OUTS (outf, uimm5 (src));
1614 OUTS (outf, uimm5 (src));
1624 OUTS (outf, uimm5 (src));
1630 OUTS (outf, uimm5 (src));
1636 OUTS (outf, uimm5 (src))
[all...] |
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| bfin-sim.c | 169 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
306 #define uimm5(x) fmtconst_val (c_uimm5, x, 0) macro
2732 int uimm = uimm5 (src);
2737 TRACE_DECODE (cpu, "%s: uimm5:%#x", __func__, uimm);
5949 int shift = uimm5 (newimmag);
5969 int shiftup = uimm5 (immag);
5970 int shiftdn = uimm5 (newimmag);
6056 int count = uimm5 (newimmag);
|
