1 /* $NetBSD: esp.c,v 1.36 2026/01/02 23:33:58 nia Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994 Peter Galbavy 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 50 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 51 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 52 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 53 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 56 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 57 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Based on aic6360 by Jarle Greipsland 63 * 64 * Acknowledgements: Many of the algorithms used in this driver are 65 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 66 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.36 2026/01/02 23:33:58 nia Exp $"); 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/queue.h> 82 83 #include <dev/scsipi/scsi_all.h> 84 #include <dev/scsipi/scsipi_all.h> 85 #include <dev/scsipi/scsiconf.h> 86 #include <dev/scsipi/scsi_message.h> 87 88 #include <dev/ofw/openfirm.h> 89 90 #include <machine/cpu.h> 91 #include <machine/autoconf.h> 92 #include <machine/pio.h> 93 94 #include <dev/ic/ncr53c9xreg.h> 95 #include <dev/ic/ncr53c9xvar.h> 96 97 #include <macppc/dev/dbdma.h> 98 #include <macppc/dev/espvar.h> 99 100 int espmatch(device_t, cfdata_t, void *); 101 void espattach(device_t, device_t, void *); 102 103 /* Linkup to the rest of the kernel */ 104 CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc), 105 espmatch, espattach, NULL, NULL); 106 107 /* 108 * Functions and the switch for the MI code. 109 */ 110 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int); 111 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 112 static int esp_dma_isintr(struct ncr53c9x_softc *); 113 static void esp_dma_reset(struct ncr53c9x_softc *); 114 static int esp_dma_intr(struct ncr53c9x_softc *); 115 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, 116 size_t *, int, size_t *); 117 static void esp_dma_go(struct ncr53c9x_softc *); 118 static void esp_dma_stop(struct ncr53c9x_softc *); 119 static int esp_dma_isactive(struct ncr53c9x_softc *); 120 121 static struct ncr53c9x_glue esp_glue = { 122 esp_read_reg, 123 esp_write_reg, 124 esp_dma_isintr, 125 esp_dma_reset, 126 esp_dma_intr, 127 esp_dma_setup, 128 esp_dma_go, 129 esp_dma_stop, 130 esp_dma_isactive, 131 NULL, /* gl_clear_latched_intr */ 132 }; 133 134 static int espdmaintr(struct esp_softc *); 135 static bool esp_shutdown(device_t, int); 136 137 int 138 espmatch(device_t parent, cfdata_t cf, void *aux) 139 { 140 struct confargs *ca = aux; 141 142 if (strcmp(ca->ca_name, "53c94") != 0) 143 return 0; 144 145 if (ca->ca_nreg != 16) 146 return 0; 147 if (ca->ca_nintr != 8) 148 return 0; 149 150 return 1; 151 } 152 153 /* 154 * Attach this instance, and then all the sub-devices 155 */ 156 void 157 espattach(device_t parent, device_t self, void *aux) 158 { 159 struct esp_softc *esc = device_private(self); 160 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 161 struct confargs *ca = aux; 162 u_int *reg; 163 int sz; 164 165 /* 166 * Set up glue for MI code early; we use some of it here. 167 */ 168 sc->sc_dev = self; 169 sc->sc_glue = &esp_glue; 170 171 esc->sc_node = ca->ca_node; 172 esc->sc_pri = ca->ca_intr[0]; 173 aprint_normal(" irq %d", esc->sc_pri); 174 175 /* 176 * Map my registers in. 177 */ 178 reg = ca->ca_reg; 179 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1], false); 180 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3], false); 181 182 /* Allocate 16-byte aligned DMA command space */ 183 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20, NULL); 184 185 /* Other settings */ 186 sc->sc_id = 7; 187 sz = OF_getprop(ca->ca_node, "clock-frequency", 188 &sc->sc_freq, sizeof(int)); 189 if (sz != sizeof(int)) 190 sc->sc_freq = 25000000; 191 192 /* gimme MHz */ 193 sc->sc_freq /= 1000000; 194 195 /* esc->sc_dma->sc_esp = esc;*/ 196 197 /* 198 * XXX More of this should be in ncr53c9x_attach(), but 199 * XXX should we really poke around the chip that much in 200 * XXX the MI code? Think about this more... 201 */ 202 203 /* 204 * Set up static configuration info. 205 */ 206 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 207 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 208 sc->sc_cfg3 = NCRCFG3_CDB; 209 sc->sc_rev = NCR_VARIANT_NCR53C94; 210 211 /* 212 * XXX minsync and maxxfer _should_ be set up in MI code, 213 * XXX but it appears to have some dependency on what sort 214 * XXX of DMA we're hooked up to, etc. 215 */ 216 217 /* 218 * This is the value used to start sync negotiations 219 * Note that the NCR register "SYNCTP" is programmed 220 * in "clocks per byte", and has a minimum value of 4. 221 * The SCSI period used in negotiation is one-fourth 222 * of the time (in nanoseconds) needed to transfer one byte. 223 * Since the chip's clock is given in MHz, we have the following 224 * formula: 4 * period = (1000 / freq) * 4 225 */ 226 sc->sc_minsync = 1000 / sc->sc_freq; 227 228 sc->sc_maxxfer = 64 * 1024; 229 230 /* and the interrupts */ 231 intr_establish_xname(esc->sc_pri, IST_EDGE, IPL_BIO, ncr53c9x_intr, sc, 232 device_xname(self)); 233 234 /* Do the common parts of attachment. */ 235 sc->sc_adapter.adapt_minphys = minphys; 236 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 237 ncr53c9x_attach(sc); 238 239 /* Turn on target selection using the `DMA' method */ 240 sc->sc_features |= NCR_F_DMASELECT; 241 242 /* Reset SCSI bus when halt. */ 243 if (!pmf_device_register1(self, NULL, NULL, esp_shutdown)) 244 aprint_error_dev(self, "couldn't establish power handler\n"); 245 } 246 247 /* 248 * Glue functions. 249 */ 250 251 uint8_t 252 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 253 { 254 struct esp_softc *esc = (struct esp_softc *)sc; 255 256 return in8(&esc->sc_reg[reg * 16]); 257 /*return (esc->sc_reg[reg * 16]);*/ 258 } 259 260 void 261 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 262 { 263 struct esp_softc *esc = (struct esp_softc *)sc; 264 uint8_t v = val; 265 266 out8(&esc->sc_reg[reg * 16], v); 267 /*esc->sc_reg[reg * 16] = v;*/ 268 } 269 270 int 271 esp_dma_isintr(struct ncr53c9x_softc *sc) 272 { 273 274 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 275 } 276 277 void 278 esp_dma_reset(struct ncr53c9x_softc *sc) 279 { 280 struct esp_softc *esc = (struct esp_softc *)sc; 281 282 dbdma_stop(esc->sc_dmareg); 283 esc->sc_dmaactive = 0; 284 } 285 286 int 287 esp_dma_intr(struct ncr53c9x_softc *sc) 288 { 289 struct esp_softc *esc = (struct esp_softc *)sc; 290 291 return espdmaintr(esc); 292 } 293 294 int 295 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 296 int datain, size_t *dmasize) 297 { 298 struct esp_softc *esc = (struct esp_softc *)sc; 299 dbdma_command_t *cmdp; 300 u_int cmd; 301 u_int va; 302 int count, offset; 303 304 cmdp = esc->sc_dmacmd; 305 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 306 307 count = *dmasize; 308 309 if (count / PAGE_SIZE > 32) 310 panic("%s: transfer size >= 128k", device_xname(sc->sc_dev)); 311 312 esc->sc_dmaaddr = addr; 313 esc->sc_dmalen = len; 314 esc->sc_dmasize = count; 315 316 va = (u_int)*esc->sc_dmaaddr; 317 offset = va & PGOFSET; 318 319 /* if va is not page-aligned, setup the first page */ 320 if (offset != 0) { 321 int rest = PAGE_SIZE - offset; /* the rest of the page */ 322 323 if (count > rest) { /* if continues to next page */ 324 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((void *)va), 325 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 326 DBDMA_BRANCH_NEVER); 327 count -= rest; 328 va += rest; 329 cmdp++; 330 } 331 } 332 333 /* now va is page-aligned */ 334 while (count > PAGE_SIZE) { 335 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, kvtop((void *)va), 336 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 337 count -= PAGE_SIZE; 338 va += PAGE_SIZE; 339 cmdp++; 340 } 341 342 /* the last page (count <= PAGE_SIZE here) */ 343 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 344 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((void *)va), 345 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 346 cmdp++; 347 348 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 349 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 350 351 esc->sc_dma_direction = datain ? D_WRITE : 0; 352 353 return 0; 354 } 355 356 void 357 esp_dma_go(struct ncr53c9x_softc *sc) 358 { 359 struct esp_softc *esc = (struct esp_softc *)sc; 360 361 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 362 esc->sc_dmaactive = 1; 363 } 364 365 void 366 esp_dma_stop(struct ncr53c9x_softc *sc) 367 { 368 struct esp_softc *esc = (struct esp_softc *)sc; 369 370 dbdma_stop(esc->sc_dmareg); 371 esc->sc_dmaactive = 0; 372 } 373 374 int 375 esp_dma_isactive(struct ncr53c9x_softc *sc) 376 { 377 struct esp_softc *esc = (struct esp_softc *)sc; 378 379 return esc->sc_dmaactive; 380 } 381 382 383 /* 384 * Pseudo (chained) interrupt from the esp driver to kick the 385 * current running DMA transfer. I am replying on espintr() to 386 * pickup and clean errors for now 387 * 388 * return 1 if it was a DMA continue. 389 */ 390 int 391 espdmaintr(struct esp_softc *sc) 392 { 393 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 394 int trans, resid; 395 u_long csr = sc->sc_dma_direction; 396 397 #if 0 398 if (csr & D_ERR_PEND) { 399 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 400 DMACSR(sc) |= D_INVALIDATE; 401 snprintb(bits, sizeof(bits), DMACSRBITS, csr); 402 printf("%s: error: csr=%s\n", device_xname(nsc->sc_dev), bits); 403 return -1; 404 } 405 #endif 406 407 /* This is an "assertion" :) */ 408 if (sc->sc_dmaactive == 0) 409 panic("%s: DMA wasn't active", __func__); 410 411 /* dbdma_flush(sc->sc_dmareg); */ 412 413 /* DMA has stopped */ 414 dbdma_stop(sc->sc_dmareg); 415 sc->sc_dmaactive = 0; 416 417 if (sc->sc_dmasize == 0) { 418 /* A "Transfer Pad" operation completed */ 419 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 420 NCR_READ_REG(nsc, NCR_TCL) | 421 (NCR_READ_REG(nsc, NCR_TCM) << 8), 422 NCR_READ_REG(nsc, NCR_TCL), 423 NCR_READ_REG(nsc, NCR_TCM))); 424 return 0; 425 } 426 427 resid = 0; 428 /* 429 * If a transfer onto the SCSI bus gets interrupted by the device 430 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 431 * as residual since the ESP counter registers get decremented as 432 * bytes are clocked into the FIFO. 433 */ 434 if (!(csr & D_WRITE) && 435 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 436 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 437 } 438 439 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 440 /* 441 * `Terminal count' is off, so read the residue 442 * out of the ESP counter registers. 443 */ 444 resid += (NCR_READ_REG(nsc, NCR_TCL) | 445 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 446 ((nsc->sc_cfg2 & NCRCFG2_FE) 447 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 448 : 0)); 449 450 if (resid == 0 && sc->sc_dmasize == 65536 && 451 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 452 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 453 resid = 65536; 454 } 455 456 trans = sc->sc_dmasize - resid; 457 if (trans < 0) { /* transferred < 0 ? */ 458 #if 0 459 /* 460 * This situation can happen in perfectly normal operation 461 * if the ESP is reselected while using DMA to select 462 * another target. As such, don't print the warning. 463 */ 464 printf("%s: xfer (%d) > req (%d)\n", 465 device_xname(nsc->sc_dev), trans, sc->sc_dmasize); 466 #endif 467 trans = sc->sc_dmasize; 468 } 469 470 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 471 NCR_READ_REG(nsc, NCR_TCL), 472 NCR_READ_REG(nsc, NCR_TCM), 473 (nsc->sc_cfg2 & NCRCFG2_FE) 474 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 475 trans, resid)); 476 477 #if 0 478 if (csr & D_WRITE) 479 flushcache(*sc->sc_dmaaddr, trans); 480 #endif 481 482 *sc->sc_dmalen -= trans; 483 *sc->sc_dmaaddr += trans; 484 485 #if 0 /* this is not normal operation just yet */ 486 if (*sc->sc_dmalen == 0 || 487 nsc->sc_phase != nsc->sc_prevphase) 488 return 0; 489 490 /* and again */ 491 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 492 return 1; 493 #endif 494 return 0; 495 } 496 497 bool 498 esp_shutdown(device_t self, int howto) 499 { 500 struct esp_softc *esc; 501 struct ncr53c9x_softc *sc; 502 503 esc = device_private(self); 504 sc = &esc->sc_ncr53c9x; 505 NCRCMD(sc, NCRCMD_RSTSCSI); 506 507 return true; 508 } 509
Indexes created Sun Oct 25 00:26:45 UTC 2026