1 /* $NetBSD: umcpmio.c,v 1.7 2025/09/15 13:23:03 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: umcpmio.c,v 1.7 2025/09/15 13:23:03 thorpej Exp $"); 21 22 /* 23 * Driver for the Microchip MCP2221 / MCP2221A USB multi-io chip 24 */ 25 26 #ifdef _KERNEL_OPT 27 #include "opt_usb.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/types.h> 32 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/file.h> 36 #include <sys/gpio.h> 37 #include <sys/kauth.h> 38 #include <sys/kernel.h> 39 #include <sys/kmem.h> 40 #include <sys/lwp.h> 41 #include <sys/sysctl.h> 42 #include <sys/systm.h> 43 #include <sys/tty.h> 44 #include <sys/vnode.h> 45 46 #include <dev/i2c/i2cvar.h> 47 48 #include <dev/gpio/gpiovar.h> 49 50 #include <dev/hid/hid.h> 51 52 #include <dev/usb/uhidev.h> 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdevs.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbhid.h> 58 59 #include <dev/usb/umcpmio.h> 60 #include <dev/usb/umcpmio_hid_reports.h> 61 #include <dev/usb/umcpmio_io.h> 62 #include <dev/usb/umcpmio_subr.h> 63 64 int umcpmio_send_report(struct umcpmio_softc *, uint8_t *, size_t, uint8_t *, 65 int); 66 67 static const struct usb_devno umcpmio_devs[] = { 68 { USB_VENDOR_MICROCHIP, USB_PRODUCT_MICROCHIP_MCP2221 }, 69 }; 70 #define umcpmio_lookup(v, p) usb_lookup(umcpmio_devs, v, p) 71 72 static int umcpmio_match(device_t, cfdata_t, void *); 73 static void umcpmio_attach(device_t, device_t, void *); 74 static int umcpmio_detach(device_t, int); 75 static int umcpmio_activate(device_t, enum devact); 76 static int umcpmio_verify_sysctl(SYSCTLFN_ARGS); 77 static int umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS); 78 static int umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS); 79 static int umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS); 80 static int umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS); 81 82 #define UMCPMIO_DEBUG 1 83 #ifdef UMCPMIO_DEBUG 84 #define DPRINTF(x) do { if (umcpmiodebug) printf x; } while (0) 85 #define DPRINTFN(n, x) do { if (umcpmiodebug > (n)) printf x; } while (0) 86 int umcpmiodebug = 0; 87 #else 88 #define DPRINTF(x) __nothing 89 #define DPRINTFN(n, x) __nothing 90 #endif 91 92 CFATTACH_DECL_NEW(umcpmio, sizeof(struct umcpmio_softc), umcpmio_match, 93 umcpmio_attach, umcpmio_detach, umcpmio_activate); 94 95 static void 96 WAITMS(int ms) 97 { 98 if (ms > 0) 99 delay(ms * 1000); 100 } 101 102 extern struct cfdriver umcpmio_cd; 103 104 static dev_type_open(umcpmio_dev_open); 105 static dev_type_read(umcpmio_dev_read); 106 static dev_type_write(umcpmio_dev_write); 107 static dev_type_close(umcpmio_dev_close); 108 static dev_type_ioctl(umcpmio_dev_ioctl); 109 110 const struct cdevsw umcpmio_cdevsw = { 111 .d_open = umcpmio_dev_open, 112 .d_close = umcpmio_dev_close, 113 .d_read = umcpmio_dev_read, 114 .d_write = umcpmio_dev_write, 115 .d_ioctl = umcpmio_dev_ioctl, 116 .d_stop = nostop, 117 .d_tty = notty, 118 .d_poll = nopoll, 119 .d_mmap = nommap, 120 .d_kqfilter = nokqfilter, 121 .d_discard = nodiscard, 122 .d_flag = D_OTHER 123 }; 124 125 static const char umcpmio_valid_vrefs[] = 126 "4.096V, 2.048V, 1.024V, OFF, VDD"; 127 128 static const char umcpmio_valid_dcs[] = 129 "75%, 50%, 25%, 0%"; 130 131 static const char umcpmio_valid_cds[] = 132 "375kHz, 750kHz, 1.5MHz, 3MHz, 6MHz, 12MHz, 24MHz"; 133 134 static void 135 umcpmio_dump_buffer(bool enabled, uint8_t *buf, u_int len, const char *name) 136 { 137 int i; 138 139 if (enabled) { 140 DPRINTF(("%s:", name)); 141 for (i = 0; i < len; i++) { 142 DPRINTF((" %02x", buf[i])); 143 } 144 DPRINTF(("\n")); 145 } 146 } 147 148 /* 149 * Communication with the HID function requires sending a HID report 150 * request and then waiting for a response. 151 * 152 * The panic that occurs when trying to use the interrupt... i.e. 153 * attaching though this driver seems to be related to the fact that 154 * a spin lock is held and the USB stack wants to wait. 155 * 156 * The USB stack *IS* going to have to wait for the response from 157 * the device, somehow... 158 * 159 * It didn't seem possible to defer the uhidev_write to a thread. 160 * Attempts to yield() while spinning hard also did not work and 161 * not yield()ing didn't allow anything else to run. 162 * 163 */ 164 165 /* 166 * This is the panic you will get: 167 * 168 * panic: kernel diagnostic assertion "ci->ci_mtx_count == -1" failed: file "../../../../kern/kern_synch.c", line 762 mi_switch: cpu0: ci_mtx_count (-2) != -1 (block with spin-mutex held) 169 */ 170 171 static void 172 umcpmio_uhidev_intr(void *cookie, void *ibuf, u_int len) 173 { 174 struct umcpmio_softc *sc = cookie; 175 176 if (sc->sc_dying) 177 return; 178 179 DPRINTFN(30, ("umcpmio_uhidev_intr: len=%d\n", len)); 180 181 mutex_enter(&sc->sc_res_mutex); 182 switch(len) { 183 case MCP2221_RES_BUFFER_SIZE: 184 if (sc->sc_res_buffer != NULL) { 185 memcpy(sc->sc_res_buffer, ibuf, 186 MCP2221_RES_BUFFER_SIZE); 187 sc->sc_res_ready = true; 188 cv_signal(&sc->sc_res_cv); 189 } else { 190 int d = umcpmiodebug; 191 device_printf(sc->sc_dev, 192 "umcpmio_uhidev_intr: NULL sc_res_buffer:" 193 " len=%d\n", 194 len); 195 umcpmiodebug = 20; 196 umcpmio_dump_buffer(true, (uint8_t *)ibuf, len, 197 "umcpmio_uhidev_intr: ibuf"); 198 umcpmiodebug = d; 199 } 200 201 break; 202 default: 203 device_printf(sc->sc_dev, 204 "umcpmio_uhidev_intr: Unknown interrupt length: %d", 205 len); 206 break; 207 } 208 mutex_exit(&sc->sc_res_mutex); 209 } 210 211 /* Send a HID report. This needs to be called with the action mutex held */ 212 213 int 214 umcpmio_send_report(struct umcpmio_softc *sc, uint8_t *sendbuf, 215 size_t sendlen, uint8_t *resbuf, int timeout) 216 { 217 int err = 0; 218 int err_count = 0; 219 220 if (sc->sc_dying) 221 return EIO; 222 223 KASSERT(mutex_owned(&sc->sc_action_mutex)); 224 225 if (sc->sc_res_buffer != NULL) { 226 device_printf(sc->sc_dev, 227 "umcpmio_send_report: sc->sc_res_buffer is not NULL\n"); 228 } 229 sc->sc_res_buffer = resbuf; 230 sc->sc_res_ready = false; 231 232 err = uhidev_write(sc->sc_hdev, sendbuf, sendlen); 233 234 if (err) { 235 DPRINTF(("umcpmio_send_report: uhidev_write errored with:" 236 " err=%d\n", err)); 237 goto out; 238 } 239 240 DPRINTFN(30, ("umcpmio_send_report: about to wait on cv. err=%d\n", 241 err)); 242 243 mutex_enter(&sc->sc_res_mutex); 244 while (!sc->sc_res_ready) { 245 DPRINTFN(20, ("umcpmio_send_report: LOOP for response." 246 " sc_res_ready=%d, err_count=%d, timeout=%d\n", 247 sc->sc_res_ready, err_count, mstohz(timeout))); 248 249 err = cv_timedwait_sig(&sc->sc_res_cv, &sc->sc_res_mutex, 250 mstohz(timeout)); 251 252 /* 253 * We are only going to allow this to loop on an error, 254 * any error at all, so many times. 255 */ 256 if (err) { 257 DPRINTF(("umcpmio_send_report:" 258 " cv_timedwait_sig reported an error:" 259 " err=%d, sc->sc_res_ready=%d\n", 260 err, sc->sc_res_ready)); 261 err_count++; 262 } 263 264 /* 265 * The CV was interrupted, but the buffer is ready so, 266 * clear the error and break out. 267 */ 268 if ((err == ERESTART) && (sc->sc_res_ready)) { 269 DPRINTF(("umcpmio_send_report:" 270 " ERESTART and buffer is ready\n")); 271 err = 0; 272 break; 273 } 274 275 /* 276 * Too many times though the loop, just break out. Turn 277 * a ERESTART (interruption) into a I/O error at this point. 278 */ 279 if (err_count > sc->sc_response_errcnt) { 280 DPRINTF(("umcpmio_send_report: err_count exceeded:" 281 " err=%d\n", err)); 282 if (err == ERESTART) 283 err = EIO; 284 break; 285 } 286 287 /* This is a normal timeout, without interruption, try again */ 288 if (err == EWOULDBLOCK) { 289 DPRINTF(("umcpmio_send_report: EWOULDBLOCK:" 290 " err_count=%d\n", err_count)); 291 continue; 292 } 293 294 /* 295 * The CV was interrupted and the buffer wasn't filled 296 * in, so try again 297 */ 298 if ((err == ERESTART) && (!sc->sc_res_ready)) { 299 DPRINTF(("umcpmio_send_report:" 300 " ERESTART and buffer is NOT ready." 301 " err_count=%d\n", err_count)); 302 continue; 303 } 304 } 305 306 sc->sc_res_buffer = NULL; 307 sc->sc_res_ready = false; 308 mutex_exit(&sc->sc_res_mutex); 309 310 /* Turn most errors into an I/O error */ 311 if (err && 312 err != ERESTART) 313 err = EIO; 314 315 out: 316 return err; 317 } 318 319 /* These are standard gpio reads and set calls */ 320 321 static int 322 umcpmio_gpio_pin_read(void *arg, int pin) 323 { 324 struct umcpmio_softc *sc = arg; 325 int r = GPIO_PIN_LOW; 326 327 r = umcpmio_get_gpio_value(sc, pin, true); 328 329 return r; 330 } 331 332 static void 333 umcpmio_gpio_pin_write(void *arg, int pin, int value) 334 { 335 struct umcpmio_softc *sc = arg; 336 337 umcpmio_set_gpio_value_one(sc, pin, value, true); 338 } 339 340 /* 341 * Internal function that does the dirty work of setting a gpio 342 * pin to its "type". 343 * 344 * There are really two ways to do some of this, one is to set the pin 345 * to input and output, or whatever, using SRAM calls, the other is to 346 * use the GPIO config calls to set input and output and SRAM for 347 * everything else. This just uses SRAM for everything. 348 */ 349 350 static int 351 umcpmio_gpio_pin_ctlctl(void *arg, int pin, int flags) 352 { 353 struct umcpmio_softc *sc = arg; 354 struct mcp2221_set_sram_req set_sram_req; 355 struct mcp2221_set_sram_res set_sram_res; 356 struct mcp2221_get_sram_res current_sram_res; 357 struct mcp2221_get_gpio_cfg_res current_gpio_cfg_res; 358 int err = 0; 359 360 if (sc->sc_dying) 361 return 0; 362 363 KASSERT(mutex_owned(&sc->sc_action_mutex)); 364 365 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 366 if (err) 367 goto out; 368 369 err = umcpmio_get_gpio_cfg(sc, ¤t_gpio_cfg_res, false); 370 if (err) 371 goto out; 372 373 /* 374 * You can't just set one pin, you must set all of them, so copy the 375 * current settings for the pin we are not messing with. 376 * 377 * And, yes, of course, if the MCP-2210 is ever supported with this 378 * driver, this sort of unrolling will need to be turned into 379 * something different, but for now, just unroll as there are only 380 * 4 pins to care about. 381 * 382 */ 383 384 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 385 switch (pin) { 386 case 0: 387 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 388 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 389 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 390 break; 391 case 1: 392 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 393 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 394 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 395 break; 396 case 2: 397 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 398 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 399 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 400 break; 401 case 3: 402 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 403 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 404 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 405 break; 406 } 407 umcpmio_set_gpio_designation_sram(&set_sram_req, pin, flags); 408 umcpmio_set_gpio_dir_sram(&set_sram_req, pin, flags); 409 410 /* 411 * This part is unfortunate... if a pin is set to output, the 412 * value set on the pin is not mirrored by the chip into SRAM, 413 * but the chip will use the value from SRAM to set the value of 414 * the pin. What this means is that we have to learn the value 415 * from the GPIO config and make sure it is set properly when 416 * updating SRAM. 417 */ 418 419 if (current_gpio_cfg_res.gp0_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 420 if (current_gpio_cfg_res.gp0_pin_value == 1) { 421 set_sram_req.gp0_settings |= 422 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 423 } else { 424 set_sram_req.gp0_settings &= 425 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 426 } 427 } 428 if (current_gpio_cfg_res.gp1_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 429 if (current_gpio_cfg_res.gp1_pin_value == 1) { 430 set_sram_req.gp1_settings |= 431 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 432 } else { 433 set_sram_req.gp1_settings &= 434 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 435 } 436 } 437 if (current_gpio_cfg_res.gp2_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 438 if (current_gpio_cfg_res.gp2_pin_value == 1) { 439 set_sram_req.gp2_settings |= 440 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 441 } else { 442 set_sram_req.gp2_settings &= 443 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 444 } 445 } 446 if (current_gpio_cfg_res.gp3_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 447 if (current_gpio_cfg_res.gp3_pin_value == 1) { 448 set_sram_req.gp3_settings |= 449 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 450 } else { 451 set_sram_req.gp3_settings &= 452 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 453 } 454 } 455 456 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 457 if (err) 458 goto out; 459 460 umcpmio_dump_buffer(sc->sc_dumpbuffer, 461 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 462 "umcpmio_gpio_pin_ctlctl set sram buffer copy"); 463 if (set_sram_res.cmd != MCP2221_CMD_SET_SRAM || 464 set_sram_res.completion != MCP2221_CMD_COMPLETE_OK) { 465 device_printf(sc->sc_dev, "umcpmio_gpio_pin_ctlctl:" 466 " not the command desired, or error: %02x %02x\n", 467 set_sram_res.cmd, 468 set_sram_res.completion); 469 err = EIO; 470 goto out; 471 } 472 473 sc->sc_gpio_pins[pin].pin_flags = flags; 474 err = 0; 475 476 out: 477 return err; 478 } 479 480 static void 481 umcpmio_gpio_pin_ctl(void *arg, int pin, int flags) 482 { 483 struct umcpmio_softc *sc = arg; 484 485 if (sc->sc_dying) 486 return; 487 488 mutex_enter(&sc->sc_action_mutex); 489 umcpmio_gpio_pin_ctlctl(sc, pin, flags); 490 mutex_exit(&sc->sc_action_mutex); 491 } 492 493 /* 494 * XXX - 495 * 496 * Since testing of gpio interrupts wasn't possible, this part probably 497 * is not complete. At the very least, there is a scheduled callout 498 * that needs to exist to read the interrupt status. The chip does not 499 * send anything on its own when the interrupt happens. 500 */ 501 502 static void * 503 umcpmio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 504 int (*func)(void *), void *arg) 505 { 506 struct umcpmio_softc *sc = vsc; 507 struct umcpmio_irq *irq = &sc->sc_gpio_irqs[0]; 508 struct mcp2221_set_sram_req set_sram_req; 509 struct mcp2221_set_sram_res set_sram_res; 510 struct mcp2221_get_sram_res current_sram_res; 511 int err = 0; 512 513 if (sc->sc_dying) 514 return NULL; 515 516 irq->sc_gpio_irqfunc = func; 517 irq->sc_gpio_irqarg = arg; 518 519 DPRINTF(("umcpmio_intr_establish: pin=%d, irqmode=%04x\n", 520 pin, irqmode)); 521 522 mutex_enter(&sc->sc_action_mutex); 523 524 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 525 if (err) 526 goto out; 527 528 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 529 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 530 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 531 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 532 umcpmio_set_gpio_irq_sram(&set_sram_req, irqmode); 533 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 534 if (err) { 535 device_printf(sc->sc_dev, "umcpmio_intr_establish:" 536 " set sram error: err=%d\n", 537 err); 538 goto out; 539 } 540 umcpmio_dump_buffer(sc->sc_dumpbuffer, 541 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 542 "umcpmio_intr_establish set sram buffer copy"); 543 if (set_sram_res.cmd != MCP2221_CMD_SET_SRAM || 544 set_sram_res.completion != MCP2221_CMD_COMPLETE_OK) { 545 device_printf(sc->sc_dev, "umcpmio_intr_establish:" 546 " not the command desired, or error: %02x %02x\n", 547 set_sram_res.cmd, 548 set_sram_res.completion); 549 goto out; 550 } 551 552 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_ALT2; 553 554 out: 555 mutex_exit(&sc->sc_action_mutex); 556 557 return irq; 558 } 559 560 static void 561 umcpmio_gpio_intr_disestablish(void *vsc, void *ih) 562 { 563 struct umcpmio_softc *sc = vsc; 564 struct mcp2221_set_sram_req set_sram_req; 565 struct mcp2221_set_sram_res set_sram_res; 566 struct mcp2221_get_sram_res current_sram_res; 567 int err = 0; 568 569 if (sc->sc_dying) 570 return; 571 572 DPRINTF(("umcpmio_intr_disestablish:\n")); 573 574 mutex_enter(&sc->sc_action_mutex); 575 576 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 577 if (err) 578 goto out; 579 580 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 581 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 582 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 583 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 584 umcpmio_set_gpio_irq_sram(&set_sram_req, 0); 585 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, true); 586 if (err) { 587 device_printf(sc->sc_dev, "umcpmio_intr_disestablish:" 588 " set sram error: err=%d\n", 589 err); 590 goto out; 591 } 592 593 umcpmio_dump_buffer(sc->sc_dumpbuffer, 594 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 595 "umcpmio_intr_disestablish set sram buffer copy"); 596 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 597 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 598 device_printf(sc->sc_dev, "umcpmio_intr_disestablish:" 599 " not the command desired, or error: %02x %02x\n", 600 set_sram_res.cmd, 601 set_sram_res.completion); 602 goto out; 603 } 604 605 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_INPUT; 606 607 out: 608 mutex_exit(&sc->sc_action_mutex); 609 } 610 611 static bool 612 umcpmio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 613 { 614 615 if (pin < 0 || pin >= MCP2221_NPINS) { 616 DPRINTF(("umcpmio_gpio_intrstr:" 617 " pin %d less than zero or too big\n", 618 pin)); 619 return false; 620 } 621 622 if (pin != 1) { 623 DPRINTF(("umcpmio_gpio_intrstr: pin %d was not 1\n", 624 pin)); 625 return false; 626 } 627 628 snprintf(buf, buflen, "GPIO %d", pin); 629 630 return true; 631 } 632 633 /* Clear status of the I2C engine */ 634 635 static int 636 umcpmio_i2c_clear(struct umcpmio_softc *sc, bool takemutex) 637 { 638 int err = 0; 639 struct mcp2221_status_req status_req; 640 struct mcp2221_status_res status_res; 641 642 memset(&status_req, 0, MCP2221_REQ_BUFFER_SIZE); 643 status_req.cmd = MCP2221_CMD_STATUS; 644 status_req.cancel_transfer = MCP2221_I2C_DO_CANCEL; 645 646 if (takemutex) 647 mutex_enter(&sc->sc_action_mutex); 648 err = umcpmio_send_report(sc, 649 (uint8_t *)&status_req, MCP2221_REQ_BUFFER_SIZE, 650 (uint8_t *)&status_res, sc->sc_cv_wait); 651 if (takemutex) 652 mutex_exit(&sc->sc_action_mutex); 653 if (err) { 654 device_printf(sc->sc_dev, "umcpmio_i2c_clear: request error:" 655 " err=%d\n", err); 656 err = EIO; 657 goto out; 658 } 659 660 umcpmio_dump_buffer(sc->sc_dumpbuffer, 661 (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, 662 "umcpmio_i2c_clear buffer copy"); 663 664 if (status_res.cmd != MCP2221_CMD_STATUS && 665 status_res.completion != MCP2221_CMD_COMPLETE_OK) { 666 device_printf(sc->sc_dev, "umcpmio_i2c_clear:" 667 " cmd exec: not the command desired, or error:" 668 " %02x %02x\n", 669 status_res.cmd, 670 status_res.completion); 671 err = EIO; 672 goto out; 673 } 674 675 umcpmio_dump_buffer(true, 676 (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, 677 "umcpmio_i2c_clear res buffer"); 678 679 out: 680 return err; 681 } 682 683 /* 684 * There isn't much required to acquire or release the I2C bus, but the man 685 * pages says these are needed 686 */ 687 688 static int 689 umcpmio_acquire_bus(void *v, int flags) 690 { 691 return 0; 692 } 693 694 static void 695 umcpmio_release_bus(void *v, int flags) 696 { 697 return; 698 } 699 700 /* 701 * The I2C write and I2C read functions mostly use an algorithm that Adafruit 702 * came up with in their Python based driver. A lot of other people have used 703 * this same algorithm to good effect. If changes are made to the I2C read and 704 * write functions, it is HIGHLY advisable that a MCP2221 or MCP2221A be on 705 * hand to test them. 706 */ 707 708 /* This is what is considered a fatal return from the engine. */ 709 710 static bool 711 umcpmio_i2c_fatal(uint8_t state) 712 { 713 int r = false; 714 715 if (state == MCP2221_ENGINE_ADDRNACK || 716 state == MCP2221_ENGINE_STARTTIMEOUT || 717 state == MCP2221_ENGINE_REPSTARTTIMEOUT || 718 state == MCP2221_ENGINE_STOPTIMEOUT || 719 state == MCP2221_ENGINE_READTIMEOUT || 720 state == MCP2221_ENGINE_WRITETIMEOUT || 721 state == MCP2221_ENGINE_ADDRTIMEOUT) 722 r = true; 723 return r; 724 } 725 726 static int 727 umcpmio_i2c_write(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 728 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, 729 int flags) 730 { 731 struct mcp2221_i2c_req i2c_req; 732 struct mcp2221_i2c_res i2c_res; 733 struct mcp2221_status_res status_res; 734 int remaining; 735 int err = 0; 736 uint8_t cmd; 737 size_t totallen = 0; 738 int wretry = sc->sc_retry_busy_write; 739 int wsretry = sc->sc_retry_busy_write; 740 741 err = umcpmio_get_status(sc, &status_res, true); 742 if (err) 743 goto out; 744 if (status_res.internal_i2c_state != 0) { 745 DPRINTF(("umcpmio_i2c_write: internal state not zero," 746 " clearing. internal_i2c_state=%02x\n", 747 status_res.internal_i2c_state)); 748 err = umcpmio_i2c_clear(sc, true); 749 } 750 if (err) 751 goto out; 752 753 if (cmdbuf != NULL) 754 totallen += cmdlen; 755 if (databuf != NULL) 756 totallen += datalen; 757 758 again: 759 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 760 cmd = MCP2221_I2C_WRITE_DATA_NS; 761 if (I2C_OP_STOP_P(op)) 762 cmd = MCP2221_I2C_WRITE_DATA; 763 i2c_req.cmd = cmd; 764 i2c_req.lsblen = totallen; 765 i2c_req.msblen = 0; 766 i2c_req.slaveaddr = addr << 1; 767 768 remaining = 0; 769 if (cmdbuf != NULL) { 770 memcpy(&i2c_req.data[0], cmdbuf, cmdlen); 771 remaining = cmdlen; 772 } 773 if (databuf != NULL) 774 memcpy(&i2c_req.data[remaining], databuf, datalen); 775 776 DPRINTF(("umcpmio_i2c_write: I2C WRITE: cmd: %02x\n", cmd)); 777 umcpmio_dump_buffer(sc->sc_dumpbuffer, 778 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 779 "umcpmio_i2c_write: write req buffer copy"); 780 781 mutex_enter(&sc->sc_action_mutex); 782 err = umcpmio_send_report(sc, 783 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 784 (uint8_t *)&i2c_res, sc->sc_cv_wait); 785 mutex_exit(&sc->sc_action_mutex); 786 if (err) { 787 device_printf(sc->sc_dev, "umcpmio_i2c_write request error:" 788 " err=%d\n", err); 789 err = EIO; 790 goto out; 791 } 792 793 umcpmio_dump_buffer(sc->sc_dumpbuffer, 794 (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, 795 "umcpmio_i2c_write: write res buffer copy"); 796 if (i2c_res.cmd == cmd && 797 i2c_res.completion == MCP2221_CMD_COMPLETE_OK) { 798 /* 799 * Adafruit does a read back of the status at 800 * this point. We choose not to do that. That 801 * is done later anyway, and it seemed to be 802 * redundent. 803 */ 804 } else if (i2c_res.cmd == cmd && 805 i2c_res.completion == MCP2221_I2C_ENGINE_BUSY) { 806 DPRINTF(("umcpmio_i2c_write:" 807 " I2C engine busy\n")); 808 809 if (umcpmio_i2c_fatal(i2c_res.internal_i2c_state)) { 810 err = EIO; 811 goto out; 812 } 813 wretry--; 814 if (wretry > 0) { 815 WAITMS(sc->sc_busy_delay); 816 goto again; 817 } else { 818 err = EBUSY; 819 goto out; 820 } 821 } else { 822 device_printf(sc->sc_dev, "umcpmio_i2c_write:" 823 " not the command desired, or error:" 824 " %02x %02x\n", 825 i2c_res.cmd, 826 i2c_res.completion); 827 err = EIO; 828 goto out; 829 } 830 831 while (wsretry > 0) { 832 wsretry--; 833 834 DPRINTF(("umcpmio_i2c_write: checking status loop:" 835 " wcretry=%d\n", wsretry)); 836 837 err = umcpmio_get_status(sc, &status_res, true); 838 if (err) { 839 err = EIO; 840 break; 841 } 842 umcpmio_dump_buffer(sc->sc_dumpbuffer, 843 (uint8_t *)&status_res, 844 MCP2221_RES_BUFFER_SIZE, 845 "umcpmio_i2c_write post check status"); 846 /* 847 * Since there isn't any documentation on what 848 * some of the internal state means, it isn't 849 * clear that this is any different than than 850 * MCP2221_ENGINE_ADDRNACK in the other state 851 * register. 852 */ 853 854 if (status_res.internal_i2c_state20 & 855 MCP2221_ENGINE_T1_MASK_NACK) { 856 DPRINTF(("umcpmio_i2c_write post check:" 857 " engine internal state T1 says NACK\n")); 858 err = EIO; 859 break; 860 } 861 if (status_res.internal_i2c_state == 0) { 862 DPRINTF(("umcpmio_i2c_write post check:" 863 " engine internal state is ZERO\n")); 864 err = 0; 865 break; 866 } 867 if (status_res.internal_i2c_state == 868 MCP2221_ENGINE_WRITINGNOSTOP && 869 cmd == MCP2221_I2C_WRITE_DATA_NS) { 870 DPRINTF(("umcpmio_i2c_write post check:" 871 " engine internal state is WRITINGNOSTOP\n")); 872 err = 0; 873 break; 874 } 875 if (umcpmio_i2c_fatal(status_res.internal_i2c_state)) { 876 DPRINTF(("umcpmio_i2c_write post check:" 877 " engine internal state is fatal: %02x\n", 878 status_res.internal_i2c_state)); 879 err = EIO; 880 break; 881 } 882 WAITMS(sc->sc_busy_delay); 883 } 884 885 out: 886 return err; 887 } 888 889 /* 890 * This one deviates a bit from Adafruit in that is supports a straight 891 * read and a write + read. That is, write a register to read from and 892 * then do the read. 893 */ 894 895 static int 896 umcpmio_i2c_read(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 897 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int 898 flags) 899 { 900 struct mcp2221_i2c_req i2c_req; 901 struct mcp2221_i2c_res i2c_res; 902 struct mcp2221_i2c_fetch_req i2c_fetch_req; 903 struct mcp2221_i2c_fetch_res i2c_fetch_res; 904 struct mcp2221_status_res status_res; 905 int err = 0; 906 uint8_t cmd; 907 int rretry = sc->sc_retry_busy_read; 908 909 if (cmdbuf != NULL) { 910 DPRINTF(("umcpmio_i2c_read: has a cmdbuf, doing write first:" 911 " addr=%02x\n", addr)); 912 err = umcpmio_i2c_write(sc, I2C_OP_WRITE, addr, cmdbuf, cmdlen, 913 NULL, 0, flags); 914 } 915 if (err) 916 goto out; 917 918 err = umcpmio_get_status(sc, &status_res, true); 919 if (err) 920 goto out; 921 922 if (status_res.internal_i2c_state != 0 && 923 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 924 DPRINTF(("umcpmio_i2c_read:" 925 " internal state not zero and not WRITINGNOSTOP," 926 " clearing. internal_i2c_state=%02x\n", 927 status_res.internal_i2c_state)); 928 err = umcpmio_i2c_clear(sc, true); 929 } 930 if (err) 931 goto out; 932 933 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 934 if (cmdbuf == NULL && 935 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 936 cmd = MCP2221_I2C_READ_DATA; 937 } else { 938 cmd = MCP2221_I2C_READ_DATA_RS; 939 } 940 941 /* 942 * The chip apparently can't do a READ without a STOP 943 * operation. Report that, and try treating it like a READ 944 * with a STOP. This won't work for a lot of devices. 945 */ 946 947 if (!I2C_OP_STOP_P(op) && sc->sc_reportreadnostop) { 948 device_printf(sc->sc_dev, 949 "umcpmio_i2c_read: ************ called with READ" 950 " without STOP ***************\n"); 951 } 952 953 i2c_req.cmd = cmd; 954 i2c_req.lsblen = datalen; 955 i2c_req.msblen = 0; 956 i2c_req.slaveaddr = (addr << 1) | 0x01; 957 958 DPRINTF(("umcpmio_i2c_read: I2C READ normal read:" 959 " cmd=%02x, addr=%02x\n", cmd, addr)); 960 961 umcpmio_dump_buffer(sc->sc_dumpbuffer, 962 (uint8_t *)&i2c_req, MCP2221_RES_BUFFER_SIZE, 963 "umcpmio_i2c_read normal read req buffer copy"); 964 965 mutex_enter(&sc->sc_action_mutex); 966 err = umcpmio_send_report(sc, 967 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 968 (uint8_t *)&i2c_res, sc->sc_cv_wait); 969 mutex_exit(&sc->sc_action_mutex); 970 971 if (err) { 972 device_printf(sc->sc_dev, "umcpmio_i2c_read request error:" 973 " cmd=%02x, err=%d\n", cmd, err); 974 err = EIO; 975 goto out; 976 } 977 978 umcpmio_dump_buffer(sc->sc_dumpbuffer, 979 (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, 980 "umcpmio_i2c_read read-request response buffer copy"); 981 982 while (rretry > 0) { 983 rretry--; 984 DPRINTF(("umcpmio_i2c_read: fetch loop: rretry=%d\n", rretry)); 985 err = 0; 986 memset(&i2c_fetch_req, 0, MCP2221_REQ_BUFFER_SIZE); 987 i2c_fetch_req.cmd = MCP2221_CMD_I2C_FETCH_READ_DATA; 988 mutex_enter(&sc->sc_action_mutex); 989 err = umcpmio_send_report(sc, 990 (uint8_t *)&i2c_fetch_req, MCP2221_REQ_BUFFER_SIZE, 991 (uint8_t *)&i2c_fetch_res, sc->sc_cv_wait); 992 mutex_exit(&sc->sc_action_mutex); 993 umcpmio_dump_buffer(sc->sc_dumpbuffer, 994 (uint8_t *)&i2c_fetch_req, MCP2221_RES_BUFFER_SIZE, 995 "umcpmio_i2c_read fetch res buffer copy"); 996 997 if (i2c_fetch_res.cmd != MCP2221_CMD_I2C_FETCH_READ_DATA) { 998 device_printf(sc->sc_dev, "umcpmio_i2c_read:" 999 " fetch2: not the command desired: %02x\n", 1000 i2c_fetch_res.cmd); 1001 err = EIO; 1002 break; 1003 } 1004 if (i2c_fetch_res.completion == 1005 MCP2221_FETCH_READ_PARTIALDATA || 1006 i2c_fetch_res.fetchlen == MCP2221_FETCH_READERROR) { 1007 DPRINTF(("umcpmio_i2c_read: fetch loop:" 1008 " partial data or read error:" 1009 " completion=%02x, fetchlen=%02x\n", 1010 i2c_fetch_res.completion, 1011 i2c_fetch_res.fetchlen)); 1012 WAITMS(sc->sc_busy_delay); 1013 err = EAGAIN; 1014 continue; 1015 } 1016 if (i2c_fetch_res.internal_i2c_state == 1017 MCP2221_ENGINE_ADDRNACK) { 1018 DPRINTF(("umcpmio_i2c_read:" 1019 " fetch loop: engine NACK\n")); 1020 err = EIO; 1021 break; 1022 } 1023 if (i2c_fetch_res.internal_i2c_state == 0 && 1024 i2c_fetch_res.fetchlen == 0) { 1025 DPRINTF(("umcpmio_i2c_read: fetch loop:" 1026 " internal state and fetch len are ZERO\n")); 1027 err = 0; 1028 break; 1029 } 1030 if (i2c_fetch_res.internal_i2c_state == 1031 MCP2221_ENGINE_READPARTIAL || 1032 i2c_fetch_res.internal_i2c_state == 1033 MCP2221_ENGINE_READCOMPLETE) { 1034 DPRINTF(("umcpmio_i2c_read:" 1035 " fetch loop: read partial or" 1036 " read complete: internal_i2c_state=%02x\n", 1037 i2c_fetch_res.internal_i2c_state)); 1038 err = 0; 1039 break; 1040 } 1041 } 1042 if (err == EAGAIN) 1043 err = ETIMEDOUT; 1044 if (err) 1045 goto out; 1046 1047 if (databuf == NULL || 1048 i2c_fetch_res.fetchlen == MCP2221_FETCH_READERROR) { 1049 DPRINTF(("umcpmio_i2c_read: copy data:" 1050 " databuf is NULL\n")); 1051 goto out; 1052 } 1053 1054 const int size = uimin(i2c_fetch_res.fetchlen, datalen); 1055 DPRINTF(("umcpmio_i2c_read: copy data: size=%d, fetchlen=%d\n", 1056 size, i2c_fetch_res.fetchlen)); 1057 if (size > 0) { 1058 memcpy(databuf, &i2c_fetch_res.data[0], size); 1059 } 1060 1061 out: 1062 return err; 1063 } 1064 1065 static int 1066 umcpmio_i2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 1067 size_t cmdlen, void *databuf, size_t datalen, int flags) 1068 { 1069 struct umcpmio_softc *sc = v; 1070 size_t totallen = 0; 1071 int err = 0; 1072 1073 if (addr > 0x7f) 1074 return ENOTSUP; 1075 1076 if (cmdbuf != NULL) 1077 totallen += cmdlen; 1078 if (databuf != NULL) 1079 totallen += datalen; 1080 1081 /* 1082 * There is a way to do a transfer that is larger than 60 bytes, 1083 * but it requires that your break the transfer up into pieces and 1084 * send them in 60 byte chunks. We just won't support that right now. 1085 * It would be somewhat unusual for there to be a transfer that big, 1086 * unless you are trying to do block transfers and that isn't natively 1087 * supported by the chip anyway... so those have to be broken up and 1088 * sent as bytes. 1089 */ 1090 1091 if (totallen > 60) 1092 return ENOTSUP; 1093 1094 if (I2C_OP_WRITE_P(op)) { 1095 err = umcpmio_i2c_write(sc, op, addr, cmdbuf, cmdlen, 1096 databuf, datalen, flags); 1097 1098 DPRINTF(("umcpmio_exec: I2C WRITE: err=%d\n", err)); 1099 } else { 1100 err = umcpmio_i2c_read(sc, op, addr, cmdbuf, cmdlen, 1101 databuf, datalen, flags); 1102 1103 DPRINTF(("umcpmio_exec: I2C READ: err=%d\n", err)); 1104 } 1105 1106 return err; 1107 } 1108 1109 /* Accessing the ADC and DAC part of the chip */ 1110 1111 #define UMCPMIO_DEV_UNIT(m) ((m) & 0x80 ? ((m) & 0x7f) / 3 : (m)) 1112 #define UMCPMIO_DEV_WHAT(m) ((m) & 0x80 ? (((m) & 0x7f) % 3) + 1 : CONTROL_DEV) 1113 1114 static int 1115 umcpmio_dev_open(dev_t dev, int flags, int fmt, struct lwp *l) 1116 { 1117 struct umcpmio_softc *sc; 1118 int dunit; 1119 int pin = -1; 1120 int error = 0; 1121 1122 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1123 if (!sc) 1124 return ENXIO; 1125 1126 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1127 1128 if (sc->sc_dev_open[dunit]) { 1129 DPRINTF(("umcpmio_dev_open: dunit=%d BUSY\n", dunit)); 1130 return EBUSY; 1131 } 1132 1133 /* 1134 * The control device only allows for ioctl calls, so pretty 1135 * much allow any sort of access. For the ADC, you perform a 1136 * strict O_RDONLY and for the DAC a strict O_WRONLY. It is an 1137 * error to try and do a O_RDWR It makes little sense to try 1138 * and support select or poll. The ADC and DAC are always 1139 * available for use. 1140 */ 1141 1142 if (dunit != CONTROL_DEV && 1143 ((flags & FREAD) && (flags & FWRITE))) { 1144 DPRINTF(("umcpmio_dev_open: Not CONTROL device and trying to" 1145 " do READ and WRITE\n")); 1146 return EINVAL; 1147 } 1148 1149 /* 1150 * Ya, this unrolling will also have to be changed if the MCP-2210 is 1151 * supported. There are currently only 4 pins, so don't worry too much 1152 * about it. The MCP-2210 has RAM, so there would be a fifth for it. 1153 */ 1154 1155 mutex_enter(&sc->sc_action_mutex); 1156 if (dunit != CONTROL_DEV) { 1157 switch (dunit) { 1158 case GP1_DEV: 1159 pin = 1; 1160 break; 1161 case GP2_DEV: 1162 pin = 2; 1163 break; 1164 case GP3_DEV: 1165 pin = 3; 1166 break; 1167 default: 1168 error = EINVAL; 1169 goto out; 1170 } 1171 /* 1172 * XXX - we can probably do better here... it 1173 * doesn't remember what the pin was set to and 1174 * probably should. 1175 */ 1176 if (flags & FREAD) { 1177 error = umcpmio_gpio_pin_ctlctl(sc, pin, 1178 GPIO_PIN_ALT0); 1179 } else { 1180 if (pin == 1) { 1181 error = EINVAL; 1182 } else { 1183 error = umcpmio_gpio_pin_ctlctl(sc, 1184 pin, GPIO_PIN_ALT1); 1185 } 1186 } 1187 } 1188 if (error) 1189 goto out; 1190 sc->sc_dev_open[dunit] = true; 1191 out: 1192 mutex_exit(&sc->sc_action_mutex); 1193 1194 DPRINTF(("umcpmio_dev_open: Opened dunit=%d, pin=%d, error=%d\n", 1195 dunit, pin, error)); 1196 1197 return error; 1198 } 1199 1200 /* Read an ADC value */ 1201 1202 static int 1203 umcpmio_dev_read(dev_t dev, struct uio *uio, int flags) 1204 { 1205 struct umcpmio_softc *sc; 1206 struct mcp2221_status_res status_res; 1207 int dunit; 1208 int error = 0; 1209 uint8_t adc_lsb; 1210 uint8_t adc_msb; 1211 uint16_t buf; 1212 1213 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1214 if (sc == NULL) 1215 return ENXIO; 1216 1217 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1218 1219 if (dunit == CONTROL_DEV) { 1220 error = EINVAL; 1221 goto out; 1222 } 1223 1224 while (uio->uio_resid && !sc->sc_dying) { 1225 error = umcpmio_get_status(sc, &status_res, true); 1226 if (error) 1227 break; 1228 switch (dunit) { 1229 case GP1_DEV: 1230 adc_lsb = status_res.adc_channel0_lsb; 1231 adc_msb = status_res.adc_channel0_msb; 1232 break; 1233 case GP2_DEV: 1234 adc_lsb = status_res.adc_channel1_lsb; 1235 adc_msb = status_res.adc_channel1_msb; 1236 break; 1237 case GP3_DEV: 1238 adc_lsb = status_res.adc_channel2_lsb; 1239 adc_msb = status_res.adc_channel2_msb; 1240 break; 1241 default: 1242 error = EINVAL; 1243 break; 1244 } 1245 if (error) 1246 break; 1247 if (sc->sc_dying) 1248 break; 1249 1250 buf = adc_msb << 8; 1251 buf |= adc_lsb; 1252 error = uiomove(&buf, 2, uio); 1253 if (error) 1254 break; 1255 } 1256 out: 1257 return error; 1258 } 1259 1260 /* Write to the DAC */ 1261 1262 static int 1263 umcpmio_dev_write(dev_t dev, struct uio *uio, int flags) 1264 { 1265 struct umcpmio_softc *sc; 1266 int dunit; 1267 int error = 0; 1268 1269 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1270 if (sc == NULL) 1271 return ENXIO; 1272 1273 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1274 1275 if (dunit == CONTROL_DEV) { 1276 error = EINVAL; 1277 goto out; 1278 } 1279 1280 while (uio->uio_resid && !sc->sc_dying) { 1281 uint8_t buf; 1282 1283 if ((error = uiomove(&buf, 1, uio)) != 0) 1284 break; 1285 1286 if (sc->sc_dying) 1287 break; 1288 1289 error = umcpmio_set_dac_value_one(sc, buf, true); 1290 if (error) 1291 break; 1292 } 1293 out: 1294 return error; 1295 } 1296 1297 /* Close everything up */ 1298 1299 static int 1300 umcpmio_dev_close(dev_t dev, int flags, int fmt, struct lwp *l) 1301 { 1302 struct umcpmio_softc *sc; 1303 int dunit; 1304 int pin; 1305 int error = 0; 1306 1307 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1308 if (sc->sc_dying) 1309 return EIO; 1310 1311 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1312 1313 mutex_enter(&sc->sc_action_mutex); 1314 if (dunit != CONTROL_DEV) { 1315 switch (dunit) { 1316 case GP1_DEV: 1317 pin = 1; 1318 break; 1319 case GP2_DEV: 1320 pin = 2; 1321 break; 1322 case GP3_DEV: 1323 pin = 3; 1324 break; 1325 default: 1326 error = EINVAL; 1327 goto out; 1328 break; 1329 } 1330 /* 1331 * XXX - Ya, this really could be done better. 1332 * Probably should read the sram config and 1333 * maybe the gpio config and save out what the 1334 * pin was set to. 1335 */ 1336 error = umcpmio_gpio_pin_ctlctl(sc, pin, GPIO_PIN_INPUT); 1337 } 1338 out: 1339 sc->sc_dev_open[dunit] = false; 1340 mutex_exit(&sc->sc_action_mutex); 1341 1342 return error; 1343 } 1344 1345 static int 1346 umcpmio_dev_ioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1347 { 1348 struct umcpmio_softc *sc; 1349 struct mcp2221_status_res get_status_res; 1350 struct mcp2221_get_sram_res get_sram_res; 1351 struct mcp2221_get_gpio_cfg_res get_gpio_cfg_res; 1352 struct mcp2221_get_flash_res get_flash_res; 1353 struct mcp2221_status_res *ioctl_get_status; 1354 struct mcp2221_get_sram_res *ioctl_get_sram; 1355 struct mcp2221_get_gpio_cfg_res *ioctl_get_gpio_cfg; 1356 struct umcpmio_ioctl_get_flash *ioctl_get_flash; 1357 struct umcpmio_ioctl_put_flash *ioctl_put_flash; 1358 struct mcp2221_put_flash_req put_flash_req; 1359 struct mcp2221_put_flash_res put_flash_res; 1360 int dunit; 1361 int error = 0; 1362 1363 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1364 if (sc->sc_dying) 1365 return EIO; 1366 1367 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1368 1369 if (dunit != CONTROL_DEV) { 1370 /* 1371 * It actually is fine to call ioctl with a unsupported 1372 * cmd, but be a little noisy if debug is enabled. 1373 */ 1374 DPRINTF(("umcpmio_dev_ioctl: dunit is not the CONTROL device:" 1375 " dunit=%d, cmd=%ld\n", dunit, cmd)); 1376 return EINVAL; 1377 } 1378 1379 mutex_enter(&sc->sc_action_mutex); 1380 1381 switch (cmd) { 1382 /* 1383 * The GET calls use a shadow buffer for each type of 1384 * call. That probably isn't actually needed and the 1385 * memcpy could be avoided. but... it is only ever 64 1386 * bytes, so maybe not a big deal. 1387 */ 1388 case UMCPMIO_GET_STATUS: 1389 ioctl_get_status = (struct mcp2221_status_res *)data; 1390 error = umcpmio_get_status(sc, &get_status_res, false); 1391 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1392 (uint8_t *)&get_status_res, MCP2221_RES_BUFFER_SIZE, 1393 "umcpmio_dev_ioctl: UMCPMIO_GET_STATUS: get_status_res"); 1394 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_STATUS:" 1395 " umcpmio_get_status error=%d\n", error)); 1396 if (error) 1397 break; 1398 memcpy(ioctl_get_status, &get_status_res, 1399 MCP2221_RES_BUFFER_SIZE); 1400 break; 1401 1402 case UMCPMIO_GET_SRAM: 1403 ioctl_get_sram = (struct mcp2221_get_sram_res *)data; 1404 error = umcpmio_get_sram(sc, &get_sram_res, false); 1405 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1406 (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, 1407 "umcpmio_dev_ioctl: UMCPMIO_GET_SRAM: get_sram_res"); 1408 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_SRAM:" 1409 " umcpmio_get_sram error=%d\n", error)); 1410 if (error) 1411 break; 1412 memcpy(ioctl_get_sram, &get_sram_res, 1413 MCP2221_RES_BUFFER_SIZE); 1414 break; 1415 1416 case UMCPMIO_GET_GP_CFG: 1417 ioctl_get_gpio_cfg = (struct mcp2221_get_gpio_cfg_res *)data; 1418 error = umcpmio_get_gpio_cfg(sc, &get_gpio_cfg_res, false); 1419 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1420 (uint8_t *)&get_gpio_cfg_res, MCP2221_RES_BUFFER_SIZE, 1421 "umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG: get_gpio_cfg_res"); 1422 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG:" 1423 " umcpmio_get_gpio_cfg error=%d\n", error)); 1424 if (error) 1425 break; 1426 memcpy(ioctl_get_gpio_cfg, &get_gpio_cfg_res, 1427 MCP2221_RES_BUFFER_SIZE); 1428 break; 1429 1430 case UMCPMIO_GET_FLASH: 1431 ioctl_get_flash = (struct umcpmio_ioctl_get_flash *)data; 1432 error = umcpmio_get_flash(sc, ioctl_get_flash->subcode, 1433 &get_flash_res, false); 1434 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1435 (uint8_t *)&get_flash_res, MCP2221_RES_BUFFER_SIZE, 1436 "umcpmio_dev_ioctl: UMCPMIO_GET_FLASH: get_flash_res"); 1437 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_FLASH:" 1438 " umcpmio_get_flash subcode=%d, error=%d\n", 1439 ioctl_get_flash->subcode, error)); 1440 if (error) 1441 break; 1442 memcpy(&ioctl_get_flash->get_flash_res, &get_flash_res, 1443 MCP2221_RES_BUFFER_SIZE); 1444 break; 1445 1446 case UMCPMIO_PUT_FLASH: 1447 /* 1448 * We only allow the flash parts related to gpio to be changed. 1449 * Bounce any attempt to do something else. Also use a shadow 1450 * buffer for the put, so we get to control just literally 1451 * everything about the write to flash. 1452 */ 1453 ioctl_put_flash = (struct umcpmio_ioctl_put_flash *)data; 1454 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1455 " umcpmio_put_flash subcode=%d\n", 1456 ioctl_put_flash->subcode)); 1457 if (ioctl_put_flash->subcode != MCP2221_FLASH_SUBCODE_GP) { 1458 error = EINVAL; 1459 break; 1460 } 1461 memset(&put_flash_req, 0, MCP2221_REQ_BUFFER_SIZE); 1462 put_flash_req.subcode = ioctl_put_flash->subcode; 1463 put_flash_req.u.gp.gp0_settings = 1464 ioctl_put_flash->put_flash_req.u.gp.gp0_settings; 1465 put_flash_req.u.gp.gp1_settings = 1466 ioctl_put_flash->put_flash_req.u.gp.gp1_settings; 1467 put_flash_req.u.gp.gp2_settings = 1468 ioctl_put_flash->put_flash_req.u.gp.gp2_settings; 1469 put_flash_req.u.gp.gp3_settings = 1470 ioctl_put_flash->put_flash_req.u.gp.gp3_settings; 1471 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1472 (uint8_t *)&ioctl_put_flash->put_flash_req, 1473 MCP2221_REQ_BUFFER_SIZE, 1474 "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1475 " ioctl put_flash_req"); 1476 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1477 (uint8_t *)&put_flash_req, MCP2221_REQ_BUFFER_SIZE, 1478 "umcpmio_dev_ioctl:" 1479 " UMCPMIO_PUT_FLASH: put_flash_req"); 1480 memset(&put_flash_res, 0, MCP2221_RES_BUFFER_SIZE); 1481 error = umcpmio_put_flash(sc, &put_flash_req, 1482 &put_flash_res, false); 1483 if (error) 1484 break; 1485 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1486 (uint8_t *)&put_flash_res, MCP2221_RES_BUFFER_SIZE, 1487 "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1488 " put_flash_res"); 1489 memcpy(&ioctl_put_flash->put_flash_res, &put_flash_res, 1490 MCP2221_RES_BUFFER_SIZE); 1491 break; 1492 default: 1493 error = EINVAL; 1494 } 1495 1496 mutex_exit(&sc->sc_action_mutex); 1497 1498 return error; 1499 } 1500 1501 /* This is for sysctl variables that don't actually change the chip. */ 1502 1503 int 1504 umcpmio_verify_sysctl(SYSCTLFN_ARGS) 1505 { 1506 int error, t; 1507 struct sysctlnode node; 1508 1509 node = *rnode; 1510 t = *(int *)rnode->sysctl_data; 1511 node.sysctl_data = &t; 1512 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1513 if (error || newp == NULL) 1514 return error; 1515 1516 if (t < 0) 1517 return EINVAL; 1518 1519 *(int *)rnode->sysctl_data = t; 1520 1521 return 0; 1522 } 1523 1524 /* 1525 * sysctl validation for stuff that interacts with the chip needs to 1526 * happen in a transaction. The read of the current state and the 1527 * update to new state can't allow for someone to sneak in between the 1528 * two. 1529 * 1530 * We use text for the values of a lot of these variables so you don't 1531 * need the datasheet in front of you. You get to do that with 1532 * umcpmioctl(8). 1533 */ 1534 1535 static struct umcpmio_sysctl_name umcpmio_vref_names[] = { 1536 { 1537 .text = "4.096V", 1538 }, 1539 { 1540 .text = "2.048V", 1541 }, 1542 { 1543 .text = "1.024V", 1544 }, 1545 { 1546 .text = "OFF", 1547 }, 1548 { 1549 .text = "VDD", 1550 } 1551 }; 1552 1553 int 1554 umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS) 1555 { 1556 char buf[UMCPMIO_VREF_NAME]; 1557 char cbuf[UMCPMIO_VREF_NAME]; 1558 struct umcpmio_softc *sc; 1559 struct sysctlnode node; 1560 int error = 0; 1561 int vrm; 1562 size_t i; 1563 struct mcp2221_get_sram_res sram_res; 1564 1565 node = *rnode; 1566 sc = node.sysctl_data; 1567 1568 mutex_enter(&sc->sc_action_mutex); 1569 1570 error = umcpmio_get_sram(sc, &sram_res, false); 1571 if (error) 1572 goto out; 1573 1574 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1575 (uint8_t *)&sram_res, MCP2221_RES_BUFFER_SIZE, 1576 "umcpmio_verify_dac_sysctl SRAM res buffer"); 1577 1578 if (sram_res.dac_reference_voltage & MCP2221_SRAM_DAC_IS_VRM) { 1579 vrm = sram_res.dac_reference_voltage & 1580 MCP2221_SRAM_DAC_VRM_MASK; 1581 switch (vrm) { 1582 case MCP2221_SRAM_DAC_VRM_4096V: 1583 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1584 break; 1585 case MCP2221_SRAM_DAC_VRM_2048V: 1586 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1587 break; 1588 case MCP2221_SRAM_DAC_VRM_1024V: 1589 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1590 break; 1591 case MCP2221_SRAM_DAC_VRM_OFF: 1592 default: 1593 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1594 break; 1595 } 1596 } else { 1597 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1598 } 1599 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1600 node.sysctl_data = buf; 1601 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1602 if (error || newp == NULL) 1603 goto out; 1604 1605 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1606 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1607 UMCPMIO_VREF_NAME) == 0) { 1608 break; 1609 } 1610 } 1611 if (i == __arraycount(umcpmio_vref_names)) { 1612 error = EINVAL; 1613 goto out; 1614 } 1615 1616 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) == 0) { 1617 error = 0; 1618 goto out; 1619 } 1620 1621 DPRINTF(("umcpmio_verify_dac_sysctl: setting DAC vref: %s\n", buf)); 1622 error = umcpmio_set_dac_vref_one(sc, buf, false); 1623 1624 out: 1625 mutex_exit(&sc->sc_action_mutex); 1626 return error; 1627 } 1628 1629 int 1630 umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS) 1631 { 1632 char buf[UMCPMIO_VREF_NAME]; 1633 char cbuf[UMCPMIO_VREF_NAME]; 1634 struct umcpmio_softc *sc; 1635 struct sysctlnode node; 1636 int error = 0; 1637 int vrm; 1638 size_t i; 1639 struct mcp2221_get_sram_res sram_res; 1640 1641 node = *rnode; 1642 sc = node.sysctl_data; 1643 1644 mutex_enter(&sc->sc_action_mutex); 1645 1646 error = umcpmio_get_sram(sc, &sram_res, false); 1647 if (error) 1648 goto out; 1649 1650 if (sram_res.irq_adc_reference_voltage & MCP2221_SRAM_ADC_IS_VRM) { 1651 vrm = sram_res.irq_adc_reference_voltage & 1652 MCP2221_SRAM_ADC_VRM_MASK; 1653 switch (vrm) { 1654 case MCP2221_SRAM_ADC_VRM_4096V: 1655 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1656 break; 1657 case MCP2221_SRAM_ADC_VRM_2048V: 1658 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1659 break; 1660 case MCP2221_SRAM_ADC_VRM_1024V: 1661 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1662 break; 1663 case MCP2221_SRAM_ADC_VRM_OFF: 1664 default: 1665 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1666 break; 1667 } 1668 } else { 1669 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1670 } 1671 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1672 node.sysctl_data = buf; 1673 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1674 if (error || newp == NULL) 1675 goto out; 1676 1677 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1678 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1679 UMCPMIO_VREF_NAME) == 0) { 1680 break; 1681 } 1682 } 1683 if (i == __arraycount(umcpmio_vref_names)) { 1684 error = EINVAL; 1685 goto out; 1686 } 1687 1688 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) == 0) { 1689 error = 0; 1690 goto out; 1691 } 1692 1693 DPRINTF(("umcpmio_verify_adc_sysctl: setting ADC vref: %s\n", buf)); 1694 error = umcpmio_set_adc_vref_one(sc, buf, false); 1695 1696 out: 1697 mutex_exit(&sc->sc_action_mutex); 1698 return error; 1699 } 1700 1701 static struct umcpmio_sysctl_name umcpmio_dc_names[] = { 1702 { 1703 .text = "75%", 1704 }, 1705 { 1706 .text = "50%", 1707 }, 1708 { 1709 .text = "25%", 1710 }, 1711 { 1712 .text = "0%", 1713 } 1714 }; 1715 1716 static int 1717 umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS) 1718 { 1719 char buf[UMCPMIO_VREF_NAME]; 1720 char cbuf[UMCPMIO_VREF_NAME]; 1721 struct umcpmio_softc *sc; 1722 struct sysctlnode node; 1723 int error = 0; 1724 uint8_t duty_cycle; 1725 size_t i; 1726 struct mcp2221_get_sram_res sram_res; 1727 1728 node = *rnode; 1729 sc = node.sysctl_data; 1730 1731 mutex_enter(&sc->sc_action_mutex); 1732 1733 error = umcpmio_get_sram(sc, &sram_res, false); 1734 if (error) 1735 goto out; 1736 1737 duty_cycle = sram_res.clock_divider & MCP2221_SRAM_GPIO_CLOCK_DC_MASK; 1738 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl: current duty cycle:" 1739 " %02x\n", duty_cycle)); 1740 switch (duty_cycle) { 1741 case MCP2221_SRAM_GPIO_CLOCK_DC_75: 1742 strncpy(buf, "75%", UMCPMIO_DC_NAME); 1743 break; 1744 case MCP2221_SRAM_GPIO_CLOCK_DC_50: 1745 strncpy(buf, "50%", UMCPMIO_DC_NAME); 1746 break; 1747 case MCP2221_SRAM_GPIO_CLOCK_DC_25: 1748 strncpy(buf, "25%", UMCPMIO_DC_NAME); 1749 break; 1750 case MCP2221_SRAM_GPIO_CLOCK_DC_0: 1751 default: 1752 strncpy(buf, "0%", UMCPMIO_DC_NAME); 1753 break; 1754 } 1755 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1756 node.sysctl_data = buf; 1757 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1758 if (error || newp == NULL) 1759 goto out; 1760 1761 for (i = 0; i < __arraycount(umcpmio_dc_names); i++) { 1762 if (strncmp(node.sysctl_data, umcpmio_dc_names[i].text, 1763 UMCPMIO_VREF_NAME) == 0) { 1764 break; 1765 } 1766 } 1767 if (i == __arraycount(umcpmio_dc_names)) { 1768 error = EINVAL; 1769 goto out; 1770 } 1771 1772 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) == 0) { 1773 error = 0; 1774 goto out; 1775 } 1776 1777 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl:" 1778 " setting GPIO clock duty cycle: %s\n", buf)); 1779 error = umcpmio_set_gpioclock_dc_one(sc, buf, false); 1780 1781 out: 1782 mutex_exit(&sc->sc_action_mutex); 1783 return error; 1784 } 1785 1786 static struct umcpmio_sysctl_name umcpmio_cd_names[] = { 1787 { 1788 .text = "375kHz", 1789 }, 1790 { 1791 .text = "750kHz", 1792 }, 1793 { 1794 .text = "1.5MHz", 1795 }, 1796 { 1797 .text = "3MHz", 1798 }, 1799 { 1800 .text = "6MHz", 1801 }, 1802 { 1803 .text = "12MHz", 1804 }, 1805 { 1806 .text = "24MHz", 1807 } 1808 }; 1809 1810 static int 1811 umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS) 1812 { 1813 char buf[UMCPMIO_CD_NAME]; 1814 char cbuf[UMCPMIO_CD_NAME]; 1815 struct umcpmio_softc *sc; 1816 struct sysctlnode node; 1817 int error = 0; 1818 uint8_t clock_divider; 1819 size_t i; 1820 struct mcp2221_get_sram_res sram_res; 1821 1822 node = *rnode; 1823 sc = node.sysctl_data; 1824 1825 mutex_enter(&sc->sc_action_mutex); 1826 1827 error = umcpmio_get_sram(sc, &sram_res, false); 1828 if (error) 1829 goto out; 1830 1831 clock_divider = sram_res.clock_divider & 1832 MCP2221_SRAM_GPIO_CLOCK_CD_MASK; 1833 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl: current clock divider:" 1834 " %02x\n", clock_divider)); 1835 switch (clock_divider) { 1836 case MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ: 1837 strncpy(buf, "375kHz", UMCPMIO_CD_NAME); 1838 break; 1839 case MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ: 1840 strncpy(buf, "750kHz", UMCPMIO_CD_NAME); 1841 break; 1842 case MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ: 1843 strncpy(buf, "1.5MHz", UMCPMIO_CD_NAME); 1844 break; 1845 case MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ: 1846 strncpy(buf, "3MHz", UMCPMIO_CD_NAME); 1847 break; 1848 case MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ: 1849 strncpy(buf, "6MHz", UMCPMIO_CD_NAME); 1850 break; 1851 case MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ: 1852 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1853 break; 1854 case MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ: 1855 strncpy(buf, "24MHz", UMCPMIO_CD_NAME); 1856 break; 1857 default: 1858 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1859 break; 1860 } 1861 strncpy(cbuf, buf, UMCPMIO_CD_NAME); 1862 node.sysctl_data = buf; 1863 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1864 if (error || newp == NULL) 1865 goto out; 1866 1867 for (i = 0; i < __arraycount(umcpmio_cd_names); i++) { 1868 if (strncmp(node.sysctl_data, umcpmio_cd_names[i].text, 1869 UMCPMIO_CD_NAME) == 0) { 1870 break; 1871 } 1872 } 1873 if (i == __arraycount(umcpmio_cd_names)) { 1874 error = EINVAL; 1875 goto out; 1876 } 1877 1878 if (strncmp(cbuf, buf, UMCPMIO_CD_NAME) == 0) { 1879 error = 0; 1880 goto out; 1881 } 1882 1883 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl:" 1884 " setting GPIO clock clock divider: %s\n", 1885 buf)); 1886 error = umcpmio_set_gpioclock_cd_one(sc, buf, false); 1887 1888 out: 1889 mutex_exit(&sc->sc_action_mutex); 1890 return error; 1891 } 1892 1893 static int 1894 umcpmio_sysctl_init(struct umcpmio_softc *sc) 1895 { 1896 int error; 1897 const struct sysctlnode *cnode; 1898 int sysctlroot_num, i2c_num, adc_dac_num, adc_num, dac_num, gpio_num; 1899 1900 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1901 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 1902 SYSCTL_DESCR("mcpmio controls"), 1903 NULL, 0, NULL, 0, 1904 CTL_HW, CTL_CREATE, CTL_EOL)) != 0) 1905 return error; 1906 1907 sysctlroot_num = cnode->sysctl_num; 1908 1909 #ifdef UMCPMIO_DEBUG 1910 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1911 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 1912 SYSCTL_DESCR("Debug level"), 1913 umcpmio_verify_sysctl, 0, &umcpmiodebug, 0, 1914 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1915 return error; 1916 1917 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1918 CTLFLAG_READWRITE, CTLTYPE_BOOL, "dump_buffers", 1919 SYSCTL_DESCR("Dump buffer when debugging"), 1920 NULL, 0, &sc->sc_dumpbuffer, 0, 1921 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1922 return error; 1923 #endif 1924 1925 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1926 CTLFLAG_READWRITE, CTLTYPE_INT, "response_wait", 1927 SYSCTL_DESCR("How long to wait in ms for a response" 1928 " for a HID report"), 1929 umcpmio_verify_sysctl, 0, &sc->sc_cv_wait, 0, 1930 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1931 return error; 1932 1933 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1934 CTLFLAG_READWRITE, CTLTYPE_INT, "response_errcnt", 1935 SYSCTL_DESCR("How many errors to allow on a response"), 1936 umcpmio_verify_sysctl, 0, &sc->sc_response_errcnt, 0, 1937 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1938 return error; 1939 1940 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1941 0, CTLTYPE_NODE, "i2c", 1942 SYSCTL_DESCR("I2C controls"), 1943 NULL, 0, NULL, 0, 1944 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1945 return error; 1946 1947 i2c_num = cnode->sysctl_num; 1948 1949 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1950 0, CTLTYPE_NODE, "adcdac", 1951 SYSCTL_DESCR("ADC and DAC controls"), 1952 NULL, 0, NULL, 0, 1953 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1954 return error; 1955 1956 adc_dac_num = cnode->sysctl_num; 1957 1958 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1959 0, CTLTYPE_NODE, "adc", 1960 SYSCTL_DESCR("ADC controls"), 1961 NULL, 0, NULL, 0, 1962 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1963 return error; 1964 1965 adc_num = cnode->sysctl_num; 1966 1967 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1968 0, CTLTYPE_NODE, "dac", 1969 SYSCTL_DESCR("DAC controls"), 1970 NULL, 0, NULL, 0, 1971 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1972 return error; 1973 1974 dac_num = cnode->sysctl_num; 1975 1976 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1977 0, CTLTYPE_NODE, "gpio", 1978 SYSCTL_DESCR("GPIO controls"), 1979 NULL, 0, NULL, 0, 1980 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1981 return error; 1982 1983 gpio_num = cnode->sysctl_num; 1984 1985 /* I2C */ 1986 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1987 CTLFLAG_READWRITE, CTLTYPE_BOOL, "reportreadnostop", 1988 SYSCTL_DESCR("Report that a READ without STOP was attempted" 1989 " by a device"), 1990 NULL, 0, &sc->sc_reportreadnostop, 0, 1991 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 1992 return error; 1993 1994 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1995 CTLFLAG_READWRITE, CTLTYPE_INT, "busy_delay", 1996 SYSCTL_DESCR("How long to wait in ms when the I2C engine is busy"), 1997 umcpmio_verify_sysctl, 0, &sc->sc_busy_delay, 0, 1998 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 1999 return error; 2000 2001 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2002 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_read", 2003 SYSCTL_DESCR("How many times to retry a busy I2C read"), 2004 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_read, 0, 2005 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2006 return error; 2007 2008 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2009 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_write", 2010 SYSCTL_DESCR("How many times to retry a busy I2C write"), 2011 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_write, 0, 2012 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2013 return error; 2014 2015 /* GPIO */ 2016 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2017 CTLFLAG_READWRITE, CTLTYPE_INT, "irq_poll", 2018 SYSCTL_DESCR("How often to poll for a IRQ change"), 2019 umcpmio_verify_sysctl, 0, &sc->sc_irq_poll, 0, 2020 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2021 return error; 2022 2023 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2024 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_duty_cycles", 2025 SYSCTL_DESCR("Valid duty cycles for GPIO clock on" 2026 " GP1 ALT3 duty cycle"), 2027 0, 0, __UNCONST(umcpmio_valid_dcs), sizeof(umcpmio_valid_dcs) + 1, 2028 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2029 return error; 2030 2031 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2032 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_duty_cycle", 2033 SYSCTL_DESCR("GPIO clock on GP1 ALT3 duty cycle"), 2034 umcpmio_verify_gpioclock_dc_sysctl, 0, (void *)sc, UMCPMIO_DC_NAME, 2035 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2036 return error; 2037 2038 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2039 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_dividers", 2040 SYSCTL_DESCR("Valid clock dividers for GPIO clock on GP1" 2041 " with ALT3"), 2042 0, 0, __UNCONST(umcpmio_valid_cds), sizeof(umcpmio_valid_cds) + 1, 2043 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2044 return error; 2045 2046 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2047 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_divider", 2048 SYSCTL_DESCR("GPIO clock on GP1 ALT3 clock divider"), 2049 umcpmio_verify_gpioclock_cd_sysctl, 0, (void *)sc, UMCPMIO_CD_NAME, 2050 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2051 return error; 2052 2053 /* ADC and DAC */ 2054 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2055 CTLFLAG_READONLY, CTLTYPE_STRING, "vrefs", 2056 SYSCTL_DESCR("Valid vref values for ADC and DAC"), 2057 0, 0, 2058 __UNCONST(umcpmio_valid_vrefs), sizeof(umcpmio_valid_vrefs) + 1, 2059 CTL_HW, sysctlroot_num, adc_dac_num, CTL_CREATE, CTL_EOL)) != 0) 2060 return error; 2061 2062 /* ADC */ 2063 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2064 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 2065 SYSCTL_DESCR("ADC voltage reference"), 2066 umcpmio_verify_adc_sysctl, 0, (void *)sc, UMCPMIO_VREF_NAME, 2067 CTL_HW, sysctlroot_num, adc_num, CTL_CREATE, CTL_EOL)) != 0) 2068 return error; 2069 2070 /* DAC */ 2071 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2072 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 2073 SYSCTL_DESCR("DAC voltage reference"), 2074 umcpmio_verify_dac_sysctl, 0, (void *)sc, UMCPMIO_VREF_NAME, 2075 CTL_HW, sysctlroot_num, dac_num, CTL_CREATE, CTL_EOL)) != 0) 2076 return error; 2077 2078 return 0; 2079 } 2080 2081 static int 2082 umcpmio_match(device_t parent, cfdata_t match, void *aux) 2083 { 2084 struct uhidev_attach_arg *uha = aux; 2085 2086 return umcpmio_lookup(uha->uiaa->uiaa_vendor, uha->uiaa->uiaa_product) 2087 != NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 2088 } 2089 2090 /* 2091 * This driver could be extended to support the MCP-2210 which is MCP's 2092 * USB to SPI / gpio chip. It also appears to be a something like the 2093 * PIC16F1455 used in the MCP2221 / MCP2221A. It is likely that a lot 2094 * of this could use tables to drive behavior. 2095 */ 2096 2097 static void 2098 umcpmio_attach(device_t parent, device_t self, void *aux) 2099 { 2100 struct umcpmio_softc *sc = device_private(self); 2101 struct uhidev_attach_arg *uha = aux; 2102 struct gpiobus_attach_args gba; 2103 struct mcp2221_status_res status_res; 2104 int err; 2105 2106 sc->sc_dev = self; 2107 sc->sc_hdev = uha->parent; 2108 sc->sc_udev = uha->uiaa->uiaa_device; 2109 2110 sc->sc_umcpmiolog = NULL; 2111 sc->sc_dumpbuffer = false; 2112 2113 sc->sc_reportreadnostop = true; 2114 sc->sc_cv_wait = 2500; 2115 sc->sc_response_errcnt = 5; 2116 sc->sc_busy_delay = 1; 2117 sc->sc_retry_busy_read = 50; 2118 sc->sc_retry_busy_write = 50; 2119 sc->sc_irq_poll = 10; 2120 sc->sc_dev_open[CONTROL_DEV] = false; 2121 sc->sc_dev_open[GP1_DEV] = false; 2122 sc->sc_dev_open[GP2_DEV] = false; 2123 sc->sc_dev_open[GP3_DEV] = false; 2124 2125 aprint_normal("\n"); 2126 2127 if ((err = umcpmio_sysctl_init(sc)) != 0) { 2128 aprint_error_dev(self, "Can't setup sysctl tree (%d)\n", err); 2129 return; 2130 } 2131 2132 mutex_init(&sc->sc_action_mutex, MUTEX_DEFAULT, IPL_NONE); 2133 cv_init(&sc->sc_res_cv, "mcpres"); 2134 mutex_init(&sc->sc_res_mutex, MUTEX_DEFAULT, IPL_NONE); 2135 sc->sc_res_buffer = NULL; 2136 sc->sc_res_ready = false; 2137 2138 err = uhidev_open(sc->sc_hdev, &umcpmio_uhidev_intr, sc); 2139 if (err) { 2140 aprint_error_dev(sc->sc_dev, "umcpmio_attach: " 2141 " uhidev_open: err=%d\n", err); 2142 return; 2143 } 2144 2145 /* 2146 * It is not clear that this should be needed, but it was noted 2147 * that the device would sometimes not be ready if this delay 2148 * was not present. In fact, the attempts to set stuff a 2149 * little later would sometimes fail. 2150 */ 2151 2152 delay(1000); 2153 2154 err = umcpmio_get_status(sc, &status_res, true); 2155 if (err) { 2156 aprint_error_dev(sc->sc_dev, "umcpmio_attach: " 2157 " umcpmio_get_status: err=%d\n", err); 2158 return; 2159 } 2160 2161 aprint_normal_dev(sc->sc_dev, 2162 "Hardware revision: %d.%d, Firmware revision: %d.%d\n", 2163 status_res.mcp2221_hardware_rev_major, 2164 status_res.mcp2221_hardware_rev_minor, 2165 status_res.mcp2221_firmware_rev_major, 2166 status_res.mcp2221_firmware_rev_minor); 2167 2168 /* 2169 * The datasheet suggests that it is possble for this 2170 * to fail if the I2C port is currently being used. 2171 * However... since you just plugged in the chip, the 2172 * I2C port should not really be in use at that moment. 2173 * In any case, try hard to set this and don't make it 2174 * fatal if it did not get set. 2175 */ 2176 int i2cspeed; 2177 for (i2cspeed = 0; i2cspeed < 3; i2cspeed++) { 2178 err = umcpmio_set_i2c_speed_one(sc, I2C_SPEED_SM, true); 2179 if (err) { 2180 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2181 " set I2C speed: err=%d\n", 2182 err); 2183 delay(300); 2184 } 2185 break; 2186 } 2187 2188 struct mcp2221_get_sram_res get_sram_res; 2189 err = umcpmio_get_sram(sc, &get_sram_res, true); 2190 if (err) { 2191 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2192 " get sram error: err=%d\n", 2193 err); 2194 return; 2195 } 2196 2197 umcpmio_dump_buffer(sc->sc_dumpbuffer, 2198 (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, 2199 "umcpmio_attach get sram buffer copy"); 2200 2201 /* 2202 * There are only 4 pins right now, just unroll 2203 * any loops 2204 */ 2205 2206 sc->sc_gpio_pins[0].pin_num = 0; 2207 sc->sc_gpio_pins[0].pin_caps = GPIO_PIN_INPUT; 2208 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_OUTPUT; 2209 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_ALT0; 2210 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_ALT3; 2211 sc->sc_gpio_pins[0].pin_flags = 2212 umcpmio_sram_gpio_to_flags(get_sram_res.gp0_settings); 2213 sc->sc_gpio_pins[0].pin_intrcaps = 0; 2214 snprintf(sc->sc_gpio_pins[0].pin_defname, 4, "GP0"); 2215 2216 sc->sc_gpio_pins[1].pin_num = 1; 2217 sc->sc_gpio_pins[1].pin_caps = GPIO_PIN_INPUT; 2218 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_OUTPUT; 2219 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT0; 2220 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT1; 2221 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT2; 2222 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT3; 2223 sc->sc_gpio_pins[1].pin_flags = 2224 umcpmio_sram_gpio_to_flags(get_sram_res.gp1_settings); 2225 /* XXX - lets not advertise this right now... */ 2226 #if 0 2227 sc->sc_gpio_pins[1].pin_intrcaps = GPIO_INTR_POS_EDGE; 2228 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_NEG_EDGE; 2229 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_DOUBLE_EDGE; 2230 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_MPSAFE; 2231 #endif 2232 sc->sc_gpio_pins[1].pin_intrcaps = 0; 2233 snprintf(sc->sc_gpio_pins[1].pin_defname, 4, "GP1"); 2234 2235 sc->sc_gpio_pins[2].pin_num = 2; 2236 sc->sc_gpio_pins[2].pin_caps = GPIO_PIN_INPUT; 2237 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_OUTPUT; 2238 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT0; 2239 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT1; 2240 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT3; 2241 sc->sc_gpio_pins[2].pin_flags = 2242 umcpmio_sram_gpio_to_flags(get_sram_res.gp2_settings); 2243 sc->sc_gpio_pins[2].pin_intrcaps = 0; 2244 snprintf(sc->sc_gpio_pins[2].pin_defname, 4, "GP2"); 2245 2246 sc->sc_gpio_pins[3].pin_num = 3; 2247 sc->sc_gpio_pins[3].pin_caps = GPIO_PIN_INPUT; 2248 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_OUTPUT; 2249 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT0; 2250 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT1; 2251 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT3; 2252 sc->sc_gpio_pins[3].pin_flags = 2253 umcpmio_sram_gpio_to_flags(get_sram_res.gp3_settings); 2254 sc->sc_gpio_pins[3].pin_intrcaps = 0; 2255 snprintf(sc->sc_gpio_pins[3].pin_defname, 4, "GP3"); 2256 2257 sc->sc_gpio_gc.gp_cookie = sc; 2258 sc->sc_gpio_gc.gp_pin_read = umcpmio_gpio_pin_read; 2259 sc->sc_gpio_gc.gp_pin_write = umcpmio_gpio_pin_write; 2260 sc->sc_gpio_gc.gp_pin_ctl = umcpmio_gpio_pin_ctl; 2261 2262 sc->sc_gpio_gc.gp_intr_establish = umcpmio_gpio_intr_establish; 2263 sc->sc_gpio_gc.gp_intr_disestablish = umcpmio_gpio_intr_disestablish; 2264 sc->sc_gpio_gc.gp_intr_str = umcpmio_gpio_intrstr; 2265 2266 gba.gba_gc = &sc->sc_gpio_gc; 2267 gba.gba_pins = sc->sc_gpio_pins; 2268 gba.gba_npins = MCP2221_NPINS; 2269 2270 sc->sc_gpio_dev = config_found(self, &gba, gpiobus_print, 2271 CFARGS(.iattr = "gpiobus")); 2272 2273 iic_tag_init(&sc->sc_i2c_tag); 2274 sc->sc_i2c_tag.ic_cookie = sc; 2275 sc->sc_i2c_tag.ic_acquire_bus = umcpmio_acquire_bus; 2276 sc->sc_i2c_tag.ic_release_bus = umcpmio_release_bus; 2277 sc->sc_i2c_tag.ic_exec = umcpmio_i2c_exec; 2278 2279 sc->sc_i2c_dev = iicbus_attach(self, &sc->sc_i2c_tag); 2280 } 2281 2282 static int 2283 umcpmio_detach(device_t self, int flags) 2284 { 2285 struct umcpmio_softc *sc = device_private(self); 2286 int err; 2287 2288 DPRINTF(("umcpmio_detach: sc=%p flags=%d\n", sc, flags)); 2289 2290 mutex_enter(&sc->sc_action_mutex); 2291 sc->sc_dying = 1; 2292 2293 err = config_detach_children(self, flags); 2294 if (err) 2295 return err; 2296 2297 uhidev_close(sc->sc_hdev); 2298 2299 mutex_destroy(&sc->sc_res_mutex); 2300 cv_destroy(&sc->sc_res_cv); 2301 2302 sysctl_teardown(&sc->sc_umcpmiolog); 2303 2304 mutex_exit(&sc->sc_action_mutex); 2305 mutex_destroy(&sc->sc_action_mutex); 2306 2307 return 0; 2308 } 2309 2310 static int 2311 umcpmio_activate(device_t self, enum devact act) 2312 { 2313 struct umcpmio_softc *sc = device_private(self); 2314 2315 DPRINTFN(5, ("umcpmio_activate: %d\n", act)); 2316 2317 switch (act) { 2318 case DVACT_DEACTIVATE: 2319 sc->sc_dying = 1; 2320 return 0; 2321 default: 2322 return EOPNOTSUPP; 2323 } 2324 } 2325
Indexes created Sun Sep 21 20:09:37 GMT 2025