1 /* $NetBSD: uninorth.c,v 1.23 2022/01/21 19:12:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: uninorth.c,v 1.23 2022/01/21 19:12:28 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/ofw/openfirm.h> 38 #include <dev/ofw/ofw_pci.h> 39 #include <powerpc/oea/cpufeat.h> 40 41 #include <machine/autoconf.h> 42 #include <machine/pio.h> 43 44 struct uninorth_softc { 45 device_t sc_dev; 46 struct genppc_pci_chipset sc_pc; 47 struct powerpc_bus_space sc_iot; 48 struct powerpc_bus_space sc_memt; 49 }; 50 51 static void uninorth_attach(device_t, device_t, void *); 52 static int uninorth_match(device_t, cfdata_t, void *); 53 54 static pcireg_t uninorth_conf_read(void *, pcitag_t, int); 55 static void uninorth_conf_write(void *, pcitag_t, int, pcireg_t); 56 static pcireg_t uninorth_conf_read_v3(void *, pcitag_t, int); 57 static void uninorth_conf_write_v3(void *, pcitag_t, int, pcireg_t); 58 59 CFATTACH_DECL_NEW(uninorth, sizeof(struct uninorth_softc), 60 uninorth_match, uninorth_attach, NULL, NULL); 61 62 static int 63 uninorth_match(device_t parent, cfdata_t cf, void *aux) 64 { 65 struct confargs *ca = aux; 66 char compat[32]; 67 68 if (strcmp(ca->ca_name, "pci") != 0) 69 return 0; 70 71 memset(compat, 0, sizeof(compat)); 72 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 73 if (strcmp(compat, "uni-north") != 0 && 74 strcmp(compat, "u3-agp") != 0 && 75 strcmp(compat, "u4-pcie") != 0) 76 return 0; 77 78 return 1; 79 } 80 81 static void 82 uninorth_attach(device_t parent, device_t self, void *aux) 83 { 84 struct uninorth_softc *sc = device_private(self); 85 pci_chipset_tag_t pc = &sc->sc_pc; 86 struct confargs *ca = aux; 87 struct pcibus_attach_args pba; 88 int len, child, node = ca->ca_node; 89 uint32_t reg[2], busrange[2]; 90 char compat[32]; 91 int ver; 92 struct ranges { 93 uint32_t pci_hi, pci_mid, pci_lo; 94 uint32_t host; 95 uint32_t size_hi, size_lo; 96 } ranges[6], *rp = ranges; 97 98 printf("\n"); 99 sc->sc_dev = self; 100 101 memset(compat, 0, sizeof(compat)); 102 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 103 if (strcmp(compat, "u3-agp") == 0) 104 ver = 3; 105 else if (strcmp(compat, "u4-pcie") == 0) 106 ver = 4; 107 else 108 ver = 0; 109 110 /* UniNorth address */ 111 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 112 return; 113 114 /* PCI bus number */ 115 if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8) 116 return; 117 118 memset(&sc->sc_iot, 0, sizeof(sc->sc_iot)); 119 120 /* find i/o tag */ 121 len = OF_getprop(node, "ranges", ranges, sizeof(ranges)); 122 if (len == -1) 123 return; 124 while (len >= sizeof(ranges[0])) { 125 if ((rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 126 OFW_PCI_PHYS_HI_SPACE_IO) { 127 sc->sc_iot.pbs_base = rp->host; 128 sc->sc_iot.pbs_limit = rp->host + rp->size_lo; 129 break; 130 } 131 len -= sizeof(ranges[0]); 132 rp++; 133 } 134 135 /* XXX enable gmac ethernet */ 136 for (child = OF_child(node); child; child = OF_peer(child)) { 137 volatile int *gmac_gbclock_en = (void *)0xf8000020; 138 139 memset(compat, 0, sizeof(compat)); 140 OF_getprop(child, "compatible", compat, sizeof(compat)); 141 if (strcmp(compat, "gmac") == 0) 142 *gmac_gbclock_en |= 0x02; 143 } 144 145 sc->sc_iot.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE; 146 sc->sc_iot.pbs_offset = 0; 147 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, &sc->sc_iot, 148 "uninorth io-space") != 0) 149 panic("Can't init uninorth io tag"); 150 151 memset(&sc->sc_memt, 0, sizeof(sc->sc_memt)); 152 sc->sc_memt.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE; 153 sc->sc_memt.pbs_base = 0x00000000; 154 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, &sc->sc_memt, 155 "uninorth mem-space") != 0) 156 panic("Can't init uninorth mem tag"); 157 158 macppc_pci_get_chipset_tag(pc); 159 pc->pc_node = node; 160 pc->pc_bus = busrange[0]; 161 pc->pc_iot = &sc->sc_iot; 162 pc->pc_memt = &sc->sc_memt; 163 164 if (ver < 3) { 165 pc->pc_addr = oea_mapiodev(reg[0] + 0x800000, 4); 166 pc->pc_data = oea_mapiodev(reg[0] + 0xc00000, 8); 167 pc->pc_conf_read = uninorth_conf_read; 168 pc->pc_conf_write = uninorth_conf_write; 169 } else { 170 pc->pc_addr = oea_mapiodev(reg[1] + 0x800000, 4); 171 pc->pc_data = oea_mapiodev(reg[1] + 0xc00000, 8); 172 pc->pc_conf_read = uninorth_conf_read_v3; 173 pc->pc_conf_write = uninorth_conf_write_v3; 174 } 175 176 memset(&pba, 0, sizeof(pba)); 177 pba.pba_memt = pc->pc_memt; 178 pba.pba_iot = pc->pc_iot; 179 pba.pba_dmat = &pci_bus_dma_tag; 180 pba.pba_dmat64 = NULL; 181 pba.pba_bus = pc->pc_bus; 182 pba.pba_bridgetag = NULL; 183 pba.pba_pc = pc; 184 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 185 186 config_found(self, &pba, pcibusprint, 187 CFARGS(.devhandle = device_handle(self))); 188 } 189 190 static pcireg_t 191 uninorth_conf_read(void *cookie, pcitag_t tag, int reg) 192 { 193 pci_chipset_tag_t pc = cookie; 194 int32_t *daddr = pc->pc_data; 195 pcireg_t data; 196 int bus, dev, func, s; 197 uint32_t x; 198 199 if ((unsigned int)reg >= PCI_CONF_SIZE) 200 return (pcireg_t) -1; 201 202 /* UniNorth seems to have a 64bit data port */ 203 if (reg & 0x04) 204 daddr++; 205 206 pci_decompose_tag(pc, tag, &bus, &dev, &func); 207 208 /* 209 * bandit's minimum device number of the first bus is 11. 210 * So we behave as if there is no device when dev < 11. 211 */ 212 if (func > 7) 213 panic("pci_conf_read: func > 7"); 214 215 if (bus == pc->pc_bus) { 216 if (dev < 11) 217 return 0xffffffff; 218 x = (1 << dev) | (func << 8) | reg; 219 } else 220 x = tag | reg | 1; 221 222 s = splhigh(); 223 224 out32rb(pc->pc_addr, x); 225 in32rb(pc->pc_addr); 226 data = 0xffffffff; 227 if (!badaddr(daddr, 4)) 228 data = in32rb(daddr); 229 out32rb(pc->pc_addr, 0); 230 in32rb(pc->pc_addr); 231 splx(s); 232 233 return data; 234 } 235 236 static void 237 uninorth_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data) 238 { 239 pci_chipset_tag_t pc = cookie; 240 int32_t *daddr = pc->pc_data; 241 int bus, dev, func, s; 242 uint32_t x; 243 244 if ((unsigned int)reg >= PCI_CONF_SIZE) 245 return; 246 247 /* UniNorth seems to have a 64bit data port */ 248 if (reg & 0x04) 249 daddr++; 250 251 pci_decompose_tag(pc, tag, &bus, &dev, &func); 252 253 if (func > 7) 254 panic("pci_conf_write: func > 7"); 255 256 if (bus == pc->pc_bus) { 257 if (dev < 11) 258 panic("pci_conf_write: dev < 11"); 259 x = (1 << dev) | (func << 8) | reg; 260 } else 261 x = tag | reg | 1; 262 263 s = splhigh(); 264 265 out32rb(pc->pc_addr, x); 266 in32rb(pc->pc_addr); 267 out32rb(daddr, data); 268 out32rb(pc->pc_addr, 0); 269 in32rb(pc->pc_addr); 270 271 splx(s); 272 } 273 274 static pcireg_t 275 uninorth_conf_read_v3(void *cookie, pcitag_t tag, int reg) 276 { 277 pci_chipset_tag_t pc = cookie; 278 int32_t *daddr = pc->pc_data; 279 pcireg_t data; 280 int bus, dev, func, s; 281 uint32_t x; 282 283 if ((unsigned int)reg >= PCI_CONF_SIZE) 284 return (pcireg_t) -1; 285 286 /* UniNorth seems to have a 64bit data port */ 287 if (reg & 0x04) 288 daddr++; 289 290 pci_decompose_tag(pc, tag, &bus, &dev, &func); 291 292 if (bus == 0) { 293 if (dev < 11) return 0xffffffff; 294 x = (1 << dev) | (func << 8) | reg; 295 } else 296 x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1; 297 /* Set extended register bits */ 298 x |= (reg >> 8) << 28; 299 300 s = splhigh(); 301 302 out32rb(pc->pc_addr, x); 303 in32rb(pc->pc_addr); 304 data = 0xffffffff; 305 if (!badaddr(daddr, 4)) { 306 data = in32rb(daddr); 307 } 308 out32rb(pc->pc_addr, 0); 309 in32rb(pc->pc_addr); 310 splx(s); 311 312 return data; 313 } 314 315 static void 316 uninorth_conf_write_v3(void *cookie, pcitag_t tag, int reg, pcireg_t data) 317 { 318 pci_chipset_tag_t pc = cookie; 319 int32_t *daddr = pc->pc_data; 320 int bus, dev, func, s; 321 uint32_t x; 322 323 if ((unsigned int)reg >= PCI_CONF_SIZE) 324 return; 325 326 /* UniNorth seems to have a 64bit data port */ 327 if (reg & 0x04) 328 daddr++; 329 330 pci_decompose_tag(pc, tag, &bus, &dev, &func); 331 332 if (bus == 0) { 333 if (dev < 11) return; 334 x = (1 << dev) | (func << 8) | reg; 335 } else 336 x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1; 337 /* Set extended register bits */ 338 x |= (reg >> 8) << 28; 339 340 s = splhigh(); 341 342 out32rb(pc->pc_addr, x); 343 in32rb(pc->pc_addr); 344 out32rb(daddr, data); 345 out32rb(pc->pc_addr, 0); 346 in32rb(pc->pc_addr); 347 348 splx(s); 349 } 350
Indexes created Mon Sep 22 21:09:42 GMT 2025