1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.76 2025/06/27 21:36:22 andvar Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.76 2025/06/27 21:36:22 andvar Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 70 /* XXXX some i386 on-board chips act weird when memory-mapped */ 71 #ifndef __i386__ 72 #define AHC_ALLOW_MEMIO 73 #endif 74 75 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 76 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 77 78 #include <dev/ic/aic7xxx_osm.h> 79 #include <dev/ic/aic7xxx_inline.h> 80 81 #include <dev/ic/smc93cx6var.h> 82 83 84 static inline uint64_t 85 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 99 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 100 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 101 #define ID_9005_SISL_ID 0x0005900500000000ull 102 #define ID_AIC7850 0x5078900400000000ull 103 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 104 #define ID_AIC7855 0x5578900400000000ull 105 #define ID_AIC7859 0x3860900400000000ull 106 #define ID_AHA_2930CU 0x3860900438699004ull 107 #define ID_AIC7860 0x6078900400000000ull 108 #define ID_AIC7860C 0x6078900478609004ull 109 #define ID_AHA_1480A 0x6075900400000000ull 110 #define ID_AHA_2940AU_0 0x6178900400000000ull 111 #define ID_AHA_2940AU_1 0x6178900478619004ull 112 #define ID_AHA_2940AU_CN 0x2178900478219004ull 113 #define ID_AHA_2930C_VAR 0x6038900438689004ull 114 115 #define ID_AIC7870 0x7078900400000000ull 116 #define ID_AHA_2940 0x7178900400000000ull 117 #define ID_AHA_3940 0x7278900400000000ull 118 #define ID_AHA_398X 0x7378900400000000ull 119 #define ID_AHA_2944 0x7478900400000000ull 120 #define ID_AHA_3944 0x7578900400000000ull 121 #define ID_AHA_4944 0x7678900400000000ull 122 123 #define ID_AIC7880 0x8078900400000000ull 124 #define ID_AIC7880_B 0x8078900478809004ull 125 #define ID_AHA_2940U 0x8178900400000000ull 126 #define ID_AHA_3940U 0x8278900400000000ull 127 #define ID_AHA_2944U 0x8478900400000000ull 128 #define ID_AHA_3944U 0x8578900400000000ull 129 #define ID_AHA_398XU 0x8378900400000000ull 130 #define ID_AHA_4944U 0x8678900400000000ull 131 #define ID_AHA_2940UB 0x8178900478819004ull 132 #define ID_AHA_2930U 0x8878900478889004ull 133 #define ID_AHA_2940U_PRO 0x8778900478879004ull 134 #define ID_AHA_2940U_CN 0x0078900478009004ull 135 136 #define ID_AIC7895 0x7895900478959004ull 137 #define ID_AIC7895_ARO 0x7890900478939004ull 138 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 139 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 140 #define ID_AHA_3940AU 0x7895900478929004ull 141 #define ID_AHA_3944AU 0x7895900478949004ull 142 143 #define ID_AIC7890 0x001F9005000F9005ull 144 #define ID_AIC7890_ARO 0x00139005000F9005ull 145 #define ID_AAA_131U2 0x0013900500039005ull 146 #define ID_AHA_2930U2 0x0011900501819005ull 147 #define ID_AHA_2940U2B 0x00109005A1009005ull 148 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 149 #define ID_AHA_2940U2 0x00109005A1809005ull 150 #define ID_AHA_2950U2B 0x00109005E1009005ull 151 152 #define ID_AIC7892 0x008F9005FFFF9005ull 153 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 154 #define ID_AHA_2915LP 0x0082900502109005ull 155 #define ID_AHA_29160 0x00809005E2A09005ull 156 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 157 #define ID_AHA_29160N 0x0080900562A09005ull 158 #define ID_AHA_29160C 0x0080900562209005ull 159 #define ID_AHA_29160B 0x00809005E2209005ull 160 #define ID_AHA_19160B 0x0081900562A19005ull 161 162 #define ID_AIC7896 0x005F9005FFFF9005ull 163 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 164 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 165 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 166 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 167 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 168 169 #define ID_AIC7899 0x00CF9005FFFF9005ull 170 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 171 #define ID_AHA_3960D 0x00C09005F6209005ull 172 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 173 174 #define ID_AIC7810 0x1078900400000000ull 175 #define ID_AIC7815 0x7815900400000000ull 176 177 #define DEVID_9005_TYPE(id) ((id) & 0xF) 178 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 179 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 180 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 181 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 182 183 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 184 #define DEVID_9005_MAXRATE_U160 0x0 185 #define DEVID_9005_MAXRATE_ULTRA2 0x1 186 #define DEVID_9005_MAXRATE_ULTRA 0x2 187 #define DEVID_9005_MAXRATE_FAST 0x3 188 189 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 190 191 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 192 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 193 194 #define SUBID_9005_TYPE(id) ((id) & 0xF) 195 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 196 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 197 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 198 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 199 200 #define SUBID_9005_TYPE_KNOWN(id) \ 201 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 202 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 203 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 204 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 205 206 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 207 #define SUBID_9005_MAXRATE_ULTRA2 0x0 208 #define SUBID_9005_MAXRATE_ULTRA 0x1 209 #define SUBID_9005_MAXRATE_U160 0x2 210 #define SUBID_9005_MAXRATE_RESERVED 0x3 211 212 #define SUBID_9005_SEEPTYPE(id) \ 213 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 214 ? ((id) & 0xC0) >> 6 \ 215 : ((id) & 0x300) >> 8) 216 #define SUBID_9005_SEEPTYPE_NONE 0x0 217 #define SUBID_9005_SEEPTYPE_1K 0x1 218 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 219 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 220 #define SUBID_9005_AUTOTERM(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? (((id) & 0x400) >> 10) == 0 \ 223 : (((id) & 0x40) >> 6) == 0) 224 225 #define SUBID_9005_NUMCHAN(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? ((id) & 0x300) >> 8 \ 228 : ((id) & 0xC00) >> 10) 229 230 #define SUBID_9005_LEGACYCONN(id) \ 231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 232 ? 0 \ 233 : ((id) & 0x80) >> 7) 234 235 #define SUBID_9005_MFUNCENB(id) \ 236 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 237 ? ((id) & 0x800) >> 11 \ 238 : ((id) & 0x1000) >> 12) 239 /* 240 * Informational only. Should use chip register to be 241 * certain, but may be used in identification strings. 242 */ 243 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 244 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 245 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 246 247 static ahc_device_setup_t ahc_aic785X_setup; 248 static ahc_device_setup_t ahc_aic7860_setup; 249 static ahc_device_setup_t ahc_apa1480_setup; 250 static ahc_device_setup_t ahc_aic7870_setup; 251 static ahc_device_setup_t ahc_aha394X_setup; 252 static ahc_device_setup_t ahc_aha494X_setup; 253 static ahc_device_setup_t ahc_aha398X_setup; 254 static ahc_device_setup_t ahc_aic7880_setup; 255 static ahc_device_setup_t ahc_aha2940Pro_setup; 256 static ahc_device_setup_t ahc_aha394XU_setup; 257 static ahc_device_setup_t ahc_aha398XU_setup; 258 static ahc_device_setup_t ahc_aic7890_setup; 259 static ahc_device_setup_t ahc_aic7892_setup; 260 static ahc_device_setup_t ahc_aic7895_setup; 261 static ahc_device_setup_t ahc_aic7896_setup; 262 static ahc_device_setup_t ahc_aic7899_setup; 263 static ahc_device_setup_t ahc_aha29160C_setup; 264 static ahc_device_setup_t ahc_raid_setup; 265 static ahc_device_setup_t ahc_aha394XX_setup; 266 static ahc_device_setup_t ahc_aha494XX_setup; 267 static ahc_device_setup_t ahc_aha398XX_setup; 268 269 static const struct ahc_pci_identity ahc_pci_ident_table[] = 270 { 271 /* aic7850 based controllers */ 272 { 273 ID_AHA_2902_04_10_15_20_30C, 274 ID_ALL_MASK, 275 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 276 ahc_aic785X_setup 277 }, 278 /* aic7860 based controllers */ 279 { 280 ID_AHA_2930CU, 281 ID_ALL_MASK, 282 "Adaptec 2930CU SCSI adapter", 283 ahc_aic7860_setup 284 }, 285 { 286 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 1480A Ultra SCSI adapter", 289 ahc_apa1480_setup 290 }, 291 { 292 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940A Ultra SCSI adapter", 295 ahc_aic7860_setup 296 }, 297 { 298 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2940A/CN Ultra SCSI adapter", 301 ahc_aic7860_setup 302 }, 303 { 304 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 2930C Ultra SCSI adapter (VAR)", 307 ahc_aic7860_setup 308 }, 309 /* aic7870 based controllers */ 310 { 311 ID_AHA_2940, 312 ID_ALL_MASK, 313 "Adaptec 2940 SCSI adapter", 314 ahc_aic7870_setup 315 }, 316 { 317 ID_AHA_3940, 318 ID_ALL_MASK, 319 "Adaptec 3940 SCSI adapter", 320 ahc_aha394X_setup 321 }, 322 { 323 ID_AHA_398X, 324 ID_ALL_MASK, 325 "Adaptec 398X SCSI RAID adapter", 326 ahc_aha398X_setup 327 }, 328 { 329 ID_AHA_2944, 330 ID_ALL_MASK, 331 "Adaptec 2944 SCSI adapter", 332 ahc_aic7870_setup 333 }, 334 { 335 ID_AHA_3944, 336 ID_ALL_MASK, 337 "Adaptec 3944 SCSI adapter", 338 ahc_aha394X_setup 339 }, 340 { 341 ID_AHA_4944, 342 ID_ALL_MASK, 343 "Adaptec 4944 SCSI adapter", 344 ahc_aha494X_setup 345 }, 346 /* aic7880 based controllers */ 347 { 348 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 2940 Ultra SCSI adapter", 351 ahc_aic7880_setup 352 }, 353 { 354 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 3940 Ultra SCSI adapter", 357 ahc_aha394XU_setup 358 }, 359 { 360 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 2944 Ultra SCSI adapter", 363 ahc_aic7880_setup 364 }, 365 { 366 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec 3944 Ultra SCSI adapter", 369 ahc_aha394XU_setup 370 }, 371 { 372 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec 398X Ultra SCSI RAID adapter", 375 ahc_aha398XU_setup 376 }, 377 { 378 /* 379 * XXX Don't know the slot numbers 380 * so we can't identify channels 381 */ 382 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 383 ID_DEV_VENDOR_MASK, 384 "Adaptec 4944 Ultra SCSI adapter", 385 ahc_aic7880_setup 386 }, 387 { 388 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 389 ID_DEV_VENDOR_MASK, 390 "Adaptec 2930 Ultra SCSI adapter", 391 ahc_aic7880_setup 392 }, 393 { 394 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 395 ID_DEV_VENDOR_MASK, 396 "Adaptec 2940 Pro Ultra SCSI adapter", 397 ahc_aha2940Pro_setup 398 }, 399 { 400 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 401 ID_DEV_VENDOR_MASK, 402 "Adaptec 2940/CN Ultra SCSI adapter", 403 ahc_aic7880_setup 404 }, 405 /* Ignore all SISL (AAC on MB) based controllers. */ 406 { 407 ID_9005_SISL_ID, 408 ID_9005_SISL_MASK, 409 NULL, 410 NULL 411 }, 412 /* aic7890 based controllers */ 413 { 414 ID_AHA_2930U2, 415 ID_ALL_MASK, 416 "Adaptec 2930 Ultra2 SCSI adapter", 417 ahc_aic7890_setup 418 }, 419 { 420 ID_AHA_2940U2B, 421 ID_ALL_MASK, 422 "Adaptec 2940B Ultra2 SCSI adapter", 423 ahc_aic7890_setup 424 }, 425 { 426 ID_AHA_2940U2_OEM, 427 ID_ALL_MASK, 428 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 429 ahc_aic7890_setup 430 }, 431 { 432 ID_AHA_2940U2, 433 ID_ALL_MASK, 434 "Adaptec 2940 Ultra2 SCSI adapter", 435 ahc_aic7890_setup 436 }, 437 { 438 ID_AHA_2950U2B, 439 ID_ALL_MASK, 440 "Adaptec 2950 Ultra2 SCSI adapter", 441 ahc_aic7890_setup 442 }, 443 { 444 ID_AIC7890_ARO, 445 ID_ALL_MASK, 446 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 447 ahc_aic7890_setup 448 }, 449 { 450 ID_AAA_131U2, 451 ID_ALL_MASK, 452 "Adaptec AAA-131 Ultra2 RAID adapter", 453 ahc_aic7890_setup 454 }, 455 /* aic7892 based controllers */ 456 { 457 ID_AHA_29160, 458 ID_ALL_MASK, 459 "Adaptec 29160 Ultra160 SCSI adapter", 460 ahc_aic7892_setup 461 }, 462 { 463 ID_AHA_29160_CPQ, 464 ID_ALL_MASK, 465 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 466 ahc_aic7892_setup 467 }, 468 { 469 ID_AHA_29160N, 470 ID_ALL_MASK, 471 "Adaptec 29160N Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AHA_29160C, 476 ID_ALL_MASK, 477 "Adaptec 29160C Ultra160 SCSI adapter", 478 ahc_aha29160C_setup 479 }, 480 { 481 ID_AHA_29160B, 482 ID_ALL_MASK, 483 "Adaptec 29160B Ultra160 SCSI adapter", 484 ahc_aic7892_setup 485 }, 486 { 487 ID_AHA_19160B, 488 ID_ALL_MASK, 489 "Adaptec 19160B Ultra160 SCSI adapter", 490 ahc_aic7892_setup 491 }, 492 { 493 ID_AIC7892_ARO, 494 ID_ALL_MASK, 495 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 496 ahc_aic7892_setup 497 }, 498 { 499 ID_AHA_2915LP, 500 ID_ALL_MASK, 501 "Adaptec 2915LP Ultra160 SCSI adapter", 502 ahc_aic7892_setup 503 }, 504 /* aic7895 based controllers */ 505 { 506 ID_AHA_2940U_DUAL, 507 ID_ALL_MASK, 508 "Adaptec 2940/DUAL Ultra SCSI adapter", 509 ahc_aic7895_setup 510 }, 511 { 512 ID_AHA_3940AU, 513 ID_ALL_MASK, 514 "Adaptec 3940A Ultra SCSI adapter", 515 ahc_aic7895_setup 516 }, 517 { 518 ID_AHA_3944AU, 519 ID_ALL_MASK, 520 "Adaptec 3944A Ultra SCSI adapter", 521 ahc_aic7895_setup 522 }, 523 { 524 ID_AIC7895_ARO, 525 ID_AIC7895_ARO_MASK, 526 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 527 ahc_aic7895_setup 528 }, 529 /* aic7896/97 based controllers */ 530 { 531 ID_AHA_3950U2B_0, 532 ID_ALL_MASK, 533 "Adaptec 3950B Ultra2 SCSI adapter", 534 ahc_aic7896_setup 535 }, 536 { 537 ID_AHA_3950U2B_1, 538 ID_ALL_MASK, 539 "Adaptec 3950B Ultra2 SCSI adapter", 540 ahc_aic7896_setup 541 }, 542 { 543 ID_AHA_3950U2D_0, 544 ID_ALL_MASK, 545 "Adaptec 3950D Ultra2 SCSI adapter", 546 ahc_aic7896_setup 547 }, 548 { 549 ID_AHA_3950U2D_1, 550 ID_ALL_MASK, 551 "Adaptec 3950D Ultra2 SCSI adapter", 552 ahc_aic7896_setup 553 }, 554 { 555 ID_AIC7896_ARO, 556 ID_ALL_MASK, 557 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 558 ahc_aic7896_setup 559 }, 560 /* aic7899 based controllers */ 561 { 562 ID_AHA_3960D, 563 ID_ALL_MASK, 564 "Adaptec 3960D Ultra160 SCSI adapter", 565 ahc_aic7899_setup 566 }, 567 { 568 ID_AHA_3960D_CPQ, 569 ID_ALL_MASK, 570 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 571 ahc_aic7899_setup 572 }, 573 { 574 ID_AIC7899_ARO, 575 ID_ALL_MASK, 576 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 577 ahc_aic7899_setup 578 }, 579 /* Generic chip probes for devices we don't know 'exactly' */ 580 { 581 ID_AIC7850 & ID_DEV_VENDOR_MASK, 582 ID_DEV_VENDOR_MASK, 583 "Adaptec aic7850 SCSI adapter", 584 ahc_aic785X_setup 585 }, 586 { 587 ID_AIC7855 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 "Adaptec aic7855 SCSI adapter", 590 ahc_aic785X_setup 591 }, 592 { 593 ID_AIC7859 & ID_DEV_VENDOR_MASK, 594 ID_DEV_VENDOR_MASK, 595 "Adaptec aic7859 SCSI adapter", 596 ahc_aic7860_setup 597 }, 598 { 599 ID_AIC7860 & ID_DEV_VENDOR_MASK, 600 ID_DEV_VENDOR_MASK, 601 "Adaptec aic7860 Ultra SCSI adapter", 602 ahc_aic7860_setup 603 }, 604 { 605 ID_AIC7870 & ID_DEV_VENDOR_MASK, 606 ID_DEV_VENDOR_MASK, 607 "Adaptec aic7870 SCSI adapter", 608 ahc_aic7870_setup 609 }, 610 { 611 ID_AIC7880 & ID_DEV_VENDOR_MASK, 612 ID_DEV_VENDOR_MASK, 613 "Adaptec aic7880 Ultra SCSI adapter", 614 ahc_aic7880_setup 615 }, 616 { 617 ID_AIC7890 & ID_9005_GENERIC_MASK, 618 ID_9005_GENERIC_MASK, 619 "Adaptec aic7890/91 Ultra2 SCSI adapter", 620 ahc_aic7890_setup 621 }, 622 { 623 ID_AIC7892 & ID_9005_GENERIC_MASK, 624 ID_9005_GENERIC_MASK, 625 "Adaptec aic7892 Ultra160 SCSI adapter", 626 ahc_aic7892_setup 627 }, 628 { 629 ID_AIC7895 & ID_DEV_VENDOR_MASK, 630 ID_DEV_VENDOR_MASK, 631 "Adaptec aic7895 Ultra SCSI adapter", 632 ahc_aic7895_setup 633 }, 634 { 635 ID_AIC7896 & ID_9005_GENERIC_MASK, 636 ID_9005_GENERIC_MASK, 637 "Adaptec aic7896/97 Ultra2 SCSI adapter", 638 ahc_aic7896_setup 639 }, 640 { 641 ID_AIC7899 & ID_9005_GENERIC_MASK, 642 ID_9005_GENERIC_MASK, 643 "Adaptec aic7899 Ultra160 SCSI adapter", 644 ahc_aic7899_setup 645 }, 646 { 647 ID_AIC7810 & ID_DEV_VENDOR_MASK, 648 ID_DEV_VENDOR_MASK, 649 "Adaptec aic7810 RAID memory controller", 650 ahc_raid_setup 651 }, 652 { 653 ID_AIC7815 & ID_DEV_VENDOR_MASK, 654 ID_DEV_VENDOR_MASK, 655 "Adaptec aic7815 RAID memory controller", 656 ahc_raid_setup 657 } 658 }; 659 660 static const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 661 662 #define AHC_394X_SLOT_CHANNEL_A 4 663 #define AHC_394X_SLOT_CHANNEL_B 5 664 665 #define AHC_398X_SLOT_CHANNEL_A 4 666 #define AHC_398X_SLOT_CHANNEL_B 8 667 #define AHC_398X_SLOT_CHANNEL_C 12 668 669 #define AHC_494X_SLOT_CHANNEL_A 4 670 #define AHC_494X_SLOT_CHANNEL_B 5 671 #define AHC_494X_SLOT_CHANNEL_C 6 672 #define AHC_494X_SLOT_CHANNEL_D 7 673 674 #define DEVCONFIG 0x40 675 #define PCIERRGENDIS 0x80000000ul 676 #define SCBSIZE32 0x00010000ul /* aic789X only */ 677 #define REXTVALID 0x00001000ul /* ultra cards only */ 678 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 679 #define RAMPSM 0x00000200ul /* aic7870+ only */ 680 #define VOLSENSE 0x00000100ul 681 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 682 #define SCBRAMSEL 0x00000080ul 683 #define MRDCEN 0x00000040ul 684 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 685 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 686 #define BERREN 0x00000008ul 687 #define DACEN 0x00000004ul 688 #define STPWLEVEL 0x00000002ul 689 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 690 691 #define CSIZE_LATTIME 0x0c 692 #define CACHESIZE 0x0000003ful /* only 5 bits */ 693 #define LATTIME 0x0000ff00ul 694 695 /* PCI STATUS definitions */ 696 #define DPE 0x80 697 #define SSE 0x40 698 #define RMA 0x20 699 #define RTA 0x10 700 #define STA 0x08 701 #define DPR 0x01 702 703 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 704 uint16_t subvendor, uint16_t subdevice); 705 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 706 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 707 int pcheck, int fast, int large); 708 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 709 710 static void ahc_pci_intr(struct ahc_softc *); 711 712 static const struct ahc_pci_identity * 713 ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) 714 { 715 u_int64_t full_id; 716 const struct ahc_pci_identity *entry; 717 u_int i; 718 719 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 720 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 721 722 /* 723 * If the second function is not hooked up, ignore it. 724 * Unfortunately, not all MB vendors implement the 725 * subdevice ID as per the Adaptec spec, so do our best 726 * to sanity check it prior to accepting the subdevice 727 * ID as valid. 728 */ 729 if (func > 0 730 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 731 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 732 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 733 return (NULL); 734 735 for (i = 0; i < ahc_num_pci_devs; i++) { 736 entry = &ahc_pci_ident_table[i]; 737 if (entry->full_id == (full_id & entry->id_mask)) 738 return (entry); 739 } 740 return (NULL); 741 } 742 743 static int 744 ahc_pci_probe(device_t parent, cfdata_t match, void *aux) 745 { 746 struct pci_attach_args *pa = aux; 747 const struct ahc_pci_identity *entry; 748 pcireg_t subid; 749 750 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 751 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 752 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 753 } 754 755 static void 756 ahc_pci_attach(device_t parent, device_t self, void *aux) 757 { 758 struct pci_attach_args *pa = aux; 759 const struct ahc_pci_identity *entry; 760 struct ahc_softc *ahc = device_private(self); 761 pcireg_t command; 762 u_int our_id = 0; 763 u_int sxfrctl1; 764 u_int scsiseq; 765 u_int sblkctl; 766 uint8_t dscommand0; 767 uint32_t devconfig; 768 int error; 769 pcireg_t subid; 770 int ioh_valid; 771 bus_space_tag_t st, iot; 772 bus_space_handle_t sh, ioh; 773 #ifdef AHC_ALLOW_MEMIO 774 int memh_valid; 775 bus_space_tag_t memt; 776 bus_space_handle_t memh; 777 pcireg_t memtype; 778 #endif 779 pci_intr_handle_t ih; 780 const char *intrstr; 781 struct ahc_pci_busdata *bd; 782 bool override_ultra; 783 char intrbuf[PCI_INTRSTR_LEN]; 784 785 ahc->sc_dev = self; 786 ahc_set_name(ahc, device_xname(ahc->sc_dev)); 787 ahc->parent_dmat = pa->pa_dmat; 788 789 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 790 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 791 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 792 if (entry == NULL) 793 return; 794 aprint_naive("\n"); 795 aprint_normal(": %s\n", entry->name); 796 797 /* Keep information about the PCI bus */ 798 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_WAITOK | M_ZERO); 799 bd->pc = pa->pa_pc; 800 bd->tag = pa->pa_tag; 801 bd->func = pa->pa_function; 802 bd->dev = pa->pa_device; 803 bd->class = pa->pa_class; 804 805 ahc->bd = bd; 806 807 ahc->description = entry->name; 808 809 error = entry->setup(ahc); 810 if (error != 0) 811 return; 812 813 ioh_valid = 0; 814 815 #ifdef AHC_ALLOW_MEMIO 816 memh_valid = 0; 817 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 818 switch (memtype) { 819 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 820 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 821 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 822 memtype, 0, &memt, &memh, NULL, NULL) == 0); 823 break; 824 default: 825 memh_valid = 0; 826 } 827 #endif 828 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 829 PCI_MAPREG_TYPE_IO, 0, &iot, 830 &ioh, NULL, NULL) == 0); 831 832 #if 0 833 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", 834 ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot, 835 (u_long)ioh); 836 #endif 837 838 #ifdef AHC_ALLOW_MEMIO 839 if (memh_valid) { 840 st = memt; 841 sh = memh; 842 } else 843 #endif 844 if (ioh_valid) { 845 st = iot; 846 sh = ioh; 847 } else { 848 aprint_error(": unable to map registers\n"); 849 return; 850 } 851 ahc->tag = st; 852 ahc->bsh = sh; 853 854 ahc->chip |= AHC_PCI; 855 /* 856 * Before we continue probing the card, ensure that 857 * its interrupts are *disabled*. We don't want 858 * a misstep to hang the machine in an interrupt 859 * storm. 860 */ 861 ahc_intr_enable(ahc, FALSE); 862 863 /* 864 * XXX somehow reading this once fails on some sparc64 systems. 865 * This may be a problem in the sparc64 PCI code. Doing it 866 * twice works around it. 867 */ 868 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 869 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 870 871 /* 872 * If we need to support high memory, enable dual 873 * address cycles. This bit must be set to enable 874 * high address bit generation even if we are on a 875 * 64bit bus (PCI64BIT set in devconfig). 876 */ 877 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 878 879 if (1/*bootverbose*/) 880 aprint_normal("%s: Enabling 39Bit Addressing\n", 881 ahc_name(ahc)); 882 devconfig |= DACEN; 883 } 884 885 /* Ensure that pci error generation, a test feature, is disabled. */ 886 devconfig |= PCIERRGENDIS; 887 888 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 889 890 /* Ensure busmastering is enabled */ 891 command |= PCI_COMMAND_MASTER_ENABLE; 892 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 893 894 /* 895 * Disable PCI parity error reporting. Users typically 896 * do this to work around broken PCI chipsets that get 897 * the parity timing wrong and thus generate lots of spurious 898 * errors. 899 */ 900 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 901 command &= ~PCI_COMMAND_PARITY_ENABLE; 902 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 903 904 /* On all PCI adapters, we allow SCB paging */ 905 ahc->flags |= AHC_PAGESCBS; 906 error = ahc_softc_init(ahc); 907 if (error != 0) 908 goto error_out; 909 910 ahc->bus_intr = ahc_pci_intr; 911 912 /* Remember how the card was setup in case there is no SEEPROM */ 913 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 914 ahc_pause(ahc); 915 if ((ahc->features & AHC_ULTRA2) != 0) 916 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 917 else 918 our_id = ahc_inb(ahc, SCSIID) & OID; 919 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 920 scsiseq = ahc_inb(ahc, SCSISEQ); 921 } else { 922 sxfrctl1 = STPWEN; 923 our_id = 7; 924 scsiseq = 0; 925 } 926 927 error = ahc_reset(ahc); 928 if (error != 0) 929 goto error_out; 930 931 if ((ahc->features & AHC_DT) != 0) { 932 u_int sfunct; 933 934 /* Perform ALT-Mode Setup */ 935 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 936 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 937 ahc_outb(ahc, OPTIONMODE, 938 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 939 ahc_outb(ahc, SFUNCT, sfunct); 940 941 /* Normal mode setup */ 942 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 943 |TARGCRCENDEN); 944 } 945 946 if (pci_intr_map(pa, &ih)) { 947 aprint_error("%s: couldn't map interrupt\n", ahc_name(ahc)); 948 ahc_free(ahc); 949 return; 950 } 951 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 952 ahc->ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_BIO, ahc_intr, 953 ahc, device_xname(self)); 954 if (ahc->ih == NULL) { 955 aprint_error_dev(ahc->sc_dev, 956 "couldn't establish interrupt\n"); 957 if (intrstr != NULL) 958 aprint_error(" at %s", intrstr); 959 aprint_error("\n"); 960 ahc_free(ahc); 961 return; 962 } 963 if (intrstr != NULL) 964 aprint_normal("%s: interrupting at %s\n", ahc_name(ahc), 965 intrstr); 966 967 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 968 dscommand0 |= MPARCKEN|CACHETHEN; 969 if ((ahc->features & AHC_ULTRA2) != 0) { 970 971 /* 972 * DPARCKEN doesn't work correctly on 973 * some MBs so don't use it. 974 */ 975 dscommand0 &= ~DPARCKEN; 976 } 977 978 /* 979 * Handle chips that must have cache line 980 * streaming (dis/en)abled. 981 */ 982 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 983 dscommand0 |= CACHETHEN; 984 985 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 986 dscommand0 &= ~CACHETHEN; 987 988 ahc_outb(ahc, DSCOMMAND0, dscommand0); 989 990 ahc->pci_cachesize = 991 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 992 ahc->pci_cachesize *= 4; 993 994 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 995 && ahc->pci_cachesize == 4) { 996 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 997 ahc->pci_cachesize = 0; 998 } 999 1000 /* 1001 * We cannot perform ULTRA speeds without the presence 1002 * of the external precision resistor. 1003 * Allow override for the SGI O2 though, which has two onboard ahc 1004 * that fail here but are perfectly capable of ultra speeds. 1005 */ 1006 override_ultra = FALSE; 1007 prop_dictionary_get_bool(device_properties(self), 1008 "aic7xxx-override-ultra", &override_ultra); 1009 1010 if (((ahc->features & AHC_ULTRA) != 0) && (!override_ultra)) { 1011 uint32_t dvconfig; 1012 1013 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1014 if ((dvconfig & REXTVALID) == 0) 1015 ahc->features &= ~AHC_ULTRA; 1016 } 1017 1018 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1019 M_DEVBUF, M_WAITOK | M_ZERO); 1020 1021 /* See if we have a SEEPROM and perform auto-term */ 1022 ahc_check_extport(ahc, &sxfrctl1); 1023 1024 /* 1025 * Take the LED out of diagnostic mode 1026 */ 1027 sblkctl = ahc_inb(ahc, SBLKCTL); 1028 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1029 1030 if ((ahc->features & AHC_ULTRA2) != 0) { 1031 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1032 } else { 1033 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1034 } 1035 1036 if (ahc->flags & AHC_USEDEFAULTS) { 1037 /* 1038 * PCI Adapter default setup 1039 * Should only be used if the adapter does not have 1040 * a SEEPROM. 1041 */ 1042 /* See if someone else set us up already */ 1043 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1044 && scsiseq != 0) { 1045 prop_bool_t usetd; 1046 1047 printf("%s: Using left over BIOS settings\n", 1048 ahc_name(ahc)); 1049 ahc->flags &= ~AHC_USEDEFAULTS; 1050 /* 1051 * Ignore target device settings and use default 1052 * if BIOS initializes chip's SRAM with some 1053 * conservative settings (async, no tagged 1054 * queuing etc.) and machine dependent device 1055 * property is set. 1056 */ 1057 usetd = prop_dictionary_get( 1058 device_properties(ahc->sc_dev), 1059 "aic7xxx-use-target-defaults"); 1060 if (usetd != NULL) { 1061 KASSERT(prop_object_type(usetd) == 1062 PROP_TYPE_BOOL); 1063 if (prop_bool_true(usetd)) 1064 ahc->flags |= AHC_USETARGETDEFAULTS; 1065 } 1066 ahc->flags |= AHC_BIOS_ENABLED; 1067 } else { 1068 /* 1069 * Assume only one connector and always turn 1070 * on termination. 1071 */ 1072 our_id = 0x07; 1073 sxfrctl1 = STPWEN; 1074 } 1075 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1076 1077 ahc->our_id = our_id; 1078 } 1079 1080 /* 1081 * Take a look to see if we have external SRAM. 1082 * We currently do not attempt to use SRAM that is 1083 * shared among multiple controllers. 1084 */ 1085 ahc_probe_ext_scbram(ahc); 1086 1087 /* 1088 * Record our termination setting for the 1089 * generic initialization routine. 1090 */ 1091 if ((sxfrctl1 & STPWEN) != 0) 1092 ahc->flags |= AHC_TERM_ENB_A; 1093 1094 if (ahc_init(ahc)) 1095 goto error_out; 1096 1097 ahc_attach(ahc); 1098 1099 return; 1100 1101 error_out: 1102 ahc_free(ahc); 1103 return; 1104 } 1105 1106 CFATTACH_DECL_NEW(ahc_pci, sizeof(struct ahc_softc), 1107 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 1108 1109 static int 1110 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1111 uint16_t subdevice, uint16_t subvendor) 1112 { 1113 int result; 1114 1115 /* Default to invalid. */ 1116 result = 0; 1117 if (vendor == 0x9005 1118 && subvendor == 0x9005 1119 && subdevice != device 1120 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1121 1122 switch (SUBID_9005_TYPE(subdevice)) { 1123 case SUBID_9005_TYPE_MB: 1124 break; 1125 case SUBID_9005_TYPE_CARD: 1126 case SUBID_9005_TYPE_LCCARD: 1127 /* 1128 * Currently only trust Adaptec cards to 1129 * get the sub device info correct. 1130 */ 1131 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1132 result = 1; 1133 break; 1134 case SUBID_9005_TYPE_RAID: 1135 break; 1136 default: 1137 break; 1138 } 1139 } 1140 return (result); 1141 } 1142 1143 1144 /* 1145 * Test for the presence of external sram in an 1146 * "unshared" configuration. 1147 */ 1148 static int 1149 ahc_ext_scbram_present(struct ahc_softc *ahc) 1150 { 1151 u_int chip; 1152 int ramps; 1153 int single_user; 1154 uint32_t devconfig; 1155 1156 chip = ahc->chip & AHC_CHIPID_MASK; 1157 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1158 single_user = (devconfig & MPORTMODE) != 0; 1159 1160 if ((ahc->features & AHC_ULTRA2) != 0) 1161 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1162 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1163 /* 1164 * External SCBRAM arbitration is flakey 1165 * on these chips. Unfortunately this means 1166 * we don't use the extra SCB ram space on the 1167 * 3940AUW. 1168 */ 1169 ramps = 0; 1170 else if (chip >= AHC_AIC7870) 1171 ramps = (devconfig & RAMPSM) != 0; 1172 else 1173 ramps = 0; 1174 1175 if (ramps && single_user) 1176 return (1); 1177 return (0); 1178 } 1179 1180 /* 1181 * Enable external scbram. 1182 */ 1183 static void 1184 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1185 int fast, int large) 1186 { 1187 uint32_t devconfig; 1188 1189 if (ahc->features & AHC_MULTI_FUNC) { 1190 /* 1191 * Set the SCB Base addr (highest address bit) 1192 * depending on which channel we are. 1193 */ 1194 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1195 } 1196 1197 ahc->flags &= ~AHC_LSCBS_ENABLED; 1198 if (large) 1199 ahc->flags |= AHC_LSCBS_ENABLED; 1200 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1201 if ((ahc->features & AHC_ULTRA2) != 0) { 1202 u_int dscommand0; 1203 1204 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1205 if (enable) 1206 dscommand0 &= ~INTSCBRAMSEL; 1207 else 1208 dscommand0 |= INTSCBRAMSEL; 1209 if (large) 1210 dscommand0 &= ~USCBSIZE32; 1211 else 1212 dscommand0 |= USCBSIZE32; 1213 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1214 } else { 1215 if (fast) 1216 devconfig &= ~EXTSCBTIME; 1217 else 1218 devconfig |= EXTSCBTIME; 1219 if (enable) 1220 devconfig &= ~SCBRAMSEL; 1221 else 1222 devconfig |= SCBRAMSEL; 1223 if (large) 1224 devconfig &= ~SCBSIZE32; 1225 else 1226 devconfig |= SCBSIZE32; 1227 } 1228 if (pcheck) 1229 devconfig |= EXTSCBPEN; 1230 else 1231 devconfig &= ~EXTSCBPEN; 1232 1233 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1234 } 1235 1236 /* 1237 * Take a look to see if we have external SRAM. 1238 * We currently do not attempt to use SRAM that is 1239 * shared among multiple controllers. 1240 */ 1241 static void 1242 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1243 { 1244 int num_scbs; 1245 int test_num_scbs; 1246 int enable; 1247 int pcheck; 1248 int fast; 1249 int large; 1250 1251 enable = FALSE; 1252 pcheck = FALSE; 1253 fast = FALSE; 1254 large = FALSE; 1255 num_scbs = 0; 1256 1257 if (ahc_ext_scbram_present(ahc) == 0) 1258 goto done; 1259 1260 /* 1261 * Probe for the best parameters to use. 1262 */ 1263 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1264 num_scbs = ahc_probe_scbs(ahc); 1265 if (num_scbs == 0) { 1266 /* The SRAM wasn't really present. */ 1267 goto done; 1268 } 1269 enable = TRUE; 1270 1271 /* 1272 * Clear any outstanding parity error 1273 * and ensure that parity error reporting 1274 * is enabled. 1275 */ 1276 ahc_outb(ahc, SEQCTL, 0); 1277 ahc_outb(ahc, CLRINT, CLRPARERR); 1278 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1279 1280 /* Now see if we can do parity */ 1281 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1282 num_scbs = ahc_probe_scbs(ahc); 1283 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1284 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1285 pcheck = TRUE; 1286 1287 /* Clear any resulting parity error */ 1288 ahc_outb(ahc, CLRINT, CLRPARERR); 1289 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1290 1291 /* Now see if we can do fast timing */ 1292 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1293 test_num_scbs = ahc_probe_scbs(ahc); 1294 if (test_num_scbs == num_scbs 1295 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1296 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1297 fast = TRUE; 1298 1299 /* 1300 * See if we can use large SCBs and still maintain 1301 * the same overall count of SCBs. 1302 */ 1303 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1304 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1305 test_num_scbs = ahc_probe_scbs(ahc); 1306 if (test_num_scbs >= num_scbs) { 1307 large = TRUE; 1308 num_scbs = test_num_scbs; 1309 if (num_scbs >= 64) { 1310 /* 1311 * We have enough space to move the 1312 * "busy targets table" into SCB space 1313 * and make it qualify all the way to the 1314 * lun level. 1315 */ 1316 ahc->flags |= AHC_SCB_BTT; 1317 } 1318 } 1319 } 1320 done: 1321 /* 1322 * Disable parity error reporting until we 1323 * can load instruction ram. 1324 */ 1325 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1326 /* Clear any latched parity error */ 1327 ahc_outb(ahc, CLRINT, CLRPARERR); 1328 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1329 if (1/*bootverbose*/ && enable) { 1330 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1331 ahc_name(ahc), fast ? "fast" : "slow", 1332 pcheck ? ", parity checking enabled" : "", 1333 large ? 64 : 32); 1334 } 1335 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1336 } 1337 1338 #if 0 1339 /* 1340 * Perform some simple tests that should catch situations where 1341 * our registers are invalidly mapped. 1342 */ 1343 static int 1344 ahc_pci_test_register_access(struct ahc_softc *ahc) 1345 { 1346 int error; 1347 u_int status1; 1348 uint32_t cmd; 1349 uint8_t hcntrl; 1350 1351 error = EIO; 1352 1353 /* 1354 * Enable PCI error interrupt status, but suppress NMIs 1355 * generated by SERR raised due to target aborts. 1356 */ 1357 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1358 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1359 cmd & ~PCIM_CMD_SERRESPEN); 1360 1361 /* 1362 * First a simple test to see if any 1363 * registers can be read. Reading 1364 * HCNTRL has no side effects and has 1365 * at least one bit that is guaranteed to 1366 * be zero so it is a good register to 1367 * use for this test. 1368 */ 1369 hcntrl = ahc_inb(ahc, HCNTRL); 1370 if (hcntrl == 0xFF) 1371 goto fail; 1372 1373 /* 1374 * Next create a situation where write combining 1375 * or read prefetching could be initiated by the 1376 * CPU or host bridge. Our device does not support 1377 * either, so look for data corruption and/or flagged 1378 * PCI errors. 1379 */ 1380 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1381 while (ahc_is_paused(ahc) == 0) 1382 ; 1383 ahc_outb(ahc, SEQCTL, PERRORDIS); 1384 ahc_outb(ahc, SCBPTR, 0); 1385 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1386 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1387 goto fail; 1388 1389 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1390 PCI_COMMAND_STATUS_REG + 1); 1391 if ((status1 & STA) != 0) 1392 goto fail; 1393 1394 error = 0; 1395 1396 fail: 1397 /* Silently clear any latched errors. */ 1398 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1399 PCI_COMMAND_STATUS_REG + 1); 1400 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1401 status1, /*bytes*/1); 1402 ahc_outb(ahc, CLRINT, CLRPARERR); 1403 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1404 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1405 return (error); 1406 } 1407 #endif 1408 1409 static void 1410 ahc_pci_intr(struct ahc_softc *ahc) 1411 { 1412 u_int error; 1413 u_int status1; 1414 1415 error = ahc_inb(ahc, ERROR); 1416 if ((error & PCIERRSTAT) == 0) 1417 return; 1418 1419 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1420 PCI_COMMAND_STATUS_REG); 1421 1422 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1423 ahc_name(ahc), 1424 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1425 1426 if (status1 & DPE) { 1427 printf("%s: Data Parity Error Detected during address " 1428 "or write data phase\n", ahc_name(ahc)); 1429 } 1430 if (status1 & SSE) { 1431 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1432 } 1433 if (status1 & RMA) { 1434 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1435 } 1436 if (status1 & RTA) { 1437 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1438 } 1439 if (status1 & STA) { 1440 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1441 } 1442 if (status1 & DPR) { 1443 printf("%s: Data Parity Error has been reported via PERR#\n", 1444 ahc_name(ahc)); 1445 } 1446 1447 /* Clear latched errors. */ 1448 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, 1449 status1); 1450 1451 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1452 printf("%s: Latched PCIERR interrupt with " 1453 "no status bits set\n", ahc_name(ahc)); 1454 } else { 1455 ahc_outb(ahc, CLRINT, CLRPARERR); 1456 } 1457 1458 ahc_unpause(ahc); 1459 } 1460 1461 static int 1462 ahc_aic785X_setup(struct ahc_softc *ahc) 1463 { 1464 uint8_t rev; 1465 1466 ahc->channel = 'A'; 1467 ahc->chip = AHC_AIC7850; 1468 ahc->features = AHC_AIC7850_FE; 1469 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1470 rev = PCI_REVISION(ahc->bd->class); 1471 if (rev >= 1) 1472 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1473 return (0); 1474 } 1475 1476 static int 1477 ahc_aic7860_setup(struct ahc_softc *ahc) 1478 { 1479 uint8_t rev; 1480 1481 ahc->channel = 'A'; 1482 ahc->chip = AHC_AIC7860; 1483 ahc->features = AHC_AIC7860_FE; 1484 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1485 rev = PCI_REVISION(ahc->bd->class); 1486 if (rev >= 1) 1487 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1488 return (0); 1489 } 1490 1491 static int 1492 ahc_apa1480_setup(struct ahc_softc *ahc) 1493 { 1494 int error; 1495 1496 error = ahc_aic7860_setup(ahc); 1497 if (error != 0) 1498 return (error); 1499 ahc->features |= AHC_REMOVABLE; 1500 return (0); 1501 } 1502 1503 static int 1504 ahc_aic7870_setup(struct ahc_softc *ahc) 1505 { 1506 1507 ahc->channel = 'A'; 1508 ahc->chip = AHC_AIC7870; 1509 ahc->features = AHC_AIC7870_FE; 1510 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1511 return (0); 1512 } 1513 1514 static int 1515 ahc_aha394X_setup(struct ahc_softc *ahc) 1516 { 1517 int error; 1518 1519 error = ahc_aic7870_setup(ahc); 1520 if (error == 0) 1521 error = ahc_aha394XX_setup(ahc); 1522 return (error); 1523 } 1524 1525 static int 1526 ahc_aha398X_setup(struct ahc_softc *ahc) 1527 { 1528 int error; 1529 1530 error = ahc_aic7870_setup(ahc); 1531 if (error == 0) 1532 error = ahc_aha398XX_setup(ahc); 1533 return (error); 1534 } 1535 1536 static int 1537 ahc_aha494X_setup(struct ahc_softc *ahc) 1538 { 1539 int error; 1540 1541 error = ahc_aic7870_setup(ahc); 1542 if (error == 0) 1543 error = ahc_aha494XX_setup(ahc); 1544 return (error); 1545 } 1546 1547 static int 1548 ahc_aic7880_setup(struct ahc_softc *ahc) 1549 { 1550 uint8_t rev; 1551 1552 ahc->channel = 'A'; 1553 ahc->chip = AHC_AIC7880; 1554 ahc->features = AHC_AIC7880_FE; 1555 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1556 rev = PCI_REVISION(ahc->bd->class); 1557 if (rev >= 1) { 1558 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1559 } else { 1560 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1561 } 1562 return (0); 1563 } 1564 1565 static int 1566 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1567 { 1568 1569 ahc->flags |= AHC_INT50_SPEEDFLEX; 1570 return (ahc_aic7880_setup(ahc)); 1571 } 1572 1573 static int 1574 ahc_aha394XU_setup(struct ahc_softc *ahc) 1575 { 1576 int error; 1577 1578 error = ahc_aic7880_setup(ahc); 1579 if (error == 0) 1580 error = ahc_aha394XX_setup(ahc); 1581 return (error); 1582 } 1583 1584 static int 1585 ahc_aha398XU_setup(struct ahc_softc *ahc) 1586 { 1587 int error; 1588 1589 error = ahc_aic7880_setup(ahc); 1590 if (error == 0) 1591 error = ahc_aha398XX_setup(ahc); 1592 return (error); 1593 } 1594 1595 static int 1596 ahc_aic7890_setup(struct ahc_softc *ahc) 1597 { 1598 uint8_t rev; 1599 1600 ahc->channel = 'A'; 1601 ahc->chip = AHC_AIC7890; 1602 ahc->features = AHC_AIC7890_FE; 1603 ahc->flags |= AHC_NEWEEPROM_FMT; 1604 rev = PCI_REVISION(ahc->bd->class); 1605 if (rev == 0) 1606 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1607 return (0); 1608 } 1609 1610 static int 1611 ahc_aic7892_setup(struct ahc_softc *ahc) 1612 { 1613 1614 ahc->channel = 'A'; 1615 ahc->chip = AHC_AIC7892; 1616 ahc->features = AHC_AIC7892_FE; 1617 ahc->flags |= AHC_NEWEEPROM_FMT; 1618 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1619 return (0); 1620 } 1621 1622 static int 1623 ahc_aic7895_setup(struct ahc_softc *ahc) 1624 { 1625 uint8_t rev; 1626 1627 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1628 /* 1629 * The 'C' revision of the aic7895 has a few additional features. 1630 */ 1631 rev = PCI_REVISION(ahc->bd->class); 1632 if (rev >= 4) { 1633 ahc->chip = AHC_AIC7895C; 1634 ahc->features = AHC_AIC7895C_FE; 1635 } else { 1636 u_int command; 1637 1638 ahc->chip = AHC_AIC7895; 1639 ahc->features = AHC_AIC7895_FE; 1640 1641 /* 1642 * The BIOS disables the use of MWI transactions 1643 * since it does not have the MWI bug work around 1644 * we have. Disabling MWI reduces performance, so 1645 * turn it on again. 1646 */ 1647 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1648 PCI_COMMAND_STATUS_REG); 1649 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1650 pci_conf_write(ahc->bd->pc, ahc->bd->tag, 1651 PCI_COMMAND_STATUS_REG, command); 1652 ahc->bugs |= AHC_PCI_MWI_BUG; 1653 } 1654 /* 1655 * XXX Does CACHETHEN really not work??? What about PCI retry? 1656 * on C level chips. Need to test, but for now, play it safe. 1657 */ 1658 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1659 | AHC_CACHETHEN_BUG; 1660 1661 #if 0 1662 uint32_t devconfig; 1663 1664 /* 1665 * Cachesize must also be zero due to stray DAC 1666 * problem when sitting behind some bridges. 1667 */ 1668 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1669 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1670 devconfig |= MRDCEN; 1671 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1672 #endif 1673 ahc->flags |= AHC_NEWEEPROM_FMT; 1674 return (0); 1675 } 1676 1677 static int 1678 ahc_aic7896_setup(struct ahc_softc *ahc) 1679 { 1680 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1681 ahc->chip = AHC_AIC7896; 1682 ahc->features = AHC_AIC7896_FE; 1683 ahc->flags |= AHC_NEWEEPROM_FMT; 1684 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1685 return (0); 1686 } 1687 1688 static int 1689 ahc_aic7899_setup(struct ahc_softc *ahc) 1690 { 1691 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1692 ahc->chip = AHC_AIC7899; 1693 ahc->features = AHC_AIC7899_FE; 1694 ahc->flags |= AHC_NEWEEPROM_FMT; 1695 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1696 return (0); 1697 } 1698 1699 static int 1700 ahc_aha29160C_setup(struct ahc_softc *ahc) 1701 { 1702 int error; 1703 1704 error = ahc_aic7899_setup(ahc); 1705 if (error != 0) 1706 return (error); 1707 ahc->features |= AHC_REMOVABLE; 1708 return (0); 1709 } 1710 1711 static int 1712 ahc_raid_setup(struct ahc_softc *ahc) 1713 { 1714 aprint_normal_dev(ahc->sc_dev, "RAID functionality unsupported\n"); 1715 return (ENXIO); 1716 } 1717 1718 static int 1719 ahc_aha394XX_setup(struct ahc_softc *ahc) 1720 { 1721 1722 switch (ahc->bd->dev) { 1723 case AHC_394X_SLOT_CHANNEL_A: 1724 ahc->channel = 'A'; 1725 break; 1726 case AHC_394X_SLOT_CHANNEL_B: 1727 ahc->channel = 'B'; 1728 break; 1729 default: 1730 printf("adapter at unexpected slot %d\n" 1731 "unable to map to a channel\n", 1732 ahc->bd->dev); 1733 ahc->channel = 'A'; 1734 } 1735 return (0); 1736 } 1737 1738 static int 1739 ahc_aha398XX_setup(struct ahc_softc *ahc) 1740 { 1741 1742 switch (ahc->bd->dev) { 1743 case AHC_398X_SLOT_CHANNEL_A: 1744 ahc->channel = 'A'; 1745 break; 1746 case AHC_398X_SLOT_CHANNEL_B: 1747 ahc->channel = 'B'; 1748 break; 1749 case AHC_398X_SLOT_CHANNEL_C: 1750 ahc->channel = 'C'; 1751 break; 1752 default: 1753 printf("adapter at unexpected slot %d\n" 1754 "unable to map to a channel\n", 1755 ahc->bd->dev); 1756 ahc->channel = 'A'; 1757 break; 1758 } 1759 ahc->flags |= AHC_LARGE_SEEPROM; 1760 return (0); 1761 } 1762 1763 static int 1764 ahc_aha494XX_setup(struct ahc_softc *ahc) 1765 { 1766 1767 switch (ahc->bd->dev) { 1768 case AHC_494X_SLOT_CHANNEL_A: 1769 ahc->channel = 'A'; 1770 break; 1771 case AHC_494X_SLOT_CHANNEL_B: 1772 ahc->channel = 'B'; 1773 break; 1774 case AHC_494X_SLOT_CHANNEL_C: 1775 ahc->channel = 'C'; 1776 break; 1777 case AHC_494X_SLOT_CHANNEL_D: 1778 ahc->channel = 'D'; 1779 break; 1780 default: 1781 printf("adapter at unexpected slot %d\n" 1782 "unable to map to a channel\n", 1783 ahc->bd->dev); 1784 ahc->channel = 'A'; 1785 } 1786 ahc->flags |= AHC_LARGE_SEEPROM; 1787 return (0); 1788 } 1789
Indexes created Tue Sep 30 07:10:03 GMT 2025