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Searched defs:v9d (Results 1 - 4 of 4) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
sparc-opc.c	93 #define v9d (MASK_V9D \| MASK_V9E \| MASK_V9V \| MASK_V9M \| MASK_M8) macro 151 { "v9d", (MASK_V6 \| MASK_V7 \| MASK_V8 \| MASK_V9 \| MASK_V9A \| MASK_V9B 394 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr / 395 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RS2_G0\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [rs1],%efsr / 396 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1+0],%efsr / 397 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0+%rs1],%efsr / 398 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RS1_G0\|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0],%efsr / 399 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|SIMM13(~0)\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1], %efsr */ 2126 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2127 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
sparc-opc.c	93 #define v9d (MASK_V9D \| MASK_V9E \| MASK_V9V \| MASK_V9M \| MASK_M8) macro 151 { "v9d", (MASK_V6 \| MASK_V7 \| MASK_V8 \| MASK_V9 \| MASK_V9A \| MASK_V9B 394 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr / 395 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RS2_G0\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [rs1],%efsr / 396 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1+0],%efsr / 397 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0+%rs1],%efsr / 398 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RS1_G0\|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0],%efsr / 399 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|SIMM13(~0)\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1], %efsr */ 2126 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2127 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, [all...]
/src/external/gpl3/gdb/dist/opcodes/
sparc-opc.c	93 #define v9d (MASK_V9D \| MASK_V9E \| MASK_V9V \| MASK_V9M \| MASK_M8) macro 151 { "v9d", (MASK_V6 \| MASK_V7 \| MASK_V8 \| MASK_V9 \| MASK_V9A \| MASK_V9B 394 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr / 395 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RS2_G0\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [rs1],%efsr / 396 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1+0],%efsr / 397 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0+%rs1],%efsr / 398 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RS1_G0\|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0],%efsr / 399 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|SIMM13(~0)\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1], %efsr */ 2126 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2127 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, [all...]
/src/external/gpl3/gdb.old/dist/opcodes/
sparc-opc.c	93 #define v9d (MASK_V9D \| MASK_V9E \| MASK_V9V \| MASK_V9M \| MASK_M8) macro 151 { "v9d", (MASK_V6 \| MASK_V7 \| MASK_V8 \| MASK_V9 \| MASK_V9A \| MASK_V9B 394 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr / 395 { "ldx", F3(3, 0x21, 0)\|RD(3), F3(~3, ~0x21, ~0)\|RS2_G0\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [rs1],%efsr / 396 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1+0],%efsr / 397 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0+%rs1],%efsr / 398 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|RS1_G0\|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [0],%efsr / 399 { "ldx", F3(3, 0x21, 1)\|RD(3), F3(~3, ~0x21, ~1)\|SIMM13(~0)\|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, / ldx [%rs1], %efsr */ 2126 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2127 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, [all...]

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