| /src/sys/arch/arm/altera/ |
| cycv_clkmgr.c | 615 uint64_t vco; local in function:cycv_clkmgr_early_get_mpu_clk
620 vco = (uint64_t) CYCV_CLOCK_OSC1 *
625 return vco / 2 / (__SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MPUCLK_CNT) + 1);
635 uint64_t vco; local in function:cycv_clkmgr_early_get_l4_sp_clk
642 vco = (uint64_t) CYCV_CLOCK_OSC1 *
648 res = vco / 4 / (tmp + 1);
651 vco = (uint64_t) CYCV_CLOCK_OSC1 *
658 res = vco / (tmp + 1);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.c | 228 unsigned int vco; local in function:intel_hpll_vco
248 vco = vco_table[tmp & 0x7];
249 if (vco == 0)
250 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
252 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
254 return vco;
269 cdclk_state->vco = intel_hpll_vco(dev_priv);
278 switch (cdclk_state->vco) {
295 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
1001 int vco = cdclk_state->vco; local in function:skl_set_cdclk
1500 int vco = cdclk_state->vco; local in function:bxt_set_cdclk
1614 int cdclk, vco; local in function:bxt_sanitize_cdclk
2183 int vco, i; local in function:skl_dpll0_vco
2216 int min_cdclk, cdclk, vco; local in function:skl_modeset_calc_cdclk
2252 int min_cdclk, min_voltage_level, cdclk, vco; local in function:bxt_modeset_calc_cdclk
2462 int max_cdclk, vco; local in function:intel_update_max_cdclk
[all...] |
| intel_dpll_mgr.c | 722 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
795 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
797 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1743 int vco; member in struct:bxt_clk_div
1784 clk_div->vco = best_clock.vco;
1803 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1811 int vco = clk_div->vco; local in function:bxt_ddi_set_dpll_hw_state
[all...] |
| intel_display_types.h | 454 int vco; member in struct:dpll
|
| intel_display.c | 186 } dot, vco, n, m, m1, m2, p, p1; member in struct:intel_limit
262 .vco = { .min = 908000, .max = 1512000 },
275 .vco = { .min = 908000, .max = 1512000 },
288 .vco = { .min = 908000, .max = 1512000 },
301 .vco = { .min = 1400000, .max = 2800000 },
314 .vco = { .min = 1400000, .max = 2800000 },
328 .vco = { .min = 1750000, .max = 3500000},
343 .vco = { .min = 1750000, .max = 3500000},
356 .vco = { .min = 1750000, .max = 3500000 },
370 .vco = { .min = 1750000, .max = 3500000 }
8325 int vco; local in function:chv_prepare_pll
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cypress_dpm.c | 450 u32 vco = clkf * ref_clk; local in function:cypress_map_clkf_to_ibias
454 if (vco > 500000)
456 if (vco > 400000)
458 if (vco > 330000)
460 if (vco > 250000)
462 if (vco > 160000)
464 if (vco > 120000)
470 if (vco > 250000)
472 if (vco > 200000)
474 if (vco > 150000
[all...] |
| radeon_display.c | 1197 uint32_t vco; local in function:radeon_compute_pll_legacy
1206 vco = radeon_div(tmp, ref_div);
1208 if (vco < pll_out_min) {
1211 } else if (vco > pll_out_max) {
1229 vco_diff = abs(vco - best_vco);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 895 unsigned int cdclk, vco, ref, bypass; member in struct:intel_cdclk_state
|
