1 /* $NetBSD: viper.h,v 1.4 2024/05/14 19:00:43 andvar Exp $ */ 2 3 /* $OpenBSD: viper.h,v 1.2 1999/06/29 20:56:10 mickey Exp $ */ 4 5 /* 6 * Copyright 1996 1995 by Open Software Foundation, Inc. 7 * All Rights Reserved 8 * 9 * Permission to use, copy, modify, and distribute this software and 10 * its documentation for any purpose and without fee is hereby granted, 11 * provided that the above copyright notice appears in all copies and 12 * that both the copyright notice and this permission notice appear in 13 * supporting documentation. 14 * 15 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 16 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 17 * FOR A PARTICULAR PURPOSE. 18 * 19 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 20 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 21 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 22 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 23 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 24 * 25 */ 26 /* 27 * Copyright (c) 1991,1994 The University of Utah and 28 * the Computer Systems Laboratory (CSL). All rights reserved. 29 * 30 * Permission to use, copy, modify and distribute this software is hereby 31 * granted provided that (1) source code retains these copyright, permission, 32 * and disclaimer notices, and (2) redistributions including binaries 33 * reproduce the notices in supporting documentation, and (3) all advertising 34 * materials mentioning features or use of this software display the following 35 * acknowledgement: ``This product includes software developed by the 36 * Computer Systems Laboratory at the University of Utah.'' 37 * 38 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 39 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 40 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 41 * 42 * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any 43 * improvements that they make and grant CSL redistribution rights. 44 * 45 * Utah $Hdr: viper.h 1.8 94/12/14$ 46 */ 47 48 #define VIPER_HPA 0xfffbf000 49 50 /* 51 * Viper control register. 52 * 53 * With respect to arbitration preference (*_prf), only one of these may be 54 * set at any one time. "preference" means that a particular device will 55 * be granted the bus on every other arbitration cycle; these bits default 56 * to unset (0). Similarly, a device may be denied the bus (*_den); these 57 * bits default to *set* (1). 58 * 59 * The macros V_CTRL_ANYPRF or V_CTRL_ANYDEN should be used to determine 60 * if any preference or deny bits are set. 61 */ 62 #define VIPER_BITS "\020\001eisa_den\002eisa_prf\003core_den\004core_prf" \ 63 "\005sgc1_den\006sgc1_prf\007sgc0_den\010sgc0_prf" \ 64 "\012cpu_prf\021lpmc_en\022ipref_en" 65 struct vi_ctrl { /* (WO) */ 66 u_int vsc_tout:13, /* VSC clocks to wait before buserr timeout */ 67 : 1, 68 ipref_en: 1, /* enable instruction prefetching */ 69 lpmc_en : 1, /* enable Low Priority Machine Checks */ 70 : 6, 71 cpu_prf : 1, /* CPU has arbitration preference */ 72 : 1, 73 sgc0_prf: 1, /* SGC0 has arbitration preference */ 74 sgc0_den: 1, /* SGC0 denied bus grants */ 75 sgc1_prf: 1, /* SGC1 has arbitration preference */ 76 sgc1_den: 1, /* SGC1 denied bus grants */ 77 core_prf: 1, /* CORE bus has arbitration preference */ 78 core_den: 1, /* CORE denied bus grants */ 79 eisa_prf: 1, /* EISA bus has arbitration preference */ 80 eisa_den: 1; /* EISA denied bus grants */ 81 }; 82 #define VI_CTRL_ANYPRF 0x02AA 83 #define VI_CTRL_ANYDEN 0x0055 84 #define VI_CTRL PAGE0->pz_Pdep.pd_Viper.v_Ctrlcpy 85 86 #define VI_STAT_BITS "\020\001grf_buserr\002cpu_buserr\003ven_tmo" \ 87 "\004ven_buserr\005toc\006hardecc\007softecc\010cmdrst" 88 struct vi_stat { /* (RO) */ 89 u_int hw_rev :24, /* Viper hardware revision (24 bits!) */ 90 cmdreset: 1, /* set if last chip reset caused by CMD_RESET */ 91 softecc : 1, /* correctable memory error (lpmc_en set) */ 92 hardecc : 1, /* uncorrectable memory error (HPMC) */ 93 toc : 1, /* Transfer Of Control signaled */ 94 vn_ader : 1, /* Venom address error (lpmc_en set) */ 95 vn_vscto: 1, /* Venom VSC timeout (lpmc_en set) */ 96 cpu_ader: 1, /* CPU address error or timeout (HPMC) */ 97 grf_ader: 1; /* Graphics address error */ 98 }; 99 100 101 /* 102 * Viper TRS. The structures have been defined above; the remaining 103 * fields are described here. 104 * 105 * vi_intrwd (WO) 106 * If a high to low transition of the interrupt line occurs, 107 * Viper will send this to the CPU to be or'd into its EIR. 108 * In general, this is an ASP interrupt request. 109 * 110 * vi_mem_ctrl (WO) 111 * Set various DRAM attributes (row, cols, refresh, etc). 112 * 113 * vi_mem_wrchk (WO), vi_mem_rdchk (RO) 114 * read/write data to be for copyin/memtest. 115 * 116 * vi_mem_limit (WO) 117 * Set an upper limit for non-IO memory accesses; this must 118 * be less than the actual memory size, low 22 bits ignored. 119 * 120 * vi_merr_w0, vi_merr_w1, vi_merr_ckbyte, vi_merr_addr (RO) 121 * If memory error detection enabled and soft/hard ECC error, 122 * raw double word is stored here (w0: most significant word). 123 * The raw checkbyte data is stored in "vi_merr_ckbyte". 124 * The address of last logged error is in "vi_merr_addr". 125 * 126 */ 127 struct vi_trs { 128 u_int vi_control; /* PAGE0->pz_Pdep.pd_Viper.v_Ctrlcpy */ 129 struct vi_stat vi_status; 130 u_int vi_intrwd; 131 u_int vi_resv1[13]; 132 u_int vi_mem_ctrl; 133 u_int vi_mem_wrchk; 134 u_int vi_mem_limit; 135 u_int vi_resv2[1]; 136 u_int vi_merr_w1; 137 u_int vi_merr_w2; 138 u_int vi_merr_ckbyte; 139 u_int vi_mem_rdchk; 140 u_int vi_merr_addr; 141 u_int vi_resv3[135]; 142 }; 143 144 145 /* 146 ** Viper also creates HPA registers for the graphics accelerator (Venom). 147 ** Venom has two sets of registers; the User HPA contains registers that 148 ** users are allowed to access, while the Supervisor HPA is only accessible 149 ** by code running at the most privileged level. Both sets of registers 150 ** are defined below. 151 */ 152 153 #define VENOM_USER ((struct vn_user *)0xFFFBC000) 154 #define VENOM_SUPR ((struct vn_supr *)0xFFFBD000) 155 156 /* 157 * Define bits in the Venom "User Control" register. 158 */ 159 struct vnu_ctl { 160 u_int sdt_msk :16, /* screen door transparancy mask */ 161 : 6, 162 d_z_intp: 1, /* disable Z Interpolation when set */ 163 d_c_intp: 1, /* disable Color Interpolation when set */ 164 d_ad_inc: 1, /* disable I/O Addr Incrementing when set */ 165 : 1, 166 z_fast : 1, /* enable Fast Z Interpolation when set */ 167 c_pseudo: 1, /* enable Pseudo Color when set (disable RG) */ 168 z_prec24: 1, /* enable 24-bit Z integer precision (o/w 16) */ 169 cmp_intp: 3; /* enable cond: Z intp owrites old Z (<,>,=) */ 170 }; 171 172 /* 173 * When vnu_ctl's "z_prec24" is set, 24-bit Z integer precision is enabled 174 * (otherwise 16-bit integer precision is used). When enabled, the format 175 * of various User Control registers is changed; `vnu_prec' (defined below) 176 * should make this format more clear. 177 */ 178 union vnu_prec { /* 16 or 24 bit precision */ 179 struct { 180 u_int zero1; /* must be zero */ 181 u_int intg :16, /* integer part (16 bits) */ 182 frac :12, /* fractional part (12 bits) */ 183 zero2 : 4; /* must be zero */ 184 } prec16; 185 struct { 186 u_int frac_lo : 4, /* fractional part (lower 4 bits) */ 187 zero1 :28; /* must be zero */ 188 u_int intg :24, /* integer part (24 bits) */ 189 frac_hi : 8; /* fractional part (upper 8 bits) */ 190 } prec24; 191 }; 192 #define vnu_p16i prec16.intg 193 #define vnu_p16f prec16.frac 194 #define vnu_p24i prec24.intg 195 #define vnu_p24f ((prec24.frac_hi << 4) | prec24.frac_lo) 196 #define vnu_p24fh prec24.frac_hi 197 #define vnu_p24fl prec24.frac_lo 198 199 /* 200 * Venom User HPA registers. 201 */ 202 struct vn_user { 203 u_int vnu_resv1[32]; 204 struct vnu_ctl vnu_uctl; /* user control */ 205 u_int vnu_spancnt; /* span count (13 bits, signed) */ 206 u_int vnu_graddr; /* graphics address (24 bits: 6-29) */ 207 u_int vnu_resv2; 208 union vnu_prec vnu_zslope; /* Z Slope */ 209 union vnu_prec vnu_z; /* Z */ 210 u_int vnu_resv3[8]; 211 u_int vnu_bslope; /* Blue Slope (12-19:int, 20-31:fra) */ 212 u_int vnu_bcolor; /* Blue Color (12-19:int, 20-31:fra) */ 213 u_int vnu_resv4[2]; 214 u_int vnu_rslope; /* Red Slope (12-19:int, 20-31:fra) */ 215 u_int vnu_rcolor; /* Red Color (12-19:int, 20-31:fra) */ 216 u_int vnu_resv5[2]; 217 u_int vnu_gslope; /* Green Slope (12-19:int, 20-31:fra) */ 218 u_int vnu_gcolor; /* Green Color (12-19:int, 20-31:fra) */ 219 }; 220 221 222 /* 223 * Define bits in Venom "Supervisor Control" register. 224 */ 225 struct vns_ctl { 226 u_int : 4, 227 ioaddr : 2, /* graphics addr (bits 4 & 5 of `vnu_graddr') */ 228 d_venom : 1, /* disable Venom operation processing */ 229 :25; 230 }; 231 232 /* 233 * Venom Supervisor HPA registers. 234 */ 235 struct vn_supr { 236 u_int vns_resv1[32]; 237 struct vns_ctl vns_sctl; /* supervisor control */ 238 u_int vns_zaddr; /* Z Buffer Address (RO) */ 239 }; 240 241 void viper_setintrwnd(uint32_t); 242 void viper_eisa_en(void); 243 244
Indexes created Thu Sep 25 16:09:42 GMT 2025