1 /* $NetBSD: gtmr.c,v 1.53 2026/10/13 14:20:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.53 2026/10/13 14:20:07 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/percpu.h> 42 #include <sys/proc.h> 43 #include <sys/systm.h> 44 #include <sys/timetc.h> 45 #include <sys/cpu.h> 46 47 #include <prop/proplib.h> 48 49 #include <arm/locore.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/cortex/gtmr_var.h> 53 #include <arm/cortex/mpcore_var.h> 54 55 static int gtmr_match(device_t, cfdata_t, void *); 56 static void gtmr_attach(device_t, device_t, void *); 57 58 static u_int gtmr_get_timecount(struct timecounter *); 59 60 static uint64_t gtmr_read_cntct(struct gtmr_softc *); 61 static uint32_t gtmr_read_ctl(struct gtmr_softc *); 62 static void gtmr_write_ctl(struct gtmr_softc *, uint32_t); 63 static void gtmr_write_tval(struct gtmr_softc *, uint32_t); 64 static void gtmr_write_cval(struct gtmr_softc *, uint64_t); 65 66 static struct gtmr_softc gtmr_sc; 67 68 struct gtmr_percpu { 69 uint32_t pc_delta; 70 }; 71 72 static struct timecounter gtmr_timecounter = { 73 .tc_get_timecount = gtmr_get_timecount, 74 .tc_poll_pps = 0, 75 .tc_counter_mask = ~0u, 76 .tc_frequency = 0, /* set by cpu_initclocks() */ 77 .tc_name = NULL, /* set by attach */ 78 .tc_quality = 500, 79 .tc_priv = >mr_sc, 80 .tc_next = NULL, 81 }; 82 83 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 84 85 /* ARGSUSED */ 86 static int 87 gtmr_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct mpcore_attach_args * const mpcaa = aux; 90 91 if (gtmr_sc.sc_dev != NULL) 92 return 0; 93 94 /* Generic Timer is always implemented in ARMv8-A */ 95 if (!cpu_gtmr_exists_p()) 96 return 0; 97 98 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 99 return 0; 100 101 return 1; 102 } 103 104 static void 105 gtmr_attach(device_t parent, device_t self, void *aux) 106 { 107 struct mpcore_attach_args * const mpcaa = aux; 108 struct gtmr_softc *sc = >mr_sc; 109 prop_dictionary_t dict = device_properties(self); 110 char freqbuf[sizeof("X.XXX SHz")]; 111 bool flag; 112 113 /* 114 * This runs at a fixed frequency of 1 to 50MHz. 115 */ 116 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) 117 sc->sc_freq = gtmr_cntfrq_read(); 118 119 if (!prop_dictionary_get_bool(dict, "physical", &sc->sc_physical)) { 120 /* Now check the parent device */ 121 KASSERT(parent == device_parent(self)); 122 const prop_dictionary_t pdict = device_properties(parent); 123 124 prop_dictionary_get_bool(pdict, "physical", &sc->sc_physical); 125 } 126 127 KASSERT(sc->sc_freq != 0); 128 129 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 130 131 aprint_naive("\n"); 132 aprint_normal(": Generic Timer (%s, %s)\n", freqbuf, 133 sc->sc_physical ? "physical" : "virtual"); 134 135 #if defined(__arm__) 136 if (prop_dictionary_get_bool(dict, "arm,cpu-registers-not-fw-configured", &flag) && flag) { 137 sc->sc_flags |= GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED; 138 aprint_debug_dev(self, "CPU registers not initialized by firmware\n"); 139 } 140 #endif 141 142 if (prop_dictionary_get_bool(dict, "sun50i-a64-unstable-timer", &flag) && flag) { 143 sc->sc_flags |= GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER; 144 aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n"); 145 } 146 147 device_set_private(self, sc); 148 sc->sc_dev = self; 149 150 #ifdef DIAGNOSTIC 151 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 152 #endif 153 154 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 155 device_xname(self), "missing interrupts"); 156 157 if (mpcaa->mpcaa_irq != -1) { 158 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 159 IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL); 160 if (sc->sc_global_ih == NULL) 161 panic("%s: unable to register timer interrupt", __func__); 162 aprint_normal_dev(self, "interrupting on irq %d\n", 163 mpcaa->mpcaa_irq); 164 } 165 166 const uint32_t cnt_frq = gtmr_cntfrq_read(); 167 if (cnt_frq == 0) { 168 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 169 } else if (cnt_frq != sc->sc_freq) { 170 aprint_verbose_dev(self, 171 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 172 cnt_frq); 173 } 174 175 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 176 gtmr_timecounter.tc_frequency = sc->sc_freq; 177 gtmr_timecounter.tc_priv = sc; 178 179 tc_init(>mr_timecounter); 180 181 /* Disable the timer until we are ready */ 182 gtmr_write_ctl(sc, 0); 183 } 184 185 static uint64_t 186 gtmr_read_cntct(struct gtmr_softc *sc) 187 { 188 isb(); 189 190 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 191 /* 192 * The Allwinner A64 SoC has an unstable architectural timer. 193 * To workaround this problem, ignore reads where the lower 194 * 10 bits are all 0s or 1s. 195 */ 196 uint64_t val; 197 u_int bits; 198 do { 199 val = sc->sc_physical ? gtmr_cntpct_read() : gtmr_cntvct_read(); 200 bits = val & __BITS(9,0); 201 } while (bits == 0 || bits == __BITS(9,0)); 202 return val; 203 } 204 205 return sc->sc_physical ? gtmr_cntpct_read() : gtmr_cntvct_read(); 206 } 207 208 static uint32_t 209 gtmr_read_ctl(struct gtmr_softc *sc) 210 { 211 isb(); 212 213 if (sc->sc_physical) 214 return gtmr_cntp_ctl_read(); 215 else 216 return gtmr_cntv_ctl_read(); 217 } 218 219 static void 220 gtmr_write_ctl(struct gtmr_softc *sc, uint32_t val) 221 { 222 if (sc->sc_physical) 223 gtmr_cntp_ctl_write(val); 224 else 225 gtmr_cntv_ctl_write(val); 226 227 isb(); 228 } 229 230 static void 231 gtmr_write_tval(struct gtmr_softc *sc, uint32_t val) 232 { 233 if (sc->sc_physical) 234 gtmr_cntp_tval_write(val); 235 else 236 gtmr_cntv_tval_write(val); 237 238 isb(); 239 } 240 241 static void 242 gtmr_write_cval(struct gtmr_softc *sc, uint64_t val) 243 { 244 if (sc->sc_physical) 245 gtmr_cntp_cval_write(val); 246 else 247 gtmr_cntv_cval_write(val); 248 249 isb(); 250 } 251 252 253 void 254 gtmr_init_cpu_clock(struct cpu_info *ci) 255 { 256 struct gtmr_softc * const sc = >mr_sc; 257 uint32_t cntk; 258 uint64_t ctl; 259 260 KASSERT(ci == curcpu()); 261 262 /* XXX hmm... called from cpu_hatch which hasn't lowered ipl yet */ 263 int s = splsched(); 264 265 #if defined(__arm__) 266 if ((sc->sc_flags & GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED) != 0) { 267 armreg_cnt_frq_write(sc->sc_freq); 268 } 269 #endif 270 271 /* 272 * Allow the virtual and physical counters to be accessed from 273 * usermode. (PL0) 274 */ 275 cntk = gtmr_cntk_ctl_read(); 276 cntk &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN); 277 if (sc->sc_physical) { 278 cntk |= CNTKCTL_PL0PCTEN; 279 cntk &= ~CNTKCTL_PL0VCTEN; 280 } else { 281 cntk |= CNTKCTL_PL0VCTEN; 282 cntk &= ~CNTKCTL_PL0PCTEN; 283 } 284 gtmr_cntk_ctl_write(cntk); 285 isb(); 286 287 /* 288 * enable timer and stop masking the timer. 289 */ 290 ctl = gtmr_read_ctl(sc); 291 ctl &= ~CNTCTL_IMASK; 292 ctl |= CNTCTL_ENABLE; 293 gtmr_write_ctl(sc, ctl); 294 295 /* 296 * Get now and update the compare timer. 297 */ 298 ci->ci_lastintr = gtmr_read_cntct(sc); 299 gtmr_write_tval(sc, sc->sc_autoinc); 300 301 splx(s); 302 303 KASSERT(gtmr_read_cntct(sc) != 0); 304 } 305 306 void 307 gtmr_cpu_initclocks(void) 308 { 309 struct gtmr_softc * const sc = >mr_sc; 310 311 KASSERT(sc->sc_dev != NULL); 312 KASSERT(sc->sc_freq != 0); 313 314 sc->sc_autoinc = sc->sc_freq / hz; 315 316 gtmr_init_cpu_clock(curcpu()); 317 } 318 319 void 320 gtmr_delay(unsigned int n) 321 { 322 struct gtmr_softc * const sc = >mr_sc; 323 324 KASSERT(sc != NULL); 325 326 uint32_t freq = sc->sc_freq ? sc->sc_freq : gtmr_cntfrq_read(); 327 KASSERT(freq != 0); 328 329 const unsigned int incr_per_us = howmany(freq, 1000000); 330 int64_t ticks = (int64_t)n * incr_per_us; 331 332 uint64_t last = gtmr_read_cntct(sc); 333 334 while (ticks > 0) { 335 SPINLOCK_BACKOFF_HOOK; 336 uint64_t curr = gtmr_read_cntct(sc); 337 if (curr >= last) 338 ticks -= (curr - last); 339 else 340 ticks -= (UINT64_MAX - curr + last); 341 last = curr; 342 } 343 } 344 345 /* 346 * gtmr_intr: 347 * 348 * Handle the hardclock interrupt. 349 */ 350 int 351 gtmr_intr(void *arg) 352 { 353 struct cpu_info * const ci = curcpu(); 354 struct clockframe * const cf = arg; 355 struct gtmr_softc * const sc = >mr_sc; 356 357 const uint32_t ctl = gtmr_read_ctl(sc); 358 if ((ctl & (CNTCTL_ENABLE | CNTCTL_ISTATUS)) != (CNTCTL_ENABLE | CNTCTL_ISTATUS)) { 359 aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl); 360 return 0; 361 } 362 363 const uint64_t now = gtmr_read_cntct(sc); 364 uint64_t delta = now - ci->ci_lastintr; 365 366 #ifdef DIAGNOSTIC 367 struct gtmr_percpu *pc = NULL; 368 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 369 const uint64_t then = sc->sc_physical ? gtmr_cntp_cval_read() : gtmr_cntv_cval_read(); 370 pc = percpu_getref(sc->sc_percpu); 371 KASSERTMSG(then <= now, "%"PRId64, now - then); 372 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 373 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 374 } 375 #endif 376 377 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 378 KASSERTMSG(delta > sc->sc_autoinc / 100, 379 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 380 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 381 } 382 383 /* 384 * If we got interrupted too soon (delta < sc->sc_autoinc) 385 * or we missed (or almost missed) a tick 386 * (delta >= 7 * sc->sc_autoinc / 4), don't try to adjust for jitter. 387 */ 388 if (delta >= sc->sc_autoinc && delta <= 7 * sc->sc_autoinc / 4) { 389 delta -= sc->sc_autoinc; 390 } else { 391 delta = 0; 392 } 393 394 isb(); 395 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 396 gtmr_write_cval(sc, now + sc->sc_autoinc - delta); 397 } else { 398 gtmr_write_tval(sc, sc->sc_autoinc - delta); 399 } 400 401 ci->ci_lastintr = now; 402 403 #ifdef DIAGNOSTIC 404 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 405 KASSERT(delta == (uint32_t) delta); 406 pc->pc_delta = delta; 407 percpu_putref(sc->sc_percpu); 408 } 409 #endif 410 411 hardclock(cf); 412 413 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 414 415 return 1; 416 } 417 418 #ifndef __HAVE_GENERIC_SETSTATCLOCKRATE 419 void 420 setstatclockrate(int newhz) 421 { 422 /* use hardclock */ 423 } 424 #endif 425 426 static u_int 427 gtmr_get_timecount(struct timecounter *tc) 428 { 429 struct gtmr_softc * const sc = tc->tc_priv; 430 431 return (u_int) gtmr_read_cntct(sc); 432 } 433
Indexes created Sun Oct 25 00:26:45 UTC 2026