| /src/sys/arch/arm/rockchip/ |
| rk_cru_gate.c | 47 const uint32_t write_mask = gate->mask << 16; local in function:rk_cru_gate_enable
50 CRU_WRITE(sc, gate->reg, write_mask | write_val);
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| rk_cru_mux.c | 77 const uint32_t write_mask = mux->mask << 16; local in function:rk_cru_mux_set_parent
82 syscon_write_4(sc->sc_grf, mux->reg, write_mask | write_val);
85 CRU_WRITE(sc, mux->reg, write_mask | write_val);
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| rk3288_usb.c | 125 uint32_t write_mask, write_val; local in function:rk3288_usbphy_enable
127 write_mask = GRF_UOCn_CON0_SIDDQ << 16;
131 syscon_write_4(sc->sc_syscon, sc->sc_reg, write_mask | write_val);
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| rk_cru_arm.c | 106 const uint32_t write_mask = arm->divs[i].mask << 16; local in function:rk_cru_arm_set_rate_rates
109 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
124 uint32_t write_mask, write_val; local in function:rk_cru_arm_set_rate_cpurates
162 write_mask = cpu_rate->divs[i].mask << 16;
164 CRU_WRITE(sc, cpu_rate->divs[i].reg, write_mask | write_val);
171 write_mask = arm->divs[i].mask << 16;
173 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
222 const uint32_t write_mask = arm->mux_mask << 16; local in function:rk_cru_arm_set_parent
225 CRU_WRITE(sc, arm->mux_reg, write_mask | write_val);
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| rk_cru_composite.c | 52 const uint32_t write_mask = composite->gate_mask << 16; local in function:rk_cru_composite_enable
55 CRU_WRITE(sc, composite->gate_reg, write_mask | write_val);
204 uint32_t write_mask = composite->div_mask << 16; local in function:rk_cru_composite_set_rate
207 write_mask |= composite->mux_mask << 16;
211 CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
249 const uint32_t write_mask = composite->mux_mask << 16; local in function:rk_cru_composite_set_parent
252 CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
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| rk3399_pmucru.c | 247 const uint32_t write_mask = pll->mode_mask << 16; local in function:rk3399_pmucru_pll_set_rate
249 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
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| rk_anxdp.c | 80 const uint32_t write_mask = EDP_LCDC_SEL << 16; local in function:rk_anxdp_select_input
84 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
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| rk_usb.c | 121 uint32_t reg, write_mask, write_val; local in function:rk_usb_clk_enable
126 write_mask = RK3328_USBPHY_COMMONONN << 16;
133 write_mask = RK3399_USBPHY_COMMONONN << 16;
141 syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
151 uint32_t reg, write_mask, write_val; local in function:rk_usb_clk_disable
156 write_mask = RK3328_USBPHY_COMMONONN << 16;
163 write_mask = RK3399_USBPHY_COMMONONN << 16;
171 syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
303 uint32_t reg, write_mask, write_val; local in function:rk_usbphy_otg_enable
309 write_mask = 0x1ffU << 16
342 uint32_t reg, write_mask, write_val; local in function:rk_usbphy_host_enable
[all...] |
| rk_dwhdmi.c | 101 const uint32_t write_mask = HDMI_LCDC_SEL << 16; local in function:rk_dwhdmi_select_input
105 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
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| rk_cru_pll.c | 252 const uint32_t write_mask = pll->mode_mask << 16; local in function:rk_cru_pll_set_rate
254 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
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| rk3399_iomux.c | 337 const uint32_t write_mask = (drv_mask & 0xffff) << 16; local in function:rk3399_iomux_set_drive_strength
338 if (write_mask) {
342 WR4(syscon, reg, write_val | write_mask);
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| rk_gmac.c | 106 uint32_t write_mask, write_val; local in function:rk3288_gmac_set_mode_rgmii
110 write_mask = (RK3288_GRF_SOC_CON1_RMII_MODE |
115 write_mask | write_val);
118 write_mask = (RK3288_GRF_SOC_CON3_RXCLK_DLY_ENA_GMAC |
124 write_mask |= RK3288_GRF_SOC_CON3_TXCLK_DLY_ENA_GMAC |
129 write_mask |= RK3288_GRF_SOC_CON3_RXCLK_DLY_ENA_GMAC |
134 write_mask | write_val);
144 uint32_t write_mask, write_val; local in function:rk3288_gmac_set_speed_rgmii
148 write_mask = (RK3288_GRF_SOC_CON1_GMAC_CLK_SEL) << 16;
162 write_mask | write_val)
190 uint32_t write_mask, write_val; local in function:rk3328_gmac_set_mode_rgmii
275 uint32_t write_mask, write_val; local in function:rk3399_gmac_set_mode_rgmii
[all...] |
| rk_gpio.c | 282 const uint32_t write_mask = GPIOV2_WRITE_MASK(pin); local in function:rk_gpio_v2_pin_write
286 WR4(sc, GPIOV2_SWPORT_DR_REG(pin), write_mask | data);
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| rk3399_cru.c | 1124 uint32_t write_mask, write_val; local in function:rk3399_cru_init
1137 write_mask = __BITS(7,0) << 16;
1139 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val);
1140 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val);
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvfw/ |
| acr.h | 109 u32 write_mask; member in struct:flcn_acr_desc::__anond9ca4e0f0208::__anond9ca4e0f0308
138 u32 write_mask; member in struct:flcn_acr_desc_v1::__anond9ca4e0f0508::__anond9ca4e0f0608
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