| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-dis.c | 840 unsigned op, xop, seg; local
846 * All SPE2 instructions have OP=4 and differs by XOP */
849 xop = SPE2_XOP (insn);
850 seg = SPE2_XOP_TO_SEG (xop);
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-dis.c | 829 unsigned op, xop, seg; local
835 * All SPE2 instructions have OP=4 and differs by XOP */
838 xop = SPE2_XOP (insn);
839 seg = SPE2_XOP_TO_SEG (xop);
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-dis.c | 819 unsigned op, xop, seg; local
825 * All SPE2 instructions have OP=4 and differs by XOP */
828 xop = SPE2_XOP (insn);
829 seg = SPE2_XOP_TO_SEG (xop);
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-dis.c | 819 unsigned op, xop, seg; local
825 * All SPE2 instructions have OP=4 and differs by XOP */
828 xop = SPE2_XOP (insn);
829 seg = SPE2_XOP_TO_SEG (xop);
|
| /src/external/gpl3/gcc.old/dist/gcc/config/avr/ |
| avr.cc | 527 avr_casei_sequence_check_operands (rtx *xop)
533 && xop[8] == all_regs_rtx[24])
536 sub_5 = xop[6];
542 && PLUS == GET_CODE (xop[6])
543 && LABEL_REF == GET_CODE (XEXP (xop[6], 1))
544 && rtx_equal_p (xop[3], XEXP (XEXP (xop[6], 1), 0))
546 && xop[8] == const0_rtx)
548 sub_5 = XEXP (xop[6], 0);
554 && rtx_equal_p (xop[5], SUBREG_REG (sub_5))
3895 rtx xop[7]; local
4067 rtx xop[4]; local
4127 rtx xop[2]; local
4204 rtx xop[2]; local
5638 rtx xop[2]; local
6405 rtx xop[3]; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/arc/ |
| arc.cc | 6962 rtx xop[5];
7269 xop[j++] = target;
7325 xop[j] = op;
7328 pat = apply_GEN_FCN (icode, xop);
9923 rtx xop[4];
9947 xop[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
9948 xop[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
9949 xop[2] = GEN_INT (trunc_int_for_mode (intval0, SImode));
9950 xop[1] = GEN_INT (trunc_int_for_mode (intval1, SImode));
9951 emit_move_insn (xop[0], xop[2])
6961 rtx xop[5]; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/avr/ |
| avr.cc | 567 avr_casei_sequence_check_operands (rtx *xop)
573 && xop[8] == all_regs_rtx[REG_24])
576 sub_5 = xop[6];
582 && PLUS == GET_CODE (xop[6])
583 && LABEL_REF == GET_CODE (XEXP (xop[6], 1))
584 && rtx_equal_p (xop[3], XEXP (XEXP (xop[6], 1), 0))
586 && xop[8] == const0_rtx)
588 sub_5 = XEXP (xop[6], 0);
594 && rtx_equal_p (xop[5], SUBREG_REG (sub_5))
4544 rtx xop[7]; local
4713 rtx xop[4]; local
4773 rtx xop[2]; local
4850 rtx xop[2]; local
6283 rtx xop[2]; local
7212 rtx xop[3] = { gen_rtx_REG (DImode, ACC_A), op[0], op[1] }; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/pa/ |
| pa.cc | 8725 rtx xop[4];
8736 xop[0] = xoperands[0];
8737 xop[1] = gen_rtx_REG (Pmode, 1);
8738 xop[2] = xop[1];
8739 pa_output_pic_pcrel_sequence (xop);
8822 rtx xop[4];
8825 xop[0] = xoperands[0];
8826 xop[1] = gen_rtx_REG (Pmode, 1);
8827 xop[2] = gen_rtx_REG (Pmode, 22)
8711 rtx xop[4]; local
8808 rtx xop[4]; local
8854 rtx xop[4]; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/pa/ |
| pa.cc | 8577 rtx xop[4];
8588 xop[0] = xoperands[0];
8589 xop[1] = gen_rtx_REG (Pmode, 1);
8590 xop[2] = xop[1];
8591 pa_output_pic_pcrel_sequence (xop);
8674 rtx xop[4];
8677 xop[0] = xoperands[0];
8678 xop[1] = gen_rtx_REG (Pmode, 1);
8679 xop[2] = gen_rtx_REG (Pmode, 22)
8563 rtx xop[4]; local
8660 rtx xop[4]; local
8706 rtx xop[4]; local
[all...] |
| /src/external/gpl3/binutils/dist/binutils/ |
| dwarf.c | 5591 int xop; local
5597 xop = op_code;
5648 xop = ext_op_code;
5649 xop = -xop;
5859 if ((is_special_opcode) || (xop == -DW_LNE_end_sequence)
5860 || (xop == DW_LNS_copy))
5906 if (xop == -DW_LNE_end_sequence)
5917 if (xop == -DW_LNE_end_sequence)
5933 if (xop == -DW_LNE_end_sequence
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-i386.c | 1146 SUBARCH (xop, XOP, ANY_XOP, false),
2713 /* For FMA4 and XOP insns VEX.W controls just the first two register
7426 err_msg = _("no VEX/XOP encoding");
7570 /* Check for data size prefix on VEX/XOP/EVEX encoded, SIMD, and
10095 /* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv. */
12534 XOP, FMA4, LPW, TBM, and AMX. */
13561 bool vex = false, xop = false;
13593 else if (startswith (line, "XOP") && ISDIGIT (line[3])
13556 bool vex = false, xop = false; local
[all...] |
| /src/external/gpl3/binutils.old/dist/binutils/ |
| dwarf.c | 5521 int xop; local
5527 xop = op_code;
5578 xop = ext_op_code;
5579 xop = -xop;
5789 if ((is_special_opcode) || (xop == -DW_LNE_end_sequence)
5790 || (xop == DW_LNS_copy))
5836 if (xop == -DW_LNE_end_sequence)
5847 if (xop == -DW_LNE_end_sequence)
5863 if (xop == -DW_LNE_end_sequence
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-i386.c | 1130 SUBARCH (xop, XOP, ANY_XOP, false),
2664 /* For FMA4 and XOP insns VEX.W controls just the first two
7264 err_msg = _("no VEX/XOP encoding");
7405 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
9928 /* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv. */
12380 XOP, FMA4, LPW, TBM, and AMX. */
13410 bool vex = false, xop = false;
13442 else if (startswith (line, "XOP") && ISDIGIT (line[3])
13405 bool vex = false, xop = false; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/arc/ |
| arc.cc | 7059 rtx xop[5];
7366 xop[j++] = target;
7422 xop[j] = op;
7425 pat = apply_GEN_FCN (icode, xop);
10149 rtx xop[4];
10173 xop[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
10174 xop[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
10175 xop[2] = GEN_INT (trunc_int_for_mode (intval0, SImode));
10176 xop[1] = GEN_INT (trunc_int_for_mode (intval1, SImode));
10177 emit_move_insn (xop[0], xop[2])
7058 rtx xop[5]; local
10148 rtx xop[4]; local
[all...] |
