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    Searched defs:zSig0 (Results 1 - 3 of 3) sorted by relevancy

  /src/lib/libc/softfloat/bits32/
softfloat.c 376 the concatenation of `zSig0' and `zSig1' into a double-precision floating-
378 positions, the three fields `zSign', `zExp', and `zSig0' are simply added
380 that any integer portion of `zSig0' will be added into the exponent. Since
383 `zSig0' and `zSig1' concatenated form a complete, normalized significand.
387 packFloat64( flag zSign, int16 zExp, bits32 zSig0, bits32 zSig1 )
392 ( ( (bits64) zSig0 )<<32 ) + zSig1 );
400 and extended significand formed by the concatenation of `zSig0', `zSig1',
421 flag zSign, int16 zExp, bits32 zSig0, bits32 zSig1, bits32 zSig2 )
445 && eq64( 0x001FFFFF, 0xFFFFFFFF, zSig0, zSig1 )
463 || lt64( zSig0, zSig1, 0x001FFFFF, 0xFFFFFFFF )
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  /src/sys/lib/libkern/
softfloat.c 625 | and extended significand formed by the concatenation of `zSig0' and `zSig1',
649 int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
670 zSig0 |= ( zSig1 != 0 );
685 roundBits = zSig0 & roundMask;
688 || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )
696 || ( zSig0 <= zSig0 + roundIncrement );
697 shift64RightJamming( zSig0, 1 - zExp, &zSig0 );
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  /src/lib/libc/softfloat/bits64/
softfloat.c 638 and extended significand formed by the concatenation of `zSig0' and `zSig1',
662 int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
683 zSig0 |= ( zSig1 != 0 );
698 roundBits = zSig0 & roundMask;
701 || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )
709 || ( zSig0 <= zSig0 + roundIncrement );
710 shift64RightJamming( zSig0, 1 - zExp, &zSig0 );
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