1 /* $NetBSD: gs.c,v 1.6 2014/03/31 11:25:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gs.c,v 1.6 2014/03/31 11:25:49 martin Exp $"); 34 35 #include <sys/param.h> 36 37 #include <playstation2/playstation2/sifbios.h> 38 #include <playstation2/ee/eevar.h> 39 #include <playstation2/ee/gsvar.h> 40 #include <playstation2/ee/gsreg.h> 41 #include <playstation2/ee/gifreg.h> 42 43 #ifdef DEBUG 44 #define STATIC 45 #else 46 #define STATIC static 47 #endif 48 49 STATIC const struct gs_crt_param { 50 int w, h, dvemode; 51 u_int64_t smode1, smode2, srfsh, synch1, synch2, syncv, display; 52 } gs_crt_param[] = { 53 [NTSC_NONINTER] = { 54 .w = 640, 55 .h = 240, 56 .dvemode= 0, 57 .smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 58 4, 0, 0, 1, 1, 0, 2, 0, 1, 32, 4), 59 .smode2 = SMODE2(0, 0, 0), 60 .srfsh = SRFSH(8), 61 .synch1 = SYNCH1(254, 1462, 124, 222, 64), 62 .synch2 = SYNCH2(1652, 1240), 63 .syncv = SYNCV(6, 480, 6, 26, 6, 2), 64 .display=DISPLAY(239, 2559, 0, 3, 25, 632) 65 }, 66 [NTSC_INTER] = { 67 .w = 640, 68 .h = 480, 69 .dvemode= 0, 70 .smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 71 4, 0, 0, 1, 1, 0, 2, 0, 1, 32, 4), 72 .smode2 = SMODE2(0, 0, 1), 73 .srfsh = SRFSH(8), 74 .synch1 = SYNCH1(254, 1462, 124, 222, 64), 75 .synch2 = SYNCH2(1652, 1240), 76 .syncv = SYNCV(6, 480, 6, 26, 6, 1), 77 .display= DISPLAY(479, 2559, 0, 3, 50, 632) 78 }, 79 [PAL_NONINTER] = { 80 .w = 640, 81 .h = 288, 82 .dvemode= 1, 83 .smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 84 4, 0, 0, 1, 1, 0, 3, 0, 1, 32, 4), 85 .smode2 = SMODE2(0, 0, 0), 86 .srfsh = SRFSH(8), 87 .synch1 = SYNCH1(254, 1474, 127, 262, 48), 88 .synch2 = SYNCH2(1680, 1212), 89 .syncv = SYNCV(5, 576, 5, 33, 5, 4), 90 .display= DISPLAY(287, 2559, 0, 3, 36, 652) 91 }, 92 [PAL_INTER] = { 93 .w = 640, 94 .h = 576, 95 .dvemode= 1, 96 .smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 97 4, 0, 0, 1, 1, 0, 3, 0, 1, 32, 4), 98 .smode2 = SMODE2(0, 0, 1), 99 .srfsh = SRFSH(8), 100 .synch1 = SYNCH1(254, 1474, 127, 262, 48), 101 .synch2 = SYNCH2(1680, 1212), 102 .syncv = SYNCV(5, 576, 5, 33, 5, 4), 103 .display= DISPLAY(575,2559,0,3,72,652) 104 }, 105 [VESA_1A] = { 106 .w = 640, 107 .h = 480, 108 .dvemode= 2, 109 .smode1 = SMODE1(1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 110 2, 0, 0, 1, 0, 0, 0, 0, 1, 15, 2), 111 .smode2 = SMODE2(0, 0, 0), 112 .srfsh = SRFSH(4), 113 .synch1 = SYNCH1(192, 608, 192, 84, 32), 114 .synch2 = SYNCH2(768, 524), 115 .syncv = SYNCV(2, 480, 0, 33, 0, 10), 116 .display= DISPLAY(479, 1279, 0, 1, 34, 276) 117 } 118 }; 119 120 void 121 gs_init(enum gs_crt_type type) 122 { 123 const struct gs_crt_param *p = &gs_crt_param[type]; 124 u_int64_t smode1 = p->smode1; 125 126 /* GS reset */ 127 _reg_write_8(GS_S_CSR_REG, 1 << 9); 128 129 /* setup PCRTC */ 130 _reg_write_8(GS_S_PMODE_REG, 0); /* disable circuit 1/2 */ 131 132 _reg_write_8(GS_S_SMODE1_REG, smode1 | ((u_int64_t)1 << 16)); 133 _reg_write_8(GS_S_SYNCH1_REG, p->synch1); 134 _reg_write_8(GS_S_SYNCH2_REG, p->synch2); 135 _reg_write_8(GS_S_SYNCV_REG, p->syncv); 136 _reg_write_8(GS_S_SMODE2_REG, p->smode2); 137 _reg_write_8(GS_S_SRFSH_REG, p->srfsh); 138 139 if (p->dvemode == 2) { /* PLL on */ 140 _reg_write_8(GS_S_SMODE1_REG, smode1 & ~((u_int64_t)1 << 16)); 141 delay(2500); 142 } 143 144 /* start sync */ 145 _reg_write_8(GS_S_SMODE1_REG, 146 smode1 & ~((u_int64_t)1 << 16) & ~((u_int64_t)1 << 17)); 147 148 sifbios_setdve(p->dvemode); 149 150 /* enable circuit */ 151 _reg_write_8(GS_S_PMODE_REG, 0x66); 152 153 /* display environment */ 154 _reg_write_8(GS_S_DISPLAY2_REG, p->display); 155 _reg_write_8(GS_S_DISPFB2_REG, (p->w >> 6) << 9); 156 _reg_write_8(GS_S_SMODE2_REG, p->smode2); 157 _reg_write_8(GS_S_BGCOLOR_REG, 0); 158 159 /* Flush GS FIFO */ 160 _reg_write_8(GS_S_CSR_REG, 1 << 8); 161 162 /* GIF reset */ 163 _reg_write_4(GIF_CTRL_REG, 1); 164 } 165
Indexes created Mon Sep 22 10:09:38 GMT 2025