1 /* $NetBSD: fpu_fscale.c,v 1.18 2026/11/01 12:13:24 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: fpu_fscale.c,v 1.18 2026/11/01 12:13:24 thorpej Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/signal.h> 45 #include <sys/systm.h> 46 #include <machine/frame.h> 47 48 #include "fpu_emulate.h" 49 50 int 51 fpu_emul_fscale(struct fpemu *fe, struct instruction *insn) 52 { 53 struct frame *frame; 54 uint32_t *fpregs; 55 int word1, sig; 56 int regnum, format; 57 int modreg; 58 int scale, sign, exp; 59 uint32_t m0, m1; 60 uint32_t buf[3], fpsr; 61 #if DEBUG_FPE 62 int flags; 63 char regname; 64 #endif 65 66 scale = sig = 0; 67 frame = fe->fe_frame; 68 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 69 /* clear all exceptions and conditions */ 70 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 71 #if DEBUG_FPE 72 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 73 #endif 74 75 word1 = insn->is_word1; 76 format = (word1 >> 10) & 7; 77 regnum = (word1 >> 7) & 7; 78 79 fe->fe_fpcr &= FPCR_ROUND; 80 fe->fe_fpcr |= FPCR_ZERO; 81 82 /* get the source operand */ 83 if ((word1 & 0x4000) == 0) { 84 #if DEBUG_FPE 85 printf("fpu_emul_fscale: FP%d op FP%d => FP%d\n", 86 format, regnum, regnum); 87 /* the operand is an FP reg */ 88 printf("fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 89 format, fpregs[format*3], fpregs[format*3+1], 90 fpregs[format*3+2]); 91 #endif 92 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 93 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 94 scale = buf[0]; 95 } else { 96 /* the operand is in memory */ 97 if (format == FTYPE_DBL) { 98 insn->is_datasize = 8; 99 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 100 insn->is_datasize = 4; 101 } else if (format == FTYPE_WRD) { 102 insn->is_datasize = 2; 103 } else if (format == FTYPE_BYT) { 104 insn->is_datasize = 1; 105 } else if (format == FTYPE_EXT) { 106 insn->is_datasize = 12; 107 } else { 108 /* invalid or unsupported operand format */ 109 sig = SIGFPE; 110 return sig; 111 } 112 113 /* Check an illegal mod/reg. */ 114 modreg = insn->is_opcode & 077; 115 if ((modreg >> 3) == 1/*An*/ || modreg >= 075) { 116 return SIGILL; 117 } 118 119 /* Get effective address. (modreg=opcode&077) */ 120 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 121 if (sig) { 122 #if DEBUG_FPE 123 printf("fpu_emul_fscale: error in decode_ea\n"); 124 #endif 125 return sig; 126 } 127 128 if (insn->is_ea.ea_flags == EA_DIRECT && 129 insn->is_datasize > 4) { 130 #if DEBUG_FPE 131 printf("%s: attempted to fetch dbl/ext from reg\n", 132 __func__); 133 #endif 134 return SIGILL; 135 } 136 137 #if DEBUG_FPE 138 printf("fpu_emul_fscale: addr mode = "); 139 flags = insn->is_ea.ea_flags; 140 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 141 142 if (flags & EA_DIRECT) { 143 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7); 144 } else if (flags & EA_PREDECR) { 145 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7); 146 } else if (flags & EA_POSTINCR) { 147 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 148 } else if (flags & EA_OFFSET) { 149 printf("%c%d@(%d)\n", 150 regname, insn->is_ea.ea_regnum & 7, 151 insn->is_ea.ea_offset); 152 } else if (flags & EA_INDEXED) { 153 printf("%c%d@(...)\n", 154 regname, insn->is_ea.ea_regnum & 7); 155 } else if (flags & EA_ABS) { 156 printf("0x%08x\n", insn->is_ea.ea_absaddr); 157 } else if (flags & EA_PC_REL) { 158 printf("pc@(%d)\n", insn->is_ea.ea_offset); 159 } else if (flags & EA_IMMED) { 160 printf("#0x%08x%08x%08x\n", 161 insn->is_ea.ea_immed[0], 162 insn->is_ea.ea_immed[1], 163 insn->is_ea.ea_immed[2]); 164 } else { 165 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 166 } 167 #endif 168 sig = fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 169 if (sig) { 170 #if DEBUG_FPE 171 printf("fpu_emul_fscale: error in load_ea\n"); 172 #endif 173 return sig; 174 } 175 176 #if DEBUG_FPE 177 printf("fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 178 buf[0], buf[1], buf[2], insn->is_datasize); 179 #endif 180 if (format == FTYPE_LNG) { 181 /* nothing */ 182 scale = buf[0]; 183 } else if (format == FTYPE_WRD) { 184 /* sign-extend */ 185 scale = buf[0] & 0xffff; 186 if (scale & 0x8000) { 187 scale |= 0xffff0000; 188 } 189 } else if (format == FTYPE_BYT) { 190 /* sign-extend */ 191 scale = buf[0] & 0xff; 192 if (scale & 0x80) { 193 scale |= 0xffffff00; 194 } 195 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 196 format == FTYPE_EXT) { 197 fpu_explode(fe, &fe->fe_f2, format, buf); 198 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 199 scale = buf[0]; 200 } 201 /* make it look like we've got an FP oprand */ 202 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 203 } 204 205 /* assume there's no exception */ 206 sig = 0; 207 208 /* 209 * it's barbaric but we're going to operate directly on 210 * the dst operand's bit pattern 211 */ 212 sign = fpregs[regnum * 3] & 0x80000000; 213 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 214 m0 = fpregs[regnum * 3 + 1]; 215 m1 = fpregs[regnum * 3 + 2]; 216 217 switch (fe->fe_f2.fp_class) { 218 case FPC_SNAN: 219 fpsr |= FPSR_SNAN; 220 case FPC_QNAN: 221 /* dst = NaN */ 222 exp = 0x7fff; 223 m0 = m1 = 0xffffffff; 224 break; 225 case FPC_ZERO: 226 case FPC_NUM: 227 if ((0 < exp && exp < 0x7fff) || 228 (exp == 0 && (m0 | m1) != 0)) { 229 /* normal or denormal */ 230 exp += scale; 231 if (exp < 0) { 232 /* underflow */ 233 uint32_t grs; /* guard, round and sticky */ 234 235 exp = 0; 236 grs = m1 << (32 + exp); 237 m1 = m0 << (32 + exp) | m1 >> -exp; 238 m0 >>= -exp; 239 if (grs != 0) { 240 fpsr |= FPSR_INEX2; 241 242 switch (fe->fe_fpcr & 0x30) { 243 case FPCR_MINF: 244 if (sign != 0) { 245 if (++m1 == 0 && 246 ++m0 == 0) { 247 m0 = 0x80000000; 248 exp++; 249 } 250 } 251 break; 252 case FPCR_NEAR: 253 if (grs == 0x80000000) { 254 /* tie */ 255 if ((m1 & 1) && 256 ++m1 == 0 && 257 ++m0 == 0) { 258 m0 = 0x80000000; 259 exp++; 260 } 261 } else if (grs & 0x80000000) { 262 if (++m1 == 0 && 263 ++m0 == 0) { 264 m0 = 0x80000000; 265 exp++; 266 } 267 } 268 break; 269 case FPCR_PINF: 270 if (sign == 0) { 271 if (++m1 == 0 && 272 ++m0 == 0) { 273 m0 = 0x80000000; 274 exp++; 275 } 276 } 277 break; 278 case FPCR_ZERO: 279 break; 280 } 281 } 282 if (exp == 0 && (m0 & 0x80000000) == 0) { 283 fpsr |= FPSR_UNFL; 284 if ((m0 | m1) == 0) { 285 fpsr |= FPSR_ZERO; 286 } 287 } 288 } else if (exp >= 0x7fff) { 289 /* overflow --> result = Inf */ 290 /* 291 * but first, try to normalize in case it's an 292 * unnormalized 293 */ 294 while ((m0 & 0x80000000) == 0) { 295 exp--; 296 m0 = (m0 << 1) | (m1 >> 31); 297 m1 = m1 << 1; 298 } 299 /* if it's still too large, then return Inf */ 300 if (exp >= 0x7fff) { 301 exp = 0x7fff; 302 m0 = m1 = 0; 303 fpsr |= FPSR_OVFL | FPSR_INF; 304 } 305 } else if ((m0 & 0x80000000) == 0) { 306 /* 307 * it's a denormal; we try to normalize but 308 * result may and may not be a normal. 309 */ 310 while (exp > 0 && (m0 & 0x80000000) == 0) { 311 exp--; 312 m0 = (m0 << 1) | (m1 >> 31); 313 m1 = m1 << 1; 314 } 315 if ((m0 & 0x80000000) == 0) { 316 fpsr |= FPSR_UNFL; 317 } 318 } /* exp in range and mantissa normalized */ 319 } else if (exp == 0 && m0 == 0 && m1 == 0) { 320 /* dst is Zero */ 321 fpsr |= FPSR_ZERO; 322 } /* else we know exp == 0x7fff */ 323 else if ((m0 | m1) == 0) { 324 fpsr |= FPSR_INF; 325 } else if ((m0 & 0x40000000) == 0) { 326 /* a signaling NaN */ 327 fpsr |= FPSR_NAN | FPSR_SNAN; 328 } else { 329 /* a quiet NaN */ 330 fpsr |= FPSR_NAN; 331 } 332 break; 333 case FPC_INF: 334 /* dst = NaN */ 335 exp = 0x7fff; 336 m0 = m1 = 0xffffffff; 337 fpsr |= FPSR_OPERR | FPSR_NAN; 338 break; 339 default: 340 #ifdef DEBUG 341 panic("fpu_emul_fscale: invalid fp class"); 342 #endif 343 break; 344 } 345 346 /* store the result */ 347 fpregs[regnum * 3] = sign | (exp << 16); 348 fpregs[regnum * 3 + 1] = m0; 349 fpregs[regnum * 3 + 2] = m1; 350 351 if (sign) { 352 fpsr |= FPSR_NEG; 353 } 354 355 /* update fpsr according to the result of operation */ 356 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 357 358 #if DEBUG_FPE 359 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 360 fe->fe_fpsr, fe->fe_fpcr); 361 #endif 362 363 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 364 } 365
Indexes created Mon Nov 02 00:24:30 UTC 2026